max11253/max11254 ev kit-evaluates: max11253/max11254 · the ev kit board (table 2). 2) connect the...

Evaluates: MAX11253/MAX11254MAX11253/MAX11254 Family Evaluation Kit

General DescriptionThe MAX11253/MAX11254 evaluation kit (EV kit) pro-vides a proven design to evaluate the MAX11253/MAX11254 family of 16-bit/24-bit, 6-channel, 64ksps, integrated PGA delta-sigma ADCs. The EV kit includes a graphical user interface (GUI) that provides communi-cation from the target device to the PC. The EV kit can operate in multiple modes:1) Standalone Mode: in “standalone” mode, the EV

kit is connected to the PC via a USB cable and performs a subset of the complete EV kit functions with limitations for sample rate, sample size, and no support for coherent sampling.

2) FPGA Mode: in “FPGA” mode, the EV kit is connected to an Avnet ZedBoard™ through a low-pin-count FMC connector. ZedBoard features a Xilinx® Zynq® -7000 SoC, which connects to the PC through an Ethernet port, allowing the GUI to perform different operations with full control over mezzanine card functions. The EV kit with FPGA platform performs the complete suite of evaluation tests for the target IC.

3) User-Supplied SPI Mode: In addition to the USB and FMC interfaces, the EV kit provides a 12-pin Pmod™-style header for user-supplied SPI interface to con-nect the signals for SCLK, DIN, DOUT, and CNVST.

The EV kit includes Windows XP®, Windows® 7, and Windows 8.1-compatible software for exercising the fea-tures of the IC. The EV kit GUI allows different sample sizes, adjustable sampling rates, internal or external ref-erence options, and graphing software that includes the FFT and histogram of the sampled signals. The ZedBoard accepts a +12V AC-DC wall adapter. The EV kit can be powered by a local +12V supply. The EV kit has on-board transformers and digital isolators to sepa-rate the IC from the ZedBoard/on-board processor. The MAX11253/MAX11254 EV kit comes installed with a MAX11253ATJ+ or MAX11254ATJ+ in a 32-pin TQFN-EP package.

Features ● High-Speed USB Connector, FMC Connector, and

Pmod-Style Connector ● 8MHz SPI Clock Capability through FMC Connector ● 8MHz SPI Clock Capability in Standalone Mode ● Various Sample Sizes and Sample Rates ● Collects Up to 1 Million Samples

(with FPGA Platform) ● Time Domain, Frequency Domain, and Histogram

Plotting ● Sync In and Sync Out for Coherent Sampling

(with FPGA Platform) ● On-Board Input Buffers: MAX9632 and MAX44205

(Fully Differential) ● On-Board Voltage References

(MAX6126 and MAX6070) ● Proven PCB Layout ● Fully Assembled and Tested ● Windows XP-, Windows 7-, and Windows

8.1-Compatible Software

Pmod is a trademark of Digilent Inc.ZedBoard is a trademark of Avnet, Inc. Xilinx and Zynq are registered trademarks and Xilinx is a regis-tered service mark of Xilinx, Inc. Windows and Windows XP are registered trademarks and reg-istered service marks of Microsoft Corporation.

Ordering Information appears at end of data sheet.

19-7584; Rev 2; 4/18

Maxim Integrated │ 2www.maximintegrated.com

Evaluates: MAX11253/MAX11254MAX11253/MAX11254 FamilyEvaluation Kit

MAX11253/11254 EV Kit Photo



Quick StartRequired Equipment

● MAX11253/MAX11254 EV kit ● +12V (500mA) power supply ● Micro-USB cable ● ZedBoard FPGA platform

(optional – NOT INCLUDED with EVKit) ● Function generator (optional) ● Windows XP, Windows 7, or Windows 8.1 PC with a

spare USB port

Note: In the following section(s), software-related items are identified by bolding. Text in bold refers to items direct-ly from the EV system software. Text in bold and under-line refers to items from the Windows operating system.

ProcedureThe EV kit is fully assembled and tested. Follow the steps below to verify board operation:1) Visit http://www.maximintegrated.com/evkitsoft-

ware to download the latest version of the EV kit soft-ware, MAX11253_54EVKITSetupV1.0.zip. Save the EV kit software to a temporary folder and uncompress the ZIP file.

2) Install the EV kit software and USB driver on your computer by running the MAX11253_54EVKitSetupV1.0.exe program inside the temporary folder. The program files are copied to your PC and icons are created in the Windows Start | Programs menu. At the end of the installation process the installer will launch the in-staller for the FTDIChip CDM drivers.

MAX11253/MAX11254 EV Kit Files

System Block Diagram

FILE DECRIPTION

MAX11253_54EVKitSetupV1.0.exe Application Program (GUI)

Boot.bin ZedBoard firmware

(SD card to boot Zynq)

http://www.maximintegrated.com/evkitsoftware

http://www.maximintegrated.com/evkitsoftware



For Standalone mode:1) Verify that all jumpers are in their default positions for

the EV kit board (Table 2).2) Connect the PC to the EV kit using a micro-USB ca-

ble.3) Connect the +12V adapter to the EV kit.4) Start the EV kit software by opening its icon in the

Start | Programs menu. The EV kit software appears as shown in Figure 1. From the Device menu select Standalone. Verify that the lower left status bar indi-cates the EV Kit hardware is Connected.

For FPGA mode (when connected to a Zedboard):1) Connect the Ethernet cable from the PC to the Zed-

Board and configure the Internet Protocol Version 4 (TCP/Ipv4) properties in the local area connec-tion to IP address 192.168.1.2 and subnet Mask to 255.255.255.0.

2) Verify that the ZedBoard SD card contains the Boot.bin file for the MAX11253/MAX11254 EV kit.

3) Connect the EV kit FMC connector to the ZedBoard FMC connector. Gently press them together.

4) Verify that all jumpers are in their default positions for the ZedBoard (Table 1) and EV kit board (Table 2).

5) Connect the 12V power supply to the ZedBoard. Leave the Zedboard powered off.

6) Enable the ZedBoard power supply by sliding SW8 to ON and connect the +12V adapter to the EV kit.

7) Start the EV kit software by opening its icon in the Start | Programs menu. The EV kit software appears as shown in Figure 1. From the Device menu select FPGA. Verify that the lower left status bar indicates the EV Kit hardware is Connected.

For Either Standalone or FPGA Mode:1) Connect the positive terminal of the function genera-

tor to the AIN0D+ (TP1) test point on the EV kit. Con-nect the negative terminal of the function generator to the AIN0D- (TP2) test point on the EV kit.

2) Configure the signal source to generate a 100Hz, 1VP-P sinusoidal wave with +1V offset.

3) Turn on the function generator.4) In the Device menu, choose either standalone or the

FPGA option. In the configuration group, select Chan-nel 0 and click Convert in the serial interface menu.

5) Click on the Scope tab.6) Check the Remove DC Offset checkbox to remove

the DC component of the sampled data.7) Click the Capture button to start the data analysis.8) The EV kit software appears as shown in Figure 1.9) Verify that the frequency, which is displayed on the

right, is approximately 100Hz. The scope image has buttons in the upper right corner that allow zooming in to detail.

Table 1. ZedBoard Jumper Settings JUMPER SHUNT POSITION DESCIPTION

J18 1-2 VDDIO set for 3.3V.

JP11JP10JP9JP8JP7

2-31-21-22-32-3

Boot from SD Card

J12 NA SD Card installed

J20 NA Connected to 12V wall adapter

SW8 OFF ZedBoard power switch, OFF while connecting boards



Table 2. MAX11253/MAX11254 Board Jumper Settings

HEADER JUMPER POSITION DESCRIPTION

JMP1

1-2* Use MAX6126 3.0V as VREF signal

1-3 Use MAX6070 3.0V as VREF signal

1-4 Use MAX6070 1.8V as VREF signal

J8Open* Generate +3.3V for DVDD

1-2 Generate +2.0V for DVDD

J101-2* Select +3.3V or +2.0V as DVDD2-3 Select +1.8V as DVDD

J11Open* U1 uses internal clock

1-2 External clock from FPGA2-3 External clock from U10

J121-2* Select +3.3V as AVDD2-3 Select +1.8V as AVDD

J131-2* Select AVSS as REFN

2-3 Select REFN_S from J1 as REFN for external sense point

J14Open* Use internal 1.8V subregulator if

DVDD ≥ 2.0V

1-2 Use DVDD for internal logic if DVDD ≤ 2.0V

J15Open* Use TP23 as GPIO1

1-2 Use external SYNC signal

J161-2* Select REFP_F signal as REFP

input

2-3 Select REFP_S signal from J1 as REFP input

J171-2* Use AGND as AVSS. Use this

setting if AVDD is +3.3V

2-3 Use -1.8V as AVSS. Use this setting if AVDD is +1.8V

J241-2* Use VREF as REFP_F2-3 Use AVDD as REFP_F

J31

1-2*Short AIN2.1- (J27, TP38) to AGND and for U11 noninverting configuration

3-4*Short AIN2.1+ (J28, TP39) to AGND and for U11 inverting configuration


J32

1-2*Short AIN2.3- (J29, TP42) to AGND and for U12 noninverting configuration

3-4*Short AIN2.3+ (J30, TP43) to AGND and for U12 inverting configuration

J33

1-2*Short AIN2.2- (TP40) to AGND and for U13 noninverting configuration

3-4*Short AIN2.2+ (TP41) to AGND and for U13 inverting configuration

J34



J35

1-2* Connect output of U11 to inverting input of U13

3-4 Connect AIN2.2- (TP40) to inverting input of U13

5-6 Connect output of U11 to noninverting input of U13

7-8* Connect AIN2.2+ (TP41) to noninverting input of U13

J36





J37Open* No offset to U13 noninverting

input

1-2 Offset U13 output by VREF/2


input




*Default configuration

Table 2. MAX11253/MAX11254 Board Jumper Settings (continued)


J39



J40



J41



J42



J43





J44






input




input


J491-2* Short AIN4+ (J47, TP72) to

AGND

3-4* Short AIN4- (J48, TP73) to AGND

J501-2* Short AIN5+ (TP74) to AGND

3-4* Short AIN5- (TP75) to AGND

J63Open* Use external +12V source

1-2 Use +12V from ZedBoard

J64Open If connected to ZedBoard FPGA

1-2* If connected to PC through USB interface

J65

1-2*Enable U28 H-bridge transformer driver to use onboard ±15V supply generation

2-3Disable U28 and use and external ±15V supply to TP83, TP86, and TP87

J661-2 Use an external -15V power

supply, connected to TP86

3-4* Use U28 driver to generate isolated -15V

J671-2 Use an external +15V power

supply, connected to TP83

3-4* Use U28 driver to generate isolated +15V

J681-2 Use an external +12V power

supply to TP91 as VCC

3-4* Use onboard +12V from U32 LDO as VCC

J69

1-2 AGND as VEE

3-4 Use an external -12V power supply to TP90 as VEE

5-6* Use onboard -12V from U33 LDO as VEE



General Description of SoftwareThe main window of the EV kit software contains seven tabs: Configuration, Scope, DMM, Histogram, FFT, Scan Mode, and Registers. The Configuration tab provides control for the ADC configuration including calibration and data capture. The other six tabs are used for evaluating the data captured by the ADC.

Configuration TabThe Configuration tab provides an interface for selecting and configuring the ADC from a functional perspective. Select the desired Device for either Standalone or FPGA in the dropdown menu and the corresponding properties of the device are displayed including Channel number, Sample Rate, Number of Samples, Reference Voltage, Sequencing Mode, Calibration, GPO/GPIO selec-tion, Input Path (Direct or internal PGA), Delta-Sigma Modulator type selection for different Data Format and Conversion Mode, Serial Interface function (Convert, and Read All), Power setting (NOP, Power Down, and

Standby), Reset Registers, and RSTB Reset, Clock/SYNC (Internal or External Clock, and Disable or Enable SYNC Mode), and Other for Disable or Enable Current Sink/Source and CAPREG LDO.The sample settings are available on the left of the config-uration menu, which allow the user to select the Channel, Sample Rate, Number of Samples and Clock Source if FPGA device is used.The Read Data and Status information is displayed on the right, which shows the data in both voltage and Hex, the sample rate, and power state for the selected chan-nel. In addition, if there are any errors, the indicator lights will turn red.

Channel SelectionTo select the desired channel among the six available channels, click Channel # dropdown menu at the top left and select the desired channel from 0 to 5. The default selection is Channel 0.

Figure 1. EV Kit Software (Configuration Tab)



Sample Rate (SPS)To select the desired data rate for single-cycle mode from 50sps to 12800sps and for continuous mode data rate from 1.9sps to 64000sps, choose the Sample Rate (SPS) from the dropdown menu below the Channel # selection.

Reference VoltageThere are three different reference voltages available on board: MAX6070AUT18+ (1.8V), MAX6070AUT30+ (3.0V), and MAX6126AASA30+ (3.0V). To select 1.8V, place JMP1 from position 1 to 4. To select 3.0V MAX6070 with ±0.04% accuracy, place JMP1 from position 1 to 3. To select 3.0V MAX6126 with ±0.02% accuracy, place JMP1 from position 1 to 2.

Sequencer ModeTo change the sequencer mode, click the Sequence Mode selection below the Sequencing menu and select Mode 1, 2, or 3 as desired. Check the GPO Sequencer Mode box to enable GPO/GPIO function in mode 3. In addition, check the Enable box to enable the MUX and GPO Delay. Choose the desired delay in microseconds by clicking on the + or – buttons.

ADC CalibrationTwo types of software calibration for offset and gain are available: Self calibration and system calibration.The primary mode for calibration is using the dropdown list to select a calibration mode, followed by clicking the Calibrate button. The checkboxes for Self Offset, Self Gain, System Offset, and System Gain allow for the user to enable or disable the calibration values. The cali-bration values can also be changed manually by entering a hex value in the numeric box.

GPO/GPIOTo select GPO or GPIO ports, choose the option under the GPO/GPIO dropdown menu and check the Enable box.

Input PathSelect Direct under the Input Path dropdown menu to bypass the internal amplifiers and apply the analog input signals directly to the MAX11253/MAX11254 inputs or to use the external amplifiers.Select PGA under the Input Path dropdown menu to use the internal programmable gain amplifiers.

Delta-Sigma ModulatorTo select the desired data format, click the Data Format dropdown menu under the Delta-Sigma Modulator section and choose either Bipolar or Unipolar with two’s complement or offset binary options.

Three conversion modes are provided: Continuous, Single Cycle, and Single Continuous. Click the Conversion Modes dropdown menu under the Delta-Sigma Modulator section to select the desired conver-sion mode.

Serial InterfaceTo starting converting, click the Convert button under the Serial interface section. To read all registers, click the Read All button.

PowerThe MAX11253/MAX11254 EV kit features three power-down states: Normal Operating Power (NOP), Power down, and Standby. Select the desired power state by clicking the drop-down menu under the Power section.To reset the configuration settings back to default values, press the Reset Registers button.To exercise the power-on reset feature, click the RSTB button.

Clock/SYNCThe internal clock mode is set at default condition. To use the external clock provided on-board, select External under the Clock/SYNC section and install jumper J11 from 2-3. To user-supplied external clock, select External under the Clock/SYNC section and install jumper J11 from 1-2. In addition, the Sync mode can be enabled or disabled by clicking the drop-down menu under this Clock/SYNC section and install jumper J15. The Sync signal should be provided externally.

OtherTo enable (J14 open) or disable (J14 installed and VDDVD ≤ 2.0V) the internal CAPREG LDO for digital and I/O sup-ply, select this option from the drop-down menu under the Other section. Additionally, Current Sink/Source can also be disabled or enabled under this section.

Read Data and StatusThe Read Data and Status on the far right hand side of this Configuration menu depicts the received data and status of the device such as the selected channel, data rate, sample rate, and power state. Click the Read Data and Status button to view the updated status.To save a configuration, select Save ADC Config As… in the File menu. This saves all the ADC register values to a XML file. To load a configuration, select Load ADC Config in the File menu. When the XML file is loaded, all the reg-ister values in the file are written to the ADC.



Scope TabThe Scope tab sheet is used to capture data and display it in the time domain. The desired Channel #, Sample Rate, Number of Samples, Display Unit, Average Samples, and Resolution Selection can also be set in this tab if they were not appropriately adjusted in other tabs. The Display Unit drop-down list allows counts in LSB and voltages in V, mV, or µV. Once the desired configuration is

set, click on the Capture button. The right side of the tab sheet displays details of the waveform, such as average, standard deviation, maximum, minimum, and fundamen-tal frequency as shown in Figure 2.To save the captured data to a file, select Options > Save Graph > Scope. This saves the setting on the left and the data captured to a CSV file.

Figure 2. EV Kit Software (ScopeTab)



DMM TabThe DMM tab sheet provides the typical information as a digital multimeter. Once the desired configuration is set,

click on the Capture button. Figure 3 displays the results shown by the DMM tab when a 1.5V signal is applied to AIN0+ and 1.0V to AIN0-.

Figure 3. EV Kit Software (DMM Tab)



Histogram TabThe Histogram tab sheet is used to show the histogram of the data. Sample rate and number of samples can also be set in this tab if they were not appropriately adjusted in other tabs. Once the desired configuration is set, click on the Capture button. The right side of the tab sheet displays details of the histogram such as average, stan-dard deviation, maximum, minimum, peak-to-peak noise, effective resolution, and noise-free resolution as shown in Figure 4.

The histogram tab is enabled at default. Using the his-togram will slow down the GUI response. To disable it, check the Disable Histogram box.To save the histogram data to a file, go to Options > Save Graph > Histogram. This saves the setting on the left and the histogram data captured to a CSV file.

Figure 4. EV Kit Software (Histogram Tab)



FFT TabThe FFT tab sheet is used to display the FFT of the data. The Sample Rate, Number of Samples, Resolution and Window Function type can be set as desired. To calcu-late the Adjusted Input Signal frequency for Coherent Sampling, enter the Input Signal frequency in Hertz and push the Calculate button. Once the preferred configura-tion is set, click on the Capture button. The right side of the tab displays the performance based on the FFT, such as fundamental frequency, SNR, SINAD, THD, SFDR, ENOB, and Noise Floor as shown in Figure 5.

To save the FFT data to a file, go to Options > Save Graph > FFT. This saves the setting on the left and the FFT data captured to a CSV file.When coherent sampling is needed, this tab allows the user to calculate the external clock frequency applied to the board. Adjust the input frequency of the low-jitter clock to the value as shown in the Adjusted Master Clock (Hz) and apply it to the EV KIT EXT_CLK connector. See the Sync Input and Sync Output section before using this feature.

Figure 5. EV Kit Software (FFT Tab)



Figure 6 shows the setup Maxim Integrated uses to cap-ture data for coherent sampling.For coherent FFT evaluation, use the jumper settings from Table 2 for proper configurations. The low-jitter clock is synchronized with the signal generator at 10MHz from the ZedBoard. To achieve coherent sampling, click on the

Calculate button and enter the Adjusted Master Clock (Hz) frequency of approximately 8.192MHz into our low-jitter clock. Timing for all SPI timing and sampling rate are based off the system clock.

Figure 6. EV Kit Coherent Sampling Setup

LOW-JITTER CLOCK

SIGNAL GENERATOR

-

+

OUT

INV-

INV+

EXT_CLK

10MHz

ZedBoard

8.192 MHz

ETHERNET CABLE

MAX11253/MAX11254EVKIT

RF_IN

RF_IN

PC



Scan Mode TabThe Scan Mode tab is used to perform selected data conversions and read the converted data.In the Sequence Setting section at the bottom, set the desired sequencer mode (1 to 3) from the Sequence Mode drop-down menu and select whether to assert the RDYB pin after one channel or after scan com-pletes options under the RDYB menu. Check the GPO Sequencer Mode and Enable boxes as desired. Then set the conversion time delay in µs for MUX and GPO by clicking on the + or - buttons under the MUX Delay and GPO Delay menu, allowing for high impedance source networks to stabilize after the channels are selected. Finally press the Read All button to view the selected settings.

In the Read Data section on top, select the desired unit in either LSB or voltage (V, mV, or µV) under the Display Unit drop-down menu. Then choose the desired sample rate by clicking on the Sample Rate drop-down menu under. Finally, click the Scan button to start convert-ing and press the Read Data button to view the con-verted data displayed on the right hand side as shown in Figure 7.

Figure 7. EV Kit Software (Scan Mode Tab)



ADC Registers TabThe Registers tab sheet shows the device registers on the left. The middle section shows the descriptions of the selected register. Click Read All to read all registers and refresh the window with the register settings. To write a register first select the hex value in the Value column, type the desired hex value and press Enter.The command byte is on the right side of the tab sheet. This byte precedes all SPI transactions and is described in the IC datasheet. To send a command byte enter a hex value in the numeric box and click the Send button. The command byte has two different formats includ-ing Conversion Command and Register Read/Write. Select the radio button for the desired mode to see the bit description in the table. See Figure 8.

Detailed Description of HardwareThe MAX11253/MAX11254 EV kit provides a proven signal path and board layout to demonstrate the performance of the MAX11253/MAX11254 16-/24-bit, delta-sigma ADCs. Included in the EV kit are digital isolators, isolated DC-DC converters, ultra-low-noise LDOs to all supply pins of the IC, on-board reference (MAX6126 and MAX6070), preci-sion amplifiers (MAX9632 and MAX44205) for analog inputs, and sync-in and sync-out signals for coherent sampling.An on-board FTDI controller is provided to allow for evaluation in standalone mode, which has limitations on maximum sample speed and on sample depth. The EV kit can be used with FPGA to achieve full speed and a larger sample depth.The EV kit supports a number of different devices as listed in Table 3.

Figure 8. EV Kit Software (ADC Registers Tab)

Table 3. Products Supported with MAX11253/MAX11254 EV KitPART NO. RESOLUTION MAX. SAMPLE RATEMAX11253 16-bits 64kspsMAX11254 24-bits 64ksps



User-Supplied SPITo evaluate the EV kit with a user-supplied SPI bus, disconnect from the FMC bus and remove jumper J64. Apply the user-supplied SPI signals to SCLK, CSB, DIN, and DOUT at the PMOD_A header (J60). Make sure the return ground is connected to PMOD ground.The on-board FTDI chip used for standalone mode does not conflict with the user-supplied SPI if it is powered off by removing jumper J64.CAUTION: DO NOT PLUG THIS HEADER INTO A STANDARD PMOD INTERFACE FOUND ON OTHER FPGA OR MICROCONTROLLER PRODUCTS. THE SIGNAL DEFINITION IS UNIQUE TO THIS EV KIT.

FMC Interface:The users should confirm compatibility of pin-usage between their own FMC implementation and that of the Maxim Integrated EV kit before connecting the Maxim Integrated EV kit to a different system with FMC connectors.

Voltage ReferencesThere are three different reference voltages available on board: MAX6070AUT18+ (1.8V), MAX6070AUT30+ (3.0V), and MAX6126AASA30+ (3.0V). To select 1.8V, place JMP1 from position 1 to 4. To select 3.0V MAX6070 with ±0.04% accuracy, place JUMP1 from position 1 to 3. To select 3.0V MAX6126 with ±0.02% accuracy, place JMP1 from position 1 to 2.For user-supplied external references, remove jumper J24 and connect a reference voltage to J24-2. Measure and enter the value of the external reference voltage into the Reference Voltage edit box on the Configuration tab of the GUI. Table 3 depicts the reference source options.

External DVDD Power SupplyThe internal 1.8V regulator can be replaced by an exter-nal supply in the range of 1.7V to 2.0V. To use external DVDD, disable the internal regulator by selecting the Disable in the CAPREG LDO drop-down menu in the Other section and install J14.

User-Supplied Power SupplyThe EV kit receives power from a single DC source of 12V, 500mA through a J61 power jack. The MAX13256, H-bridge driver and transformer create an additional negative rail for +15V and -15V. The power is then recti-fied and regulated down to a +12V and -12V supplies for the MAX9632 op amps, as well as +5V and -5V supplies for the MAX44205 op amps. Additional supplies are gen-erated for +1.8V/-1.8V and +2V/+3.3V for the ADCs and VREFs. See the EV kit schematic pdf for details. Specific

voltages can be connected to the board for each rail, see Table 4 for corresponding jumper positions.

ADC Input AmplifiersThe input amplifiers allow for significant flexibility, support-ing bipolar or unipolar input paths, as well as the option for gain control. Selected input amplifiers can be config-ured as inverting, noninverting, differential bipolar, and differential unipolar. See Table 5 for these analog input configurations for channels 0 to 5.The analog front-end consists of six channels, 0 to 5, and there are four user-selectable input pairs (for example AINx+ and AINx- where x is 2, 3, 4 or 5) allowing selec-tion between one of two op amp solutions, the MAX9632 a 36V, precision, low-noise, wide-band amplifier or the MAX44205, a 180MHz, low-noise, low-distortion, fully differential op amp. The op amps can be configured as inverting or noninverting amplifiers by jumper selectors. Both op amps work as anti-aliasing lowpass filters (LPF) and can be daisy-chained to create a second-order LPF.The range of possible configurations are listed in Table 5.

Table 4. Reference Source OptionsREF

SOURCE JUMPER CONNECTION FUNCTION

MAX6070 (1.8V)

JMP1 1-4

Select U7 MAX6070

J13 1-2J16 1-2J24 1-2

MAX6070 (3.0V)

JMP1 1-3

Select U8 MAX6070

J13 1-2J16 1-2J24 1-2

MAX6126 (3.0V)

JMP1 1-2

Select U9 MAX6126

J13 1-2J16 1-2J24 1-2

AVDDJ13 1-2

Select AVDDJ16 1-2J24 2-3

User-Supplied

J13 1-2

Select User-Supplied Reference

J16 1-2

J24

Open. Connect user-supplied

reference to J24-2



Table 5. Power Supply to the Board

Table 6. Analog Input Configurations (CH0–CH5)

POWER INPUT CONNECTORS JUMPERS

Single +12V input from a wall adapter (default) J61

J67: 3-4J66: 3-4J68: 3-4J69: 5-6J65: 1-2J64: 1-2 (select onboard FTDI)J63: 1-2 (select FPGA ZedBoard)

An external ±12V TP91 (+12V)TP90 (-12V)


An external ±15V TP86 (+15V)TP83 (-15V)


CONFIGURATION ADC INPUT CONFIGURATION INPUT CONNECTORS JUMPER POSITIONS

NO. DESCRIPTION

1 Channel 0 User-supplied signals, differential AIN0D+, AIN0D- N/A

2 Channel 1 User-supplied signals, differential AIN1D+, AIN1D- N/A

3 MAX9632, Channel 2 Noninverting, differential, second-order LPF

J28: AIN2.1+ (or TP39): AIN2.1+ and AGNDJ30: AIN2.3+ (or TP43): AIN2.3+ and AGND

J31: 1-2 J35: 5-6 and 3-4 J33: 1-2J32: 1-2J36: 5-6 and 3-4 J34: 1-2 J4: 3-4 and 5-6J37: 1-2 (for bipolar signalor open for unipolar signal)J38: 1-2 (for bipolar signalor open for unipolar signal)



Table 6. Analog Input Configurations (CH0–CH5) (continued)CONFIGURATION ADC INPUT

CONFIGURATION INPUT CONNECTORS JUMPER POSITIONSNO. DESCRIPTION

4 MAX9632, Channel 2 Inverting, differential, second-order LPF

J27: AIN2.1- (or TP38): AIN2.1- and AGNDJ29: AIN2.3- (or TP42): AIN2.3- and AGND

J31: 3-4 J35: 1-2 and 7-8 J33: 3-4J32: 3-4J36: 1-2 and 7-8J34: 3-4 J4: 3-4 and 5-6J37: 1-2 (for bipolar signalor open for unipolar signal)J38: 1-2 (for bipolar signalor open for unipolar signal)

5 MAX9632, Channel 2 Noninverting, differential, first-order LPF

AIN2.2+ (or TP41): AIN2.2+ and AGNDAIN2.4+ (or TP45): AIN2.4+ and AGND

J35: 7-8 and 3-4J33: 1-2J34: 1-2J36: 7-8 and 3-4 J4: 3-4 and 5-6J37: 1-2 (for bipolar signalor open for unipolar signal)J38: 1-2 (for bipolar signalor open for unipolar signal)

6 MAX9632, Channel 2 Inverting, differential, first-order LPF

AIN2.2- (or TP40): AIN2.2- and AGNDAIN2.4- (or TP44): AIN2.4- and AGND

J35: 7-8 and 3-4J33: 3-4J34: 3-4J36: 7-8 and 3-4 J4: 3-4 and 5-6J37: 1-2 (for bipolar signalor open for unipolar signal)J38: 1-2 (for bipolar signalor open for unipolar signal)

7 MAX9632, Channel 3 Noninverting, differential, second order LPF





Table 6. Analog Input Configurations (CH0–CH5) (continued)CONFIGURATION ADC INPUT

CONFIGURATION INPUT CONNECTORS JUMPER POSITIONSNO. DESCRIPTION

8 MAX9632, Channel 3 Inverting, differential, second-order LPF



9 MAX9632, Channel 3 Noninverting, differential, first-order LPF


J43: 7-8 and 3-4J41: 1-2J44: 7-8 and 3-4 J42: 1-2J5: 3-4 and 5-6J45: 1-2 (for bipolar signalor open for unipolar signal)J46: 1-2 (for bipolar signalor open for unipolar signal)

10 MAX9632, Channel 3 Inverting, differential, first-order LPF


J43: 7-8 and 3-4J41: 3-4J44: 7-8 and 3-4 J42: 3-4J5: 3-4 and 5-6J45: 1-2 (for bipolar signalor open for unipolar signal)J46: 1-2 (for bipolar signalor open for unipolar signal)

11 MAX44205, Channel 4 Differential, first-order LPF

J48: AIN4- (or TP73): AIN4- and AGNDJ47: AIN4+ (or TP72): AIN4+ and AGND

J6: 3-4 and 5-6J49: open

12 MAX44205, Channel 5 Differential, first-order LPF

AIN5+ (or TP74): AIN5+ and AGNDAIN5- (or TP75): AIN5- and AGND

J7: 3-4 and 5-6J50: open



Sync Input and Sync Output (For Coherent Sampling)Sync Input and Sync Output is applicable to the FPGA (ZedBoard) and is not used in Standalone mode. The SYNC_IN SMA accepts an approximate 100MHz wave-form signal to generate the system clock of the ZedBoard. For maximum performance, use a low-jitter clock that syncs to the user’s analog function generator. The SYNC_OUT SMA outputs a 10MHz square waveform that syncs to the user’s analog function generator. Both options are used for coherent sampling of the IC. Use only one option at a time. The relationship between fIN, fS, NCYCLES, and MSAMPLES is given as follows:

CYCLESIN

S SAMPLES

Nf

f M=

where:fIN = Input frequencyfS = Sampling frequencyNCYCLES = Prime number of cycles in the sampled setMSAMPLES = Total number of samples

#Denotes RoHS compliant.

Contact Avnet to purchase a ZedBoard to communicate with the MAX11253/MAX11254 EV kit.

This EV kit comes with two assembly options:The MAX11253EVKIT# comes with a MAX11253ATJ+ in a 32-pin TQFN package.The MAX11254EVKIT# comes with a MAX11254ATJ+ in a 32-pin TQFN package..Both EV kit variations use the same PCB and bill of mate-rials, and the only variation is the IC assembled at U1.

Ordering InformationPART TYPE

MAX11253EVKIT# EVKIT

MAX11254EVKIT# EVKIT



MAX1153/MAX11254 Family EV Kit Bill of Materials

ITEM

QTY

REF

DES

MFG

PAR

T #

MFG

VALU

EC

OM

MEN

TS

132

TP13

, TP1

5-TP

18, T

P20,

TP2

2, T

P27,

TP2

9, T

P31,

TP3

3, T

P35-

TP37

, TP4

6, T

P52-

TP54

, TP6

4, T

P65,

TP7

0, T

P71,

TP7

6, T

P80,

TP

82, T

P85,

TP87

,TP8

9,TP

93-T

P95,

GN

D_F

PGA

5001

TDK

N/A

263

C1-

C3,

C7-

C9,

C19

, C21

-C23

, C27

, C28

, C31

, C33

, C40

, C41

, C

44, C

45, C

52, C

53, C

56, C

57, C

64, C

65, C

68, C

69, C

76, C

77,

C80

-C84

, C95

, C96

, C99

, C10

0, C

116-

C11

8, C

121,

C12

2, C

125,

C

128,

C12

9, C

132,

C13

5, C

137-

C14

3, C

146,

C14

7, C

155,

C16

6-C

168,

C17

6, C

184,

C18

7C

1608

X7R

1H10

4K08

0AA

TDK

0.1U

F

341

C4-

C6,

C20

, C26

, C29

, C30

, C38

, C39

, C42

, C43

, C50

, C51

, C54

, C

55, C

62, C

63, C

66, C

67, C

74, C

75, C

78, C

79, C

93, C

94, C

97,

C98

, C11

3, C

114,

C11

9, C

120,

C12

3, C

124,

C14

4, C

145,

C15

2-C

154,

C17

3, C

174,

C18

6U

MK1

07AB

7105

KATA

IYO

YU

DEN

1UF

46

C10

-C15

C16

08C

0G2A

332J

080A

ATD

K33

00PF

511

C16

-C18

, C32

, C15

0, C

157,

C15

8, C

163,

C16

4, C

169,

C17

0C

2012

X7R

1E47

5K12

5AB

TDK

4.7U

F6

3C

24, C

126,

C12

7C

0603

C10

2K1G

ACKE

MET

1000

PF

728

C25

, C34

-C37

, C46

-C49

, C58

-C61

, C70

-C73

, C15

6, C

159,

C16

2,

C16

5, C

171,

C17

2, C

175,

C17

7-C

179,

C18

5C

1608

C0G

1H10

3J08

0AA

TDK

0.01

UF

88

C85

-C92

C16

08C

0G1H

472J

080A

ATD

K47

00PF

94

C11

5, C

130,

C13

1, C

136

C16

08X5

R1E

475K

080A

CTD

K4.

7UF

102

C13

3, C

134

C06

03H

QN

101-

180F

NP

KEM

ET/V

ENKE

L18

PF

119

C14

8, C

149,

C16

0, C

161,

C18

0-C

183,

C18

8C

2012

X5R

1V10

6K08

5TD

K10

UF

121

C15

1G

RM

188R

71E4

74KA

12M

UR

ATA

0.47

UF

131

D1

MBR

0520

LFA

IRC

HIL

D

SEM

ICO

ND

UC

TOR

MBR

0520

L14

2D

2, D

3BA

S400

2A-R

PPIN

FIN

EON

BAS4

002A

-RPP

152

DS1

, DS2

LGL2

9K-G

2J1-

24-Z

OSR

AMLG

L29K

-G2J

1-24

-Z

161

DS3

LS L

29K-

G1J

2-1-

ZO

SRAM

LS L

29K-

G1J

2-1-

Z17

3J1

, J25

, J26

1282

834-

0TY

CO

ELE

CTR

ON

ICS

1282

834-

018

2J2

, J3

2828

34-4

TYC

O E

LEC

TRO

NIC

S28

2834

-4

194

J4-J

7PE

C04

DAA

NSU

LLIN

S EL

ECTR

ON

ICS

CO

RP.

PEC

04D

AAN

201

J8PC

C02

SAAN

SULL

INS

PCC

02SA

AN21

9J1

0-J1

3, J

16, J

17, J

24, J

52, J

65PC

C03

SAAN

SULL

INS

PCC

03SA

AN22

10J2

7-J3

0, J

47, J

48, J

54, J

56-J

585-

1814

832-

1TY

CO

5-18

1483

2-1

2311

J31-

J34,

J39

-J42

, J66

-J68

PBC

02D

AAN

SULL

INS

ELEC

TRO

NIC

C

OR

P.PB

C02

DAA

N

244

J35,

J36

, J43

, J44

PBC

04D

AAN

SULL

INS

ELEC

TRO

NIC

S C

OR

P.PB

C04

DAA

N

252

J49,

J50

PEC

02D

AAN

SULL

INS

ELEC

TRO

NIC

C

OR

P.PE

C02

DAA

N

261

J51

PBC

10SA

ANSU

LLIN

S EL

ECTR

ON

ICS

CO

RP.

PBC

10SA

AN27

1J5

3AS

P-13

4604

-01

SAM

TEC

ASP-

1346

04-0

128

1J5

910

1181

92-0

001L

FFC

I CO

NN

ECT

1011

8192

-000

1LF

MIC

RO

-USB

291

J61

KLD

X-02

02-B

KYC

ON

KLD

X-02

02-B



MAX1153/MAX11254 Family EV Kit Bill of Materials (continued)

ITEM

QTY

REF

DES

MFG

PAR

T #

MFG

VALU

EC

OM

MEN

TS30

1J6

228

2834

-2TE

CO

NN

ECTI

VITY

2828

34-2

311

J69

PEC

03D

AAN

SULL

INS

ELEC

TRO

NIC

S C

OR

P.PE

C03

DAA

N32

1JM

P122

-28-

4043

MO

LEX

22-2

8-40

4333

1L1

MM

Z160

8B60

1CTD

K60

034

4L2

-L5

XPL2

010-

333M

LC

OIL

CR

AFT

33U

H

354

R1-

R4

RN

73C

1J49

R9B

; 9-1

6143

53-1

TE C

ON

NEC

TIVI

TY49

.9

3612

R5,

R8-

R14

, R52

, R53

, R93

, R94

RN

73C

1J10

RBT

G; 1

6143

50-2

TE C

ON

NEC

TIVI

TY10

371

R6

CR

CW

0603

237K

FK;

ERJ3

EKF2

373V

VISH

AY

DAL

E/PA

NAS

ON

IC23

7K38

6R

7, R

197,

R19

9, R

201,

R20

3, R

205

ERJ3

EKF7

322V

PAN

ASO

NIC

73.2

K

3914

R15

, R17

1, R

172,

R17

5-R

179,

R18

1-R

186

CR

CW

0603

10K0

FK;

9C06

031A

1002

FK; E

RJ-

3EKF

1002

VVI

SHAY

D

ALE/

PAN

ASO

NIC

10K

406

R16

, R17

, R16

2, R

164,

R16

6, R

167

CR

CW

0603

49R

9FK

VISH

AY D

ALE

49.9

413

R18

, R19

, R19

5

CR

CW

0603

1001

FK;

CR

CW

0603

1K00

FK; E

RJ-

3EKF

1001

VVI

SHAY

D

ALE/

PAN

ASO

NIC

1K

4216

R20

-R27

, R54

-R61

CR

CW

0603

1M00

FK;

MC

R03

EZPF

X100

4VI

SHAY

DAL

E/R

OH

M1M

4340

R28

-R35

, R40

-R43

, R46

-R49

, R62

-R69

, R81

-R84

, R87

-R90

, R97

-R

104

RG

1608

N-1

02-B

-T1

SUSU

MU

CO

LTD

.1K

4412

R36

-R39

, R50

, R51

, R70

-R72

, R80

, R91

, R92

CR

0603

-16W

-000

T; C

R06

03-

16W

-000

RJT

VEN

KEL

LTD

.0

454

R44

, R45

, R85

, R86

TNPW

0603

1K50

BE; E

RA-

3YEB

152V

PAN

ASO

NIC

1.5K

4644

R73

-R79

, R10

5, R

111-

R11

7, R

139-

R16

1, R

168,

R16

9, R

187-

R19

0ER

J-3E

KF28

R0V

PAN

ASO

NIC

28

472

R95

, R96

TNPW

0603

10K0

BE;

RN

731J

TTD

1002

BVI

SHAY

DAL

E/KO

A SP

EER

ELE

CTR

ON

ICS

10K

482

R16

3, R

165

CR

CW

0603

0000

ZS;

MC

R03

EZPJ

000;

ER

J-3G

EY0R

00V

VISH

AY D

ALE

049

1R

170

CR

CW

0603

15K0

FKVI

SHAY

DAL

E15

K50

1R

173

CR

CW

0603

2K20

FKVI

SHAY

DAL

E2.

2K51

1R

174

CR

CW

0603

12K0

FKVI

SHAY

DAL

E12

K52

1R

180

CR

CW

0603

4K70

FKVI

SHAY

DAL

E4.

7K

532

R19

1, R

194

PAN

ASO

NIC

;CR

CW

0603

200

2FK;

MC

R03

EZPF

X200

2;ER

J-3E

KF20

02V

VISH

AY D

ALE/

RO

HM

20K

541

R19

2C

RC

W06

0375

0KFK

VISH

AY D

ALE

750K

551

R19

3C

RC

W06

0316

5KFK

VISH

AY D

ALE

165K

561

R19

6ER

J-3E

KF38

32PA

NAS

ON

IC38

.3K

572

R19

8, R

200

ERJ3

EKF6

813V

PAN

ASO

NIC

681K

581

R20

2C

RC

W06

0310

R0F

K;

MC

R03

EZPF

X10R

0VI

SHAY

DAL

E/R

OH

M10

591

R20

4C

RC

W06

0312

4KFK

VISH

AY D

ALE

124K

6049

SU1-

SU49

SX11

00-B

KYC

ON

SX11

00-B

611

T1TG

M-H

240V

8LF

HAL

O E

LEC

TRO

NIC

S,

INC

TGM

-H24

0V8L

F

6258

TP1-

TP12

,TP1

4,TP

19,T

P21,

TP23

-TP2

6,TP

30,T

P38-

TP45

,TP4

8-TP

51,T

P56-

TP63

,TP6

6-TP

69,T

P72-

TP75

,TP7

7-TP

79,T

P81,

TP84

,TP8

6,TP

91,T

P92,

5V_T

TL50

00?

N/A



MAX1153/MAX11254 Family EV Kit Bill of Materials (continued)

641

U1

MAX

1125

4ATJ

+M

AXIM

MAX

1125

4ATJ

+65

1U

5M

AX14

935C

AWE+

MAX

IMM

AX14

935C

AWE+

661

U6

MAX

1493

5CAW

E+M

AXIM

MAX

1493

5CAW

E+M

AX14

931C

ASE

+67

1U

7M

AX60

70AA

UT1

8+M

AXIM

MAX

6070

AAU

T18+

681

U8

MAX

6070

AAU

T30+

MAX

IMM

AX60

70AA

UT3

0+69

1U

9M

AX61

26AA

SA30

+M

AXIM

MAX

6126

AASA

30

701

U10

LTC

6930

HD

CB-

8.19

LIN

EAR

TEC

HN

OLO

GY

LTC

6930

HD

CB-

8.19

718

U11

-U18

MAX

9632

AUA+

MAX

IMM

AX96

32AU

A+72

2U

19, U

20M

AX44

205

MAX

IMM

AX44

205

732

U21

, U22

74LV

C2G

125D

P?

74LV

C2G

125D

P74

2U

23, U

2493

LC66

BT-I/

OT

MIC

RO

CH

IP93

LC66

BT-I/

OT

751

U25

FT22

32H

LFU

TUR

E TE

CH

NO

LOG

Y D

EVIC

ES IN

TL L

TD.

FT22

32H

L76

2U

26, U

35M

AX15

006B

ATT+

MAX

IMM

AX15

006B

ATT+

771

U27

MAX

1691

0CAT

A9+

MAX

IMM

AX16

910C

ATA9

+78

1U

28M

AX13

256A

TB+

MAX

IMM

AX13

256A

TB+

791

U29

MAX

1500

6CAT

T+M

AXIM

MAX

1500

6CAT

T+

801

U30

MAX

8840

ELT1

8+M

AXIM

MAX

8840

ELT1

8+M

AX88

40EL

T18+

813

U31

, U33

, U34

TPS7

A300

1DG

NTE

XAS

INST

RU

MEN

TSTP

S7A3

001D

GN

821

U32

TPS7

A490

1DG

NTE

XAS

INST

RU

MEN

TSTP

S7A4

901D

GN

831

U36

MAX

1500

6AAT

T+M

AXIM

MAX

1500

6AAT

T+84

1Y1

ABM

7-12

.000

MH

Z-D

2Y-T

ABR

ACO

N12

MH

Z85

1PC

B E

PCB1

1254

M

AXIM

PC

B

635

TP28

,TP8

3,TP

88,T

P90,

TP96

5004

?N

/AIT

EMQ

TYR

EF D

ESM

FG P

ART

#M

FGVA

LUE

CO

MM

ENTS



MAX1153/MAX11254 Family EV Kit PCB Layout Diagrams

MAX1153/MAX11254 Family EV Kit—Top Silkscreen

MAX1153/MAX11254 Family EV Kit—Top Paste

MAX1153/MAX11254 Family EV Kit—Bottom Silkscreen

MAX1153/MAX11254 Family EV Kit—Bottom Paste



MAX1153/MAX11254 Family EV Kit PCB Layout Diagrams (continued)

MAX1153/MAX11254 Family EV Kit—Internal 2


MAX1153/MAX11254 Family EV Kit —Internal 3




MAX1153/MAX11254 Family EV Kit PCB Layout Diagrams (continued)

MAX1153/MAX11254 Family EV Kit—Top

MAX1153/MAX11254 Family EV Kit—Top Mask

MAX1153/MAX11254 Family EV Kit —Bottom

MAX1153/MAX11254 Family EV Kit—Bottom Mask



MAX1153/MAX11254 Family EV Kit Schematic

ALL INPUTS +/- 3V MAX

1282834-0

49.9

282834-4

282834-4

1282834-0

1282834-0

1K

1K

49.9

J25

J26

R17

R18

R19

R16

J3

J2

J1

GPO0GPO1

AIN5D-AIN5-AIN5+

AIN4D+

AIN4D-AIN4-AIN4+

AIN3.3-AIN3.3+AIN3.2+AIN3.1-AIN3.1+AIN3D+

AIN2.4-AIN2D-

AIN3.2-

AIN3.4+AIN3D-AIN3.4-

AIN2.4+AIN2.3-AIN2.3+AIN2.2-AIN2.2+AIN2.1-AIN2.1+AIN2D+

REFN_SAIN1D-AIN1D+AIN0D-AIN0D+REFP_SREFP

AVSS

AIN5D+

10

10987654321

10987654321

4321

4321

987654321

OUT

OUT

OUTOUT

OUTOUT

OUT

OUT

OUTOUT

OUT

OUTOUT

OUTOUTOUTOUTOUT

OUT

OUTOUT

OUTOUT

OUTOUTOUTOUTOUT

IN

OUT

OUT

OUT

OUTOUTOUT

OUT

OUT

OUT



MAX1153/MAX11254 Family EV Kit Schematic (continued)

AIN2

.4-

AIN2

.3+

AIN2

.3-

AIN2

.2+

AGND

AIN2

.2-

AIN2

.1+

AIN2

.1-

AIN2

.4+

0

AGND

0.1U

F

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

0.1%

10PPM

10

1M

1M 1M

AGND

0

0.01UF

AGND

AGND

1K

1K1K

.1%

1K.1

%

1K

.1%

.1%

AGND

1K

0.01UF

AGND

1K

0

.1%1K

1K

1K.1

%

10

0.1%

10PPM

1K.1

%

AGND

.1%

.1%

0.1%1.5K

.1%

0.1%1.5K

.1%

AGND

1K

AGND

1M

.1%

1K

AGND

1M

.1%

0.01UF

1UF

0.1U

F1U

F0.

1UF

AGND

AGND

0.01UF AGND

AGND

1M AGND

1M

.1%

AGND

1M

AGND

AGND

0.01UF

0

MAX9

632A

UA+

01K

0.1U

F0.

1UF

AGND

1K

MAX9

632A

UA+

AGND

0.1U

F1U

F0.

1UF

1UF AGND

.1%

0

0.01UF

1KMA

X963

2AUA

+

0.01UF AGND

1UF

1UF

0.01UF

1UF

1UF

0.1U

F

AGND

AGND

MAX9

632A

UA+

AGND

.1%

J37

J27 J30

J29

TP45

R25

C49

R47

R43

R30

R33

R35

C37

R32

R50

R40

R53

R52

R48

R41

R46

R44

R45

J28

TP38

TP36 TP

39

TP40

J31

R29

R26

R20

R34

C36

C38

C40

C42

C44

J35

TP48

R36

R38

C34

R21

TP37

R22

TP41

R23

R37

R31

J32

TP42

TP35

TP43

TP44

R27

R24

J34

C35

U12

R39

R42

TP50

J36

TP51

C39

C41

C45

C43

J38

U14

C53

C55

C57

C51

R49

R51

C47

J33

TP46

U11

U13

C46

C48

C50

C52

C54

C56

TP49

R28

VEE

AIN2

BN

AIN2

BP

VCC

AIN2

.2-

AIN2

.2+

AIN2

.1+

VEE VEE

AIN2

.3+

AIN2

.4+

AIN2

.4-

AIN2

.1-

AIN2

.3-

VCC

VCC

VCC

VEE

VEE

VCC

VCC VC

C

VREF

VEE

VCC

VREF

VEE

VEE

8

2

6

5

323 5

7

1

2

5432

1

5432

1

43

2

32

1

4

5

2 38

764

7

5432

5432

31

8

2

87

641

75

1

1

1

1

4

63

4

4

66

8

2

1

2

1 3

2

42

5

4

4

1

7

531

1

8

3

1

2

OU

T

JUM

PE

R

54

32

1

54

32

1

43

21

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

43

21

87

651 3

42

IN

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

ININ

IN

ININ

IN

ININ

IN

ININ

ININ

IN

ININ

ININININ

IN

INININ 54

32

1

54

32

1

43

21

43

21

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

87

651 3

42

INJU

MP

ER

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

OU

T




AIN3

.2+

AIN3

.1-

AIN3

.1+

AIN3

.2-

AIN3

.3-

AIN3

.3+

AGND

AIN3

.4+

AIN3

.4-

AGND

0

1UF

AGND

0.1U

F

0.1U

F

0.1U

F

AGND

AGND

AGND

AGND

AGND

AGND

AGND

AGND

1UF

10

0

1UF

1M

1M

1UF

1UF

1M

1UF

1M

AGND

0.1%

10PP

M

10

1UF

0

AGND

AGND

0

0.01

UF

0.01

UF0.

01UF

0

AGND

0.01

UF

AGND

1K.1

%

AGND

MAX9

632A

UA+

.1%

1K

.1%

AGND

0.01

UF1K

0.01

UF

.1%

AGND

MAX9

632A

UA+

1K

.1%

AGND

0.1U

F

0.1%

10PP

M

1K

.1%

1K

MAX9

632A

UA+

AGND

.1%

1K

0

1K.1

%

AGND

.1%

1K1K.1

%

AGND

AGND

1K

1K0.

1%1.5K

0.1%1.5K

.1%

0.1U

F

0.01

UF

.1%

MAX9

632A

UA+

0.1U

F

AGND

1M

AGND

AGND

1M

.1%1K

.1%

1K

1M

1M

AGND

AGND

.1%

AGND

0.1U

F1U

F0.

1UF

.1%

1K

1K

AGND

0.01

UF

AGND

J40

C66

C65

R59

C80

C78

C76

C74

C69

C81

C79

C77

C75

R54

J39

J41

R56

J42

R58

R72

R93

C62

U15

R92

C67

R71

J44

R57

C61

C73

R94

C60

J43

TP64

R70

R68

R63

R66

C58

C70

R89

R91

U17

C72

C63

C68

TP65

C59

U18

R90

R83

R80

R69

R65

R64

R84

R87

J45

J46

R86

R88

R85

TP59

C64

C71

TP56

TP57

R55

TP58

R82

R81

TP54

TP66

TP67

TP60

R61

TP61

TP53

TP62

TP52

TP68

TP69

TP63

R60

R62

R67

U16

AIN3

BP

VCC

VEE

VCC

VCC

AIN3

.2-

AIN3

.1+

AIN3

.1-

VCC

AIN3

.2+

AIN3

.4-

AIN3

.4+

AIN3

.3-

AIN3

BN

VCC

AGND

VCC

AGND

VEE

VEE

VEE

VEE

VCC

VCC

VEE

VEE

AIN3

.3+

VEE

VREF

VREF

6

7

1

7

87

6431

5

2

76

542

1

7

85

1

2

43

21

4

43

2

6

5

85

2

4 4

3

1

6

18

4

32

7

26

4

3

1

2

85

4

2

3

22

3

31

1

8

1 3

1

JUM

PE

R

IN

87

651 3

42

IN

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

IN

43

21

IN

87

651 3

42

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

IN

43

21

ININ

43

21

43

21

ININ

IN

IN

IN

IN

ININ

IN

IN

IN

ININ

IN

IN

IN

IN

OU

T

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-

OU

T

JUM

PE

R

IN

IN

N.C.

N.C.

SHDN

VCC

VEE

OUT

IN+

IN-




AIN5+

AIN5-

AIN4+

AIN4-

0.1%0.1%

0.1U

F

1K

1K

4700

PF

4700

PF

1K

4700

PF

1K

AGND

AGND

AGND

4700

PF

0.1U

F47

00PF

AGND

0.1U

F

0.1U

F

AGND

4700

PF

AGND

AGND

AGND

AGND

10K

1UF

0.1U

F

AGND

10K

1K

0.1U

F

4700

PF

1K

AGND

MAX4

4205

4700

PF

1UF

AGND

1UF

1UF

0.1U

F

AGND

MAX4

4205

1K

AGND

1K

R101 R1

03

R98

R102

C84

R104

C91

C90

C99

C98

C97

C93

C85

C86

C92

C89

C83

C82

R95

R96

C100

R100

R97

J47

J48

TP70

TP73

TP72

C94

C95

U19

C96

U20

R99

TP71 TP

75TP74

J50

J49

C87

C88

AIN4BP

VOCM

VCLPL

VOCM

+5V

VCLPL

REFN

-5V

+5V

VOCM

REFP

AIN4+

AIN5+

AIN4-

VCLPH

AIN4BN

-5V

AIN5-

-5V

+5V

+5V

-5V

AIN5BN

AIN5BP

VCLPH

10

6119

3

1

2345

1

2345

9

5

4

7

1

2

12

3

13

5

124

7

1

8

12 4

6

10

3

118 2

12

133

4

ININ

43

21

OUT

-

VCLP

L

SHDN NC

EPIN-

IN+

OUT

+

VS+

VOCM

VS-VC

LPH G

NDIN

INOU

T

OU

T

IN

54

32

1

ININ

ININ

ININ

ININ

ININ

OU

T

ININ

43

21

OUT

-

VCLP

L

SHDN NC

EPIN-

IN+

OUT

+

VS+

VOCM

VS-VC

LPH G

NDIN

INOU

T

OU

T

IN

54

32

1




GPO0

GPO1

3V_VREF

GPIO0_CLK

GPIO1_SYNC

3V_VREF

1.8V_VREF

GPOGND

MAX6

070A

AUT1

8+

MAX6

070A

AUT3

0+

4.7UF

AGND

AGND

MAX1

1254

ETJ+

AGND

3300PF

3300PF

AGND

3300PF

0.1%49

.9

49.9

3300PF

0.1U

F1U

F0.

1UF

1UF

AGND

1UF

AGND

AGND

4.7UF

0.1U

F

AGND

1.0UF

0.1U

F

AGND

AGND

3300PF

3300PF

AGND

49.9

LTC6

930H

DCB-

8.19

0.1U

F10

0.1%

0.1U

F

AGND

AGND

MAX6

126A

ASA3

0

1000PF

0.1U

F

AGND

0.1U

F

10K AGND

10PP

M

0.1%

AGND

10PP

M

10PP

M

10PP

M

10PP

M

0.1%10 10

0.1% 10

10PP

M

10

0.1%10 10

10PP

M

4.7UF

1UF

4.7UF

0.1%

10PP

M

10

1UF

AGND

AGND

AGNDAGND

AGND

0.1U

F0.

1UF

0.1U

F0.1U

F

10PP

M0.

1%

10PP

M

0.1% 10

10PP

M

0.01UF

0.1U

F1U

F

0.1UF

AGND

AGND

AGND

0.1%

0.1%

10PP

M

0.1%49.9

AGND

TP33

J24

U7U8U9

C18

TP18

TP12

TP11

TP16

TP17

TP10

TP9

TP8

TP7

C13

TP6

TP5

TP15

C12

TP3

C11

TP4

TP13

TP2

TP1 C1

0

J16

J13

J17

C26

J10

J12

TP28 C3

0

TP21

TP19

C19

C20

C31

C27

TP22

C32

C33

C28

C5

JMP1

C15

C14

U1

C23

J11

U10

R202

C29

J15

J14

R11

C21

TP23

R15

TP30

R5 R13

R4R1

C22

C1C7

C4C1

7

C8C2

C25

C16

C9C6

C3

TP27

TP24

TP26

TP25

C24

J7

R14

R12

R10

R9R8

J6J5J4

R2 R3

TP29

TP20

VREF

AIN3N

AIN4P

AIN4N

AIN2P

AIN0N

+1.8V

AIN1N

AIN0P

AIN0N

AVDD

AVSS

+3.3V

AVDD

REFP

REFP RSTB

AIN1P

AIN2N

REFP_F

AIN3P

AIN5N

AIN5P

AIN2N

AIN1P

SCLK

AVSS

DOUT

CSB

DIN

AGND

AIN3N

AIN4P

DVDD

REFP_S

+1.8V

REFN_S

-1.8V

+2V/+3.3V

DVDD

AIN5P

EXT_CLK

AIN2P

AIN3P

AIN4N

AIN1N

AIN0P

AVDD

VREF

AIN3D-

AIN1D-

AIN1D+

AIN0D-

AIN0D+

AIN3BP

AIN3BN

AIN3D+

AIN4D-

AIN4D+

AIN4BN

AIN4BP

AIN2D-

AIN2BP

AIN2BN

AIN2D+

AIN5BN

+3.3V

AIN5D+

AIN5BP

AGND

GPO1

RSTB

AVSS

REFN

REFP_F

AIN5N

AIN5D-

DVDD

AVSS

AVSS

RDYB

GPO0

SYNC

2

2

3

1

13

17

18

19

20

2

6

47

3

2

5125

15

2

26

21

6

11

3

8

12

7

2

1614

24

4

3

42

8

1

9

3

5 64

2

1 3

5 64 1 3

3

6

5

43

3

2

3

2

1

1

87

65

43

21

87

65

43

21

87

65

43

21

87

65

43

21

5

1

22

23

33

32 2931

3

12109

8

7

11

2

1

30 28 27

OU

T

ININ

OU

TO

UT

OU

T

ININ

IN IN IN IN IN IN IN IN IN

ININ

IN

OU

T

ININ

OU

T

OU

T

OU

T

OU

TO

UT

IN

V+

OUT

GND

DIVC

DIVB

DIVA G

ND

V+

EP

IN

OUT

FO

UTS

IN ENG

ND

FILT

ER

OUT

FO

UTS

IN ENG

ND

FILT

ER

ININ

IN

IN

OU

TININ

OU

T

IN

I.C.I.C.

OUT

F

OUT

S

GNDSGND

NR

INININ

IN

IN IN IN IN

IN

IN IN

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

OU

T

IN8

76

51 342

IN ININININ IN IN ININ

87

651 3

42

IN IN ININ

87

651 3

42

IN IN ININ

87

651 3

42

ININ

DGNDDI

N

CSB

DOUT

DVDD

RSTB

CAPR

EG

GPI

O1/

SYNC

GPO0

GPIO0_CLK

GPO1

GPOGND

CAPP

CAPN

AIN5P

AIN5N

AIN4

P

AIN4

N

AIN3

P

AIN3

N

AIN2

P

AIN2

N

AIN1

P

AIN1

N

AIN0P

AIN0N

REFN

REFP

AVSS

AVDD

SCLK

RDYB

EP



MAX1153/MAX11254 Family EV Kit Schematic (continued)4.7UF

1UF

1UF

0.1UF

0.1UF

AGND

1UF AG

ND

AGND

28 28 28 28

0.1UF

AGND

1UF

MAX14935CAWE+

AGND

0.1UF

28

AGND

MAX14935CAWE+

2828

AGND

AGND

0.1UF

28

U5

C115

C119

C121

C120

C117C1

16C1

13

R113

R105

C114

R112

R111

R116

R117

C122

U6

J52

TP77

TP76

R115

J51

C118

R114

DIN

DOUT

RDYB

VDD

VDD

VDDI

O

CSB_

FPGA

DIN_

FPGA

SCLK

_FPG

A

DOUT

_FPG

A

VDDI

O

SCLK

RSTB

_FPG

A

SYNC

RSTB

EXT_

CLK

SYNC

_FPG

A

RDYB

_FPG

AEX

T_CL

K_FP

GA

VDD

GND_

FPGA

VDDI

O

GND_

FPGA

VDD

VDD

+3.3

V

GND_

FPGA VDDI

O

GND_

FPGA

CSB

EXT_

CLK

SYNC

DOUT

CSB

RDYB

RSTB

SCLK

DIN

DVDD

1113 12

1

16

1

8

9

15

3 4 5

111310 127

2

314

6

14

16

1

2

10

3

6 754

8

9

1098764321 5

2

15

IN

VDDB

VDDA

OUT

B3O

UTB2

OUT

B1

ENA

OUT

A1IN

B1

INA3

INA2

INA1

GND

BGND

BG

NDAG

NDA

ENB

IN

IN IN

OU

TO

UT

OU

TO

UT

ININ

IN

OU

T

IN

OU

T

OU

TIN

ININ

ININ

VDDB

VDDA

OUT

B3O

UTB2

OUT

B1

ENA

OUT

A1IN

B1

INA3

INA2

INA1

GND

BGND

BG

NDAG

NDA

ENB

IN

OU

T

ININININ

IN

IN

OU

T

IN

IN IN

IN

IN

IN




GND

SYNC_CLK_IN_SPLIT

SYNC_CLK_OUT

SYNC_CLK_OUT

SYNC_CLK_OUT

SYNC_CLK_IN

SYNC_CLK_IN

28

28

28

1000PF

28

74LVC2G125DP

0.1UF

0

0.1UF

28

93LC66BT-I/OT

28

PBC06SAAN

28

28

28

49.9

49.9

28

49.9

49.9

28

74LVC2G125DP

28

28

1UF

0.1UF

1UF

28

28

28

28

28

28

ASP-134604-01

28

28

28

28

ASP-134604-01

0

1000PF

ASP-134604-01

ASP-134604-01

U22

R167J58

R148

R157

R146

R145

R144

R142

R158

R156

R153

R151

TP78

R163

J54

R166

C127

R164

J55

C128

U23

J57

TP80

J56

TP79

C125

R150

R152

R147

C129

U21

R160

R159

R155

R154

C124

C123

J53

R139

R141

R140

R161

R143

J53

R149

C126

R162

R165

J53

J53

SYNC_CLK_INSYNC_CLK_OUT

5V_TTL

GND_FPGA

GND_FPGA

GND_FPGA

SYNC_FPGA

GND_FPGA

GND_FPGA

GND_FPGA

RSTB_FPGA

SO_EEPROM_FPGA

GND_FPGA

GND_FPGA

GND_FPGA

VDDIO

SO_EEPROM_FPGA

CSB_FPGA

DIN_FPGA

DOUT_FPGAEXT_CLK_FPGA

VADJ

SYNC_CLK_OUT

GND_FPGAGND_FPGA

3V3_FPGA

GND_FPGA

GND_FPGA

SCLK_FPGA

RDYB_FPGA

3V3_FPGA

VDDIO

GND_FPGA

SYNC_CLK_IN

VADJ

GND_FPGA

+12V_FPGA

1

7

2 6

5 3

48

1

2 3 4 51

234

7

2 6

5 3

48

123456

45

31

62

1

2 3 4 5

1

2 3 4 5

C36C35C34C33

C30C29C28C27C26C25C24C23C22C21C20C19C18

C14C13C12C11C10

C8

C6

C4C5

H39H38H37H36

H33H32H31H30H29

H26

H24H23H22

H20H19

H10H9H8H7H6

H4H3H2H1

G22

C9

H35

D31

D24

D14

D9

D5D4

D1

H27

H25

D6

D8D7

D10D11

D13

D15

D17D16

D18

D12

D19

D23D22

H21

H12H13H14H15H16H17

D25D26D27D28D29D30

D35D36

D38

D32

D39D40

C7

G1G2G3

G7G6

G8G9G10G11G12G13

G15G16G17

G19G20G21

G24G23

G26G27

G30

G33G32

G37G36

G38

G40G39

G31

H40

D34D33

G35G34

C3C2

G5G4

C1

G14

H5

D2D3

H11

H18

D21D20

H34

C15C16C17

G25

1

C39C40

C38C37

H28

G29G28

5

G18

D37

C31C32

IN

40393837363534333231302928272625242322212019181716151413121110987654321

40393837363534333231302928272625242322212019181716151413121110987654321

OUT

5 4 3 2

1

5 4 3 2

1

OUT

VCC

VSS

DODICLKCS

5 4 3 2

1

IN

2A2OE

2Y

VCC

1Y

GND

1A1OE

5 4 3 2

1

IN

INOUT

2A2OE

2Y

VCC

1Y

GND

1A1OE

OUTIN

OUT

OUTOUT

INOUT

OUT

40393837363534333231302928272625242322212019181716151413121110987654321

40393837363534333231302928272625242322212019181716151413121110987654321



MAX1153/MAX11254 Family EV Kit Schematic (continued)PMOD HEADER

ONE CAPACITOR PER EACH POWER PIN

10118192-0001LF

MICR

O-US

B

28

600

10K

0.1U

F

10K

4.7K

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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2018 Maxim Integrated Products, Inc. │ 36


Revision HistoryREVISIONNUMBER

REVISIONDATE DESCRIPTION PAGES

CHANGED0 4/15 Initial release —1 5/15 Added the MAX11253 EV kit to data sheet 1–222 4/18 Updated PCB layout diagrams, schematic, and bill of materials 21-35

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

max11253/max11254 ev kit-evaluates: max11253/max11254 · the ev kit board (table 2). 2) connect the...

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