master/slave flip flops - new mexico's flagship university...
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MSFFPage 1
ECE 238L © 2006
MSFF
Master/Slave Flip Flops
MSFFPage 2
ECE 238L © 2006
A Master/Slave Flip Flop (D Type)
Gated D latch(master) Gated D latch (slave)
D Q
Gate
D Q
Gate
D
GATE
QQ1
Either:The master is loading (the master in on)
orThe slave is loading (the slave is on)
But never both at the same time…
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ECE 238L © 2006
DFF Timing
Gate
Q1
MasterLoads
SlaveLoads
D
Q
MasterLoads
MasterLoads
SlaveLoads
SlaveLoads
time
D Q
Gate
D Q
Gate
D
GATE
QQ1
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ECE 238L © 2006
Output Changes in Response to Falling Clock
CLK
Q1
MasterLoads
MasterLoads
MasterLoads
SlaveLoads
SlaveLoads
SlaveLoads
D
Q
time
D Q
Gate
D Q
Gate
D
GATE
QQ1
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ECE 238L © 2006
DFF Detailed SchematicD
CLK
Q
Q’
Master latch (D)
Slave latch (SR)Usually call the gate “CLK”
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ECE 238L © 2006
A Falling Edge Triggered DFFD
CLK
Q
Q’
D
CLK
QD Q
Edge-triggered
Falling edge triggered
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ECE 238L © 2006
Oscillator (Toggle Circuit) Operation
Q
CLK
CLK
time
QD D Q
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ECE 238L © 2006
Rising Edge Triggered DFF Schematic
D
CLK
Q
Q’
D QD
CLKEdge-triggered
Q
Rising edge triggered
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ECE 238L © 2006
Oscillator (Toggle Circuit) Operation
Q
CLK
time
CLK
QD D Q
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ECE 238L © 2006
D Flip Flop Transition Table
D Q Q+
0 0 00 1 01 0 11 1 1
Q+ = D
No clock shown since it is edge triggered (assumed)
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ECE 238L © 2006
Falling vs. Rising Edge Triggered
D Q D QD
CLK CLK
Qfall Qrise
CLK
D
Qrise
Qfall
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ECE 238L © 2006
Alternative Flip Flops
TJK
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ECE 238L © 2006
Toggle Flip Flop
T Q Q+
0 0 00 1 11 0 11 1 0
NoAction
Toggle
T Q
CLK
QT
Q+ = T’•Q + T•Q’ = T + Q
Clock edge is assumedin this transition table…
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ECE 238L © 2006
Toggle Flip Flop
T Q Q+
0 0 00 1 11 0 11 1 0
NoAction
Toggle
T Q
CLK
QT
Q+ = T’•Q + T•Q’ = T + Q
D QT
Q
CLK
An oscillator with an enableinput (T)
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ECE 238L © 2006
Toggle Flip Flop
QT
CLK
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ECE 238L © 2006
JK Flip Flop
J K Q Q+
0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 11 1 1 0
No Change
Reset
Set
Toggle
J QK
CLK
QJK
Q+ = K’•Q + J•Q’Kind of a cross betweena SR FF and a T FF
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ECE 238L © 2006
JK Flip Flop
Q
J
CLK
K
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ECE 238L © 2006
Why Alternative FF’s?
• With discrete parts (TTL family)– JK or T FF’s could reduce gate count for
the input forming logic – Extensively used
• With VLSI IC’s and FPGA’s– JK or T FF’s must be built from
DFF+gates– Larger, slower than a DFF– Not used
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ECE 238L © 2006
Flip Flops With Additional Control Inputs
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ECE 238L © 2006
D
CLK
Q
Q’
What is this?
???
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ECE 238L © 2006
D
CLK
Q
Q’
What is this?
Enable
A falling edge triggered, D-type FF with enable
Master only loads when CLK=Enable=‘1’
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ECE 238L © 2006
D
CLK
Q
Q’
What is this?
???
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ECE 238L © 2006
D
CLK
Q
Q’
What is this?
Set
A falling edge triggered, D-type FF with an asynchronous set
If Set=1 then Q=>1, regardless of CLK or D
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ECE 238L © 2006
D
CLK
Q
Q’
What is this?
???
MSFFPage 25
ECE 238L © 2006
D
CLK
Q
Q’
What is this?
A falling edge triggered, D-type FF with a synchronous set
If Set=1 then Q=>1 on the next falling edge of the clock, regardless of D
Set
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ECE 238L © 2006
Flip Flops With Additional Control Inputs
• A variety of FF’s have been made over the years
• They contain combinations of these inputs:– Enable– Set– Reset
• The Set and Reset can be either:– Asynchronous (independent of CLK)– Synchronous (work only on CLK edge)
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ECE 238L © 2006
Flip Flop Timing Characteristics
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ECE 238L © 2006
Clock-to-Q Time (tCLK Q)
D
CLK
Q
Q’
tCLK Q = tNOT + tAND + 2 x tNOR
The output does not change instantaneously…
Why 2 x tNOR?
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ECE 238L © 2006
tCLK Q
CLK
D
Q
tCLK Qtime
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ECE 238L © 2006
Setup Time (tsetup)D
CLK
Q
Q’
tsetup = tNOT + tAND + 2 x tNOR
The input has to get there early enoughto set the master latch before
the clock turns off…
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ECE 238L © 2006
tsetup
CLK
D
Q
tsetup
time
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ECE 238L © 2006
D
CLK
Q
Q’
Same setup time as before
Clock is delayed through the NOT gate
Rising Edge FF Setup Time (tSETUP)
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ECE 238L © 2006
CLK
D
Q
tsetup-old
time
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ECE 238L © 2006
CLK
D
Q
time
CLKdly
tnot tsetup-old
tsetup-old
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ECE 238L © 2006
CLK
D
Q
time
CLKdly
tnot
Dnew
tsetup-old
tsetup-old
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ECE 238L © 2006
CLK
D
Q
time
CLKdly
Dnew
tsetup
tsetup-old
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ECE 238L © 2006
Falling Edge Hold Time (thold)
D
CLK
Q
Q’
thold = 0ns (AND gates turn off immediately)
You have to keep the old D value there until the ANDgates are shut off… (but no longer)
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ECE 238L © 2006
Rising Edge Hold Time (thold)D
CLK
Q
Q’
thold = tNOT
You have to keep the old D value there until the ANDgates are shut off…
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ECE 238L © 2006
thold
CLK
D
Q
thold = tNOT
time
Clock edge AND gate turns off, D can now change
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ECE 238L © 2006
Flip Flop Timing
CLK
D
Q
tsetup
thold
tCLK Qtime
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ECE 238L © 2006
Timing of a Synchronous System
CLK
D Q
CLK
D QInputFormingLogic
InputFormingLogic
time
Q D
CLK
Q
D
tCLK Q tIFL tSETUP
tCYCLE >= tCLK Q + tIFL + tSETUP
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ECE 238L © 2006
D QD QD Q
Example of a Synchronous System
D Q+1
Circuit
4
CLK
4 4CNT = 0000
0001001000110100…11110000…One transition per clock edge…