master of science in mechatronics engineering 2019/2020
TRANSCRIPT
Master of Science in Mechatronics Engineering
2019/2020
Electronics for Internet of Things
Short summary on Digital Electronics
Same system as decimal coding: position dependent value of symbolsBase 10 (decimal), base 2 (binary, prefix 0b), base 16 (hexadecimal, prefix 0x or suffix h)To convert in mind a number from decimal to binary operate by successive approximations.
Binary and Hexadecimal Coding
4‐bit
Binary0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Dec 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
Dec 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15
Bin 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Hex 0 1 2 3 4 5 6 7 8 9 A B C D E F
Fixed Point Binary Number representation
1 bit M bit N bit
INTEGER part FRACTIONAL part
INTEGER partI
FRACTIONAL partP
SIGN(signed integer only)
ASCII code (American Standard Code for Interchange of Information) encoding with a string of 8 bits (1 byte) 28 = 256 different characters, including digits, upper and lower case letters, graphic characters and special (accented) characters. Eg from the table the 'T' character can be expressed in the software in format:
characterbinary (01010100=26+24+22=64+16+4=84)decimal (84)hexadecimal (54=5x 161+4x160=80+4) (1st row + 1st col).
Hardware only uses bynary encoding.
Unicode encoding (2 byte) can represents 216 =65536 different characters, also ethnic. (adopted by Windows).
Encoding Alphanumeric Characters
Logic Symbols Logic Levels
logic “1”
logic “0”
unspecifiedVLmax
VHmin
VHmax
Positive Logic
logic “0”
logic “1”
unspecifiedVLmax
VHmin
VHmax
Negative Logic
0
0.8
2.2
5
TTL standardVcc = 5V
VLmax
VHmin
VHmax
V
VLmin 0
0.8
2.2
3.3
CMOS standardVcc = 3.3V
VLmax
VHmin
VHmax
V
VLminVLmin VLmin
LOGIC OPERATORS
on boolean variables (True/False or High/Low) or binary (0/1)
input outputlines line
LOGIC GATES
There are two ways to realize a logic function, which performs the desired output for each input configuration:OR of AND – add the terms in which the function is 1 (minterms). AND of OR – multiply the factors in which the function is 0 (maxterms)Simply program the switches on the connections (black dots) using Programmable Logic Arrays (PLA, see later).
DESIGN OF LOGIC CIRCUIT
OR di AND
Decoder – rises (0 1) the output lines which corresponds to a particular input code (eg to access (R/W) to a memory cell with its address code).Hardware: ecc.
Multiplexer (analogue or digital) – selects the input line corresponding to the input code and connects it to the output line. Eg sequential reading of N input sensors, or parallel‐to‐serial conversion (internal data bus external serial bus).Hardware:
Demultiplexer – connects the input line to the output line corresponding to the input code. Eg serial‐to‐parallel conversion (external serial bus internal parallel bus)Hardware:
N‐bitcode(xi)
2NOUTPUTlines(yi)
DECOD
N‐bit code (si)
OUTPUTline(y)
MUX
2NINPUTlines(xi)
N‐bit code (si)
INPUTlinex
DEMUX
2NOUTPUTlines(yi)
LOGIC DEVICES
Full adder – makes the sum of two binary numbers: (xi+yi+ci=zi+ci+1)
x0 y0
FullAdder
cinc1
z0
xi yi
FullAdder
ci …ci+1
zi
xn yn
FullAdder
cn …cout
zn
Counter – starting from 0, if enabled, increases the output binary value (N bit) at each clock rise (counts clock pulses). When it reaches the maximum value (overflow, all bits are 1) equal to 2N‐1 for N bit, resets to 0 and starts again.Usually, count can go Up or Down (U/D)
xi yi ci zi ci+10 0 0 0 0
0 1 0 1 0
1 1 0 0 1
1 1 1 1 1
LOGIC DEVICES
U/D
Reset
Counter OUTCLK
Enable
N
Latch – bistable which stores 1 bit (asinchronous)
Flip‐flop – storing synchronized with clock
Register – series of FF to store a binary number of (8,16,24,32,64) bit. it is not possible to read or write the single bit, but the whole string(parallel access).
Shift Register – as the Register, but allows both paraller and serial access (even circular)
Reset
Flip‐Flop OUTSET
Enable
RESET
CLK
CLK Enabled7 d6 d5 d4 d3 d2 d1 d0
Parallel INPUT DATA BUS
Parallel OUTPUT DATA BUS
d7 d6 d5 d4 d3 d2 d1 d0
Parallel INPUT DATA BUS
Parallel OUTPUT DATA BUS
Serial INPUT line
Serial OUTPUTline
Latch OUTINPUT
Reset
Flip‐Flop OUTIN
Enable CLK
SOLID STATE MEMORIES (or Electronic/Semiconductor memories)
MEMORIES store bytes in memory cells each having an address code. They can be:
volatile (lose data when power off) permanent
rewritable (R/W) read only
random access (same access time for all cells) sequential access (LIFO, FIFO, CAM, STACK)
SOLID STATE MEMORIESLatency Volatile Permanent
Read/Write R/W Programmable Read only
NameFIFO, LIFO, CAM, STACK SRAM
DRAMEEPROM
Flash, FRAM, SSDmask ROMPROMShift Register
Access sequential random
SOLID STATE MEMORIES (or Electronic/Semiconductor memories)
PLA (Programmable Logic Array) allows to create logic circuits configuring, through programmable switches (MOSFET), the connections between the ports already implemented in the hardware, the inputs and the outputs.
FPGA (Field Programmable Logic Array) – as PLA but with memory (eg digital filters, digital modulation)
PROGRAMMABLE LOGIC DEVICES
Microcontroller – programmable devices used to read analogue or digital inputs (eg sensors), convert them to digital with ADC if analogue, control actuators (eg electric motors, light sources), timing actions, share information on serial lines. As soon as fed, execute the only one program (firmware) saved in memory, written by the user and modifiable.
DSP (Digital Signal Processor) ‐ Similar to microcontrollers, but with an architecture optimized for complex digital processing (eg digital processing of sounds, images, etc. even in real time).
Microprocessor ‐ Contain a management program (operating system, OS), on which programs can be implemented for particular functions (applications).
PROGRAMMABLE PROCESSORS