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BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Archive – Market Session
March 5 - 8, 2017
Hilton Phoenix / Mesa Hotel
Mesa, Arizona
© 2017 BiTS Workshop – Image: tonda / iStock
BiTS 2017
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Copyright Notice
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BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
BiTS Workshop 2017 Schedule
Tutorial Day Sunday March 5 - 8:30 pm
Marketplace Report
Ira Feldman
Feldman Engineering Corp.
Market
Session
Market Connections – Semiconductors to Sockets
John West
Managing Director
VLSI Research Europe
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Marketplace Report
Ira Feldman
Feldman Engineering Corp.
BiTS Workshop
March 5 - 8, 2017
Conference Ready
mm/dd/2014
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Outline
• Fundamentals
– How did we get here?
• Test Today
• Integrated “Ecosystems”
• Socket Market Data
Marketplace Report 5
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
6
… the number of
transistors on a
chip will double
approximately
every year two
years …
Gord
on M
oore
1962
cre
dit:
Fairchild
Cam
era
& I
nstr
um
ent
Corp
ora
tion.
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
7
Minimum cost
per transistor is
achieved by
doubling the
number of
transistors every
two years.
Gordon Moore
1965*
Gord
on M
oore
1962
cre
dit:
Fairchild
Cam
era
& I
nstr
um
ent
Corp
ora
tion.
* Revised in 1972 from
every 12 to 24 months.
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
8
Cramming more components
onto integrated circuits
Electronics, Volume 38, Number 8, April 19, 1965
The experts look ahead
With unit cost falling as the number of components per
circuit rises, by 1975 economics may dictate squeezing as
many as 65,000 components on a single silicon chip
By Gordon E. Moore Director, Research and Development Laboratories, Fairchild Semiconductor division of
Fairchild Camera and Instrument Corp.
The complexity for minimum component costs has increased at a rate of roughly a factor of two
per year (see graph on next page). Certainly over the short term this rate can be expected to
continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain,
although there is no reason to believe it will not remain nearly constant for at least 10 years.
That means by 1975, the number of components per integrated circuit for minimum cost will be
65,000.
Marketplace Report
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Moore’s Law is “Dead”
Marketplace Report 9
Handel Jones, 2012
http://www.eetimes.com/author.asp?section_id=36&doc_id=1287737
90 65 40 28 20 14 10 7 5 nm
?
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Marketplace Report 10
“Populist view: Any parameter related to
semiconductors must form a straight line when
plotted on exponential graph paper.”
– Prof. Subramanian Iyer (UCLA, former IBM Fellow)
Khoso & Khan – Northeastern University 4/2016
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
11
“Knobs” to reduce
product cost
Transistor Scaling
Materials
Device Structure
Substrate Size
cost / area
More than Moore
Architecture
Packaging
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
More than Moore (MtM)
Marketplace Report 12
ITRS “More than Moore” Whitepaper
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
MtM System in Package (SiP)
Marketplace Report 13
Xilinx Virtex-7 FPGA (Oct ’11)
2.5D/3D/5.5D Packaging – First to Market
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
High Performance SiP
Marketplace Report 14
Kitada, et. al / Fujitsu – February 2017
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Silicon Photonics
Marketplace Report 15
ST 100G PSM4 QSFP 28 (STsP10028) October 2016
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Microfluidics
Marketplace Report 16
SEMI European 3D Summit – January 2017
Frechette - Universite de Sherbrooke Zapater - Ecole Polytechnique Federale
de Lausanne (EPFL)
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
MtM System in Package (SiP)
Marketplace Report 17
ASE / IFTLE 295 - Phil Garrou – July 2016
Fan Out Wafer Level Packaging
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Transition to FO-PLP
Marketplace Report 18
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Historical Test Approach
Marketplace Report 19
Wafer Sort Final Test
Is it good enough to
package?
Does it meet
specification?
Can I sell it for more?
Higher performance bin
Wik
ipe
dia
Wik
ipe
dia
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Paradigm Shift – Value Creation
• Yield Management
– Process Improvement Feedback
– Die “matching”
• Repair
– Switch off defective “cores”
– Swapping in spares (memory, etc.)
• Performance Tuning
– Calibration
• Personalization
– Serialization
– Security & Keys
Marketplace Report 20
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Test Today
Marketplace Report 21
Typical 2.5/3D Heterogeneous Integration Flow
Sh
ip to
Cu
sto
me
r /
Inte
gra
tors
/ O
DM
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Test Today
Marketplace Report 22
Wafer Package /
Substrate
Ship
to C
usto
mer
/ In
tegra
tors
/ O
DM
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Wafer Package/
Substrate
Test “Convergence”
Marketplace Report 23
Test Strategy + Hardware + Software
Integrated Data Flow
Ship
to C
usto
mer
/ In
tegra
tors
/ O
DM
Device Under Test Interface Hardware
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Wafer Level Chip Scale
Packaging (WLCSP)
Simplest Example
Marketplace Report 24
Test Strategy + Hardware + Software
Integrated Data Flow
Ship
to C
usto
mer
/ In
tegra
tors
/ O
DM
Device Under Test Interface Hardware
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Die / Package Activities
Marketplace Report 25
Characterization
Validation
Reliability
Failure Analysis
Ramp
Wafer Package /
Substrate
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Future Environment
Marketplace Report 26
Characterization
Validation
Reliability
Failure Analysis
Ramp
Wafer
Package
/
Substrate
Device Under Test Interface Hardware
Test Strategy + Hardware + Software
Integrated Data Flow
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Adjacent “Test Markets”
Marketplace Report 27
Characterization
Validation
Reliability
Failure Analysis
Ramp
W P/S
Module Level Test
Product Level Test Package Test
(bare/elements)
Printed Circuit Board Test
System Level Test
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Integrated Ecosystem?
Marketplace Report 28
Characteriz
ation Validation
Reliability
Failure Analysis
Ramp
W P/
S
Module Level Test
Product Level Test Package Test
(bare/elements)
Printed Circuit Board Test
System Level Test
Device Under Test Interface Hardware
Test Strategy + Hardware + Software
Integrated Data Flow
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
-
200
400
600
800
1,000
1,200
1,400
2014 2015 2016 2017 2018 2019 2020 2021
Rev
enu
e, M
$
Test Sockets Burn-in Sockets
Test and Burn-In Socket Market
Marketplace Report
VLSI Research
2016 Preliminary
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Socket Supplier Revenue by
Headquarter Region
Marketplace Report
VLSI Research
2016 Preliminary
2015 - $1,013M 2016 - $1,043M
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Top 5 Market Share
Marketplace Report
VLSI Research
2016 Preliminary
40%
45%
50%
55%
60%
65%
70%
2013 2014 2015 2016
Mark
et S
hare
Test Sockets Burn-in Sockets
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Top Test & Burn-in Socket Vendors
Rank 2014 2015 2016
Preliminary
1 Yamaichi
Electronics
Yamaichi
Electronics
Yamaichi
Electronics
2 Enplas Enplas Enplas
3 Sensata
Technologies
Smiths
Connectors
Smiths
Connectors
4 Smiths
Connectors
ISC ISC
5 LEENO
Industrial
Sensata
Technologies
LEENO
Industrial
Marketplace Report
VLSI Research
2016 Preliminary
BiTS 2017 Market Session
March 5-8, 2017 Burn-in & Test Strategies Workshop www.bitsworkshop.org
Acknowledgements
• Test Socket & Burn-in Socket data
courtesy of John West at VLSI Research
Marketplace Report