mapped phase-shifted space vector modulation for multi-level voltage-source inverters

Mapped phase-shifted space vector modulationfor multi-level voltage-source inverters

A.M. Massoud, S.J. Finney, A. Cruden and B.W. Williams

Abstract: A new multi-level space vector modulation (SVM) technique, termed mapped phase-shifted SVM, is proposed. The SVM technique enables the use of two-level SVM with multi-levelinverters without introducing any carrier level modulation or phase shifts. The proposed techniqueis theoretically analysed for three-, five- and seven-level inverters and then generalised for them-level inverter, validated by simulation using Matlab/Simulink, and confirmed practically for afive-level, shunt, active power filter.

1 Introduction

Owing to increased demand for power converters suitablefor high-voltage, high-power applications, multi-level con-verters are attracting the attention of researchers.Multi-level converters achieve high-voltage switching bymeans of a series of cumulative voltage steps, each ofwhich lies within the rating of the individual powerdevices. One of the most important problems in controllinga multi-level voltage-source inverter is to obtain a variableamplitude and frequency sinusoidal output employingsimple control techniques. In voltage-source inverters,non-fundamental current harmonics cause power losses,electromagnetic interference and pulsating torques in ACmotor drives. Harmonic reduction can then be related tothe performance of an inverter with any switching strategy[1]. For multi-level voltage-source inverters, various pulsewidth modulation (PWM) control schemes have been devel-oped and analysed [2–4] so as to control the fundamentalvoltage and eliminate certain output lower order harmonics,via control of each pulse width.

Multi-level converters can employ different controltechniques. One of the most important techniques isspace vector modulation (SVM), which for multi-levelconverters is considered as an extension of SVM for thetwo-level voltage-source inverter. The SVM techniqueinvolves vectorially equating the volt2 second integralbetween a desired reference voltage vector and thenearest three states in space, which are realisable by theconverter. SVM offers improved DC bus utilisation,reduced commutation losses and lower total harmonic dis-tortion (THD). SVM deals with the inverter as an entitywhereas other PWM techniques – such as sinusoidalPWM, third harmonic injection PWM and dead bandPWM – deal with each phase separately. The widespreadavailability of high-performance, low-cost digital signalprocessors (DSPs), has made SVM implementation a prac-tical approach to the control of power inverters. The SVMconcept for the simple voltage-source inverter has been

# The Institution of Engineering and Technology 2007

doi:10.1049/iet-epa:20060273

Paper first received 9th July and in revised form 20th December 2006

The authors are with the Department of Electronic and Electrical Engineering,Strathclyde University, Glasgow, UK

E-mail: [email protected]

622

discussed in detail [5, 6]. SVM for multi-level convertershas been considered and part of the literature is devoted toSVM for three-level converters [7, 8], whereas [9, 10] con-sider the generalisation of multi-level SVM. A generalisedapproach to multi-level SVM has problems, especially fora high number of levels where the state matrix becomesincreasingly complex. Consequently, SVM applied to multi-level converters has been limited to a low number of levels.The simplification of multi-level space vector PWM hasbeen reported in the literature [11–15].In [11], for multi-level inverters with an odd number of

levels, the common-mode voltage can be eliminated byrestricting the inverter switching to those states that haveno common-mode voltage, at the cost of restricting themodulation depth to one (a 15% loss), harmonic degra-dation and loss of redundant states.In [12], the concept of equivalent null space vectors

applied to link two-level and multi-level modulations ispresented, and it is shown that proper placement of theseequivalent null vectors can give rise to different multi-leveldiscontinuous PWM strategies with both minimal generatedcommon-mode voltage and harmonic distortion. Thesespace vectors can be treated as two-level equivalents byidentifying them as vertices on a two-level space vectorhexagon whose origin is shifted to encompass the head ofthe target reference phasor. Inverter modulation is viewedas two-level SVM with shifted hexagons. The complicationis, as the number of levels increases, the number of shiftedtwo-level hexagons increases (e.g. five-level uses 24hexagons).Similar to [12], in [13], the space vector diagram of a

three-level inverter is simplified to that of a two-level inver-ter. The dwelling time calculation and switching sequenceselection are as for the conventional two-level inverter.Two steps are considered. First, from the location of agiven reference voltage, one hexagon is selected from thesix hexagons. Second, the original reference voltagevector is subtracted by the amount of the centre voltagevector of the selected hexagon.In [14], the common-mode voltage of the NPC inverter

can be zero for certain switching states. Similar to [12],these space vectors can be treated as two-level equivalentsby identifying them as vertices on a two-level spacevector hexagon whose origin is shifted to encompass thevertex of the target reference phasor. Inverter modulationis viewed as two-level SVM with shifted hexagons.

IET Electr. Power Appl., 2007, 1, (4), pp. 622–636

Generally, [11–14] simplify the use of multi-level SVM(five or fewer levels) to two-level SVM, which is equivalentto phase disposing the carriers, not phase shifting them.In [15], each cascaded H-bridge is a standalone bridge

with the necessary signal conditioning/processing circuitry,DC link capacitors and gate drivers. In addition, eachH-bridge has its own DSP controller (and associatedPWM timers) so that the required control and PWM capa-bilities are evenly distributed among the series connectedH-bridges. A serial peripheral interface is used for transfer-ring data between multiple processors. Based on thisconcept, the m-level cascaded inverter is viewed as a net-worked control system having 3(m2 1)/2 slave integratedpower bridges with their own remote DSP controller (forfive-level, one master and six slave DSPs).An approach to overcome the complexity of specifying

conventional multi-level SVM is to use phase-shifted, two-level SVM [with (m2 1) shifted carriers for the m-levelinverter]. This approach reduces DSP execution time asthe number of levels increases, but phase-shifted carriers(up-down counters) are needed which may not be availablein most DSPs, especially for higher levels. To overcome thisproblem, mapped phase-shifted SVM (MPS-SVM) is pro-posed, which uses only one up-counter [avoiding (m2 1)up-down counters with phase shifts].The conventional two-level SVM technique involves

vectorially equating the volt–second integral of a desiredreference voltage vector to the nearest three-space states,which are realisable by the inverter. For the two-levelinverter shown in Fig. 1a, a transformation from three totwo phases is performed to obtain the reference vectormagnitude

v�a

v�b

� �¼

1 �1

2�1

2

01

2

ffiffiffi3

p�1

2

ffiffiffi3

p

0B@

1CA v�a

v�bv�c

0@

1A (1)

Fig. 1 Two-level inverter and its space vector states

IET Electr. Power Appl., Vol. 1, No. 4, July 2007

The reference voltage vector magnitude is expressed as

V�ref ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiv�a� �2

þ v�b

� �2r(2)

whence the modulation index ma is defined as

ma ¼V �ref

E � cos p=3ð Þ(3)

Also, the rotating vector angle is

u ¼ tan�1v�b

v�a(4)

Fig. 1b represents the space vector states for the two-levelinverter. The vertices of the hexagon represent the six activestates of the inverter, whereas the hexagon centre representsthe two zero output states. For these states, ‘1’ means thatthe upper switch of the inverter phase leg, shown inFig. 1a, is ‘on’ and the lower switch is ‘off ’, and ‘0’means that the upper switch is ‘off ’ and the lower switchis ‘on’. Equating the volt–second integral over a samplingperiod (Ts) of the reference voltage vector and the nearestthree states gives

V �ref � Ts ¼ V1 � t1 þ V2 � t2 þ V0 � t0 þ V7 � t7 (5)

where t0, t1, t2 and t7 are the periods of the voltage vectorstates V0, V1, V2 and V7, respectively, and

Ts ¼ t1 þ t2 þ t0 þ t7 (6)

The voltage vector states V1 and V2 for all the six sectors areshown in Table 1, whereas the vectors V0 and V7 are the 000and 111 states, respectively. The corresponding timeperiods t0, t1, t2 and t7 are calculated from (5) and (6) and

t1 ¼ maTs sinp

3� u

� �(7)

t2 ¼ maTs sin uð Þ (8)

From (6)

t0 þ t7 ¼ Ts � t1 � t2 (9)

It is assumed that t0 and t7 are equally and symmetricallydistributed so that

t0 ¼ t7 ¼1

2Ts � t1 � t2� �

(10)

2 Phase-shifted SVM

Superposition theory can be applied to the multi-level inver-ter semiconductor switches. Conventional two-level SVM isapplied to each three-semiconductor switch group of the three

Table 1: States V1 and V2 bounding each sector

Sector States

V1 V2

1 100 110

2 010 110

3 010 011

4 001 011

5 001 101

6 100 101

623

phases and their complementary groups in the multi-levelinverter. A pre-calculated shift in time is introduced into theup-down counters of each switch group, then the output issummed and the required output voltage is obtained.

The phase shift depends on the number of levels. Themost important advantage of this approach is the simplicityin dealing with the multi-level inverter states, which in turnreduces DSP execution time. But the advantage of redun-dant sequence paths is lost and also there may be aproblem of DSP phase-shifted carriers (up-down counters)for a high number of levels.

2.1 Phase-shifted SVM (PS-SVM) implementation

For the five-level cascaded multi-level inverter (the first twocells of each phase shown in Fig. 2), the 24 switches aredivided into four groups (each group represents a leg ofone cell). These groups can be defined as follows:

† (Sa1, Sb1, Sc1) and their complementary;† (Sa4, Sb4, Sc4) and their complementary;† (Sa5, Sb5, Sc5) and their complementary;† (Sa8, Sb8, Sc8) and their complementary.

Two-level SVM is used for each group but the up-downcounters are shifted in time as in the phase-shift carrierbased PWM control technique in [16, 17].

This time shift (tps) depends on the number of levels, m,and the sampling time, Ts

tps ¼2Ts

m� 1(11)

The up-down counter used for the three-level inverter isshown in Fig. 3a. The three-level inverter is divided intotwo groups, so there are two up-down counters shifted byðTs ¼ ð1=2ÞTswÞ. The up-down counts used for the five-levelinverter are shown in Fig. 3b, where the up-down countersare shifted by ðð1=2ÞTs ¼ ð1=4ÞTswÞ. The times (t0, t1, t2 andt7) are calculated using (7), (8) and (10) and then comparedwith the shifted up-down counters to obtain the requiredoutput. The modulation index for m-levels is defined as

ma ¼V �ref

(m� 1)E � cos p=6ð Þ(12)

where E is the voltage per unit cell.

624

With this method, PWM is simplified but the switchinglosses are increased by (m2 1) times that with normalmulti-level SVM. But the carrier harmonics are shiftedto (m2 1) fs instead of fs, as with normal multi-levelSVM, where fs ¼ 1/Tsw. Also the complexity of thestates in normal multi-level SVM is avoided withPS-SVM.

2.2 Double Fourier series (DFS)

In carrier-based PWM, the switched waveform is gener-ally periodic in time for both the modulating signal fre-quency, vm, and the carrier frequency, vc, so that itcannot be expressed as a Fourier series. It can be rep-resented as a double summation series of two orthogonalsinusoidal functions (one in terms of the modulatingsignal frequency and the other in terms of the carrierfrequency).The DFS of a function f(x, y) can be expressed as [18]

f (x, y) ¼a002

þX1n¼1

[a0n cos (ny)þ b0n sin (ny)]

þX1k¼1

[ak0 cos (kx)þ bk0 sin (kx)]

þX1n¼�1n=0

X1k¼1

[akn cos (kxþ ny)þ bkn sin (kxþ ny)]

(13)

where x ¼ vct, y ¼ vmt, and

akn ¼1

2p2

ð2p0

ð2p0

f (x, y) cos (kxþ ny) dx dy (14)

bkn ¼1

2p2

ð2p0

ð2p0

f (x, y) sin (kxþ ny) dx dy (15)

ckn ¼

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffia2kn þ b2kn

q(16)

In phase-shifted SVM (PS-SVM) for an m-level inverter,the DFS of (m2 1) space vector modulated levels can be

Fig. 2 Seven-level cascaded inverter


Fig. 3 Up-down counters

a Three-level inverterb Five-level inverterc Seven-level inverter

expressed as

f (x, y) ¼Xl¼m�2

l¼0

a002

þXn¼1

n¼1

{a0n cos (ny)þ b0n sin (ny)}

"

þXk¼1

k¼1

ak0 cos kxþ l2pk

m� 1

� ��

þbk0 sin kxþ l2pk

m� 1

� �

þXn¼1

n¼�1n=0

Xk¼1

k¼1

akn cos kxþ nyþ l2pk

m� 1

� ��

þbkn sin kx0 þ nyþ l2pk

m� 1

� �(17)

From (16), the harmonic components are at (m2 1)vc andits multiples and the harmonic components atvc, 2vc, . . . , and (m� 2)vc and their multiples sum tozero (as proved in Appendix 7.1). Table 2 shows the harmo-nic components at vc, 2vc, . . . , 6vc for a seven-levelinverter.


2.3 Simulation

PS-SVM is simulated using Matlab/Simulink. Figs. 4a–dshow the line voltage THD (as defined in Appendix 7.2)of PS-SVM and normal multi-level SVM for the four differ-ent levels. From these figures, it is concluded that the THDof normal multi-level SVM is better than that of PS-SVM,for all modulation indices.

Figs. 5a–d compare the line voltage distortion factor(DF) of PS-SVM, normal multi-level SVM and normalSVM with the same switching frequency per switch asin PS-SVM (2fs, 4fs, 6fs and 8fs for the four differentlevels, respectively). From these figures, for the sameswitching frequency fs, it is concluded that the DF ofPS-SVM is better than that with normal multi-levelSVM because of the shift in the harmonic component to(m2 1) fs compared to fs in normal multi-level SVM.The exception is for three-level SVM, where the harmoniccomponent shifts for PS-SVM cannot compensate theincrease in magnitude, which worsens the DF comparedto normal multi-level SVM. Table 3 summarises a charac-teristic comparison between PS-SVM and normal multi-level SVM.

Table 2: Harmonic components at vc, 2vc, ., ., 6vc for a seven-level inverter

Frequency vc 2vc 3vc 4vc 5vc 6vc

x 2x 3x 4x 5x 6x

xþ p/3 2xþ 2p/3 3xþ p 4xþ 4p/3 5xþ 5p/3 6x

xþ 2p/3 2xþ 4p/3 3x 4xþ 2p/3 5xþ 4p/3 6x

xþ p 2x 3xþ p 4x 5xþ p 6x

xþ 4p/3 2xþ 2p/3 3x 4xþ 4p/3 5xþ 2p/3 6x

xþ 5p/3 2xþ 4p/3 3xþ p 4xþ 2p/3 5xþ p/3 6x

Psin & cos 0 0 0 0 0 =0

625

Fig. 4 Line voltage THD of PS-SVM and normal multi-level SVM

a Three levelb Five levelc Seven leveld Nine level

Fig. 5 Line voltage DF of PS-SVM and normal multi-level SVM

a Three levelb Five levelc Seven leveld Nine level


Table 3: Comparison between PS-SVM and normal multi-level SVM

Phase-shifted SVM Normal SVM

counter (m2 1) counters shifted from each other by

Tsw/(m2 1)

single counter

total number of switchings per

fundamental cycle

higher, [(m2 1) times that of generalised SVM] lower

line voltage THD worse better

line voltage DF better worse

harmonic spectrum shifted to (m2 1)fs shifted to fs

execution time 18 ms 44 ms

redundant sequence of paths no yes

complexity the well-known two-level SVM more complex

dv/dt a transition of more than one level may be in the

line voltage

lower

states the eight states of the well-known two-level SVM

are used

more complex (m3 states for

m-levels)

line voltage fundamental the same

number of levels used for odd number of levels used for odd and even number

of levels

Fig. 6 Switching cycle of the two shifted up-down counters inthree-level SVM

a First groupb Second group


Fig. 7 One switching cycle of the up-down counters for fivelevels

a Case (1)b Case (2)

627

Fig. 8 One switching cycle of the up-down counters of the third, fourth, fifth and sixth groups for the three different cases


629

Fig. 9 Conditions and sequences for the three different cases for the third, fourth, fifth and sixth groups


3 Mapped phase-shifted SVM

A new approach, mapped phase-shifted SVM, for multi-level SVM is presented. The approach is based on superpo-sition theory, as in PS-SVM, where conventional two-level

Fig. 10 Up-down counters for

a Threeb Fivec Sevend Nine levelse Even (m21)/2f Odd (m21)/2

630

SVM is applied to each three-semiconductor switch groupof the three phases and their complementary groups in themulti-level inverter. In the proposed approach, a mappingof the phase-shifted up-down counters to one up-counteris proposed, giving the same output as with PS-SVM.

3.1 Mapped phase-shifted (MPS-SVM)implementation

In MPS-SVM, the effect of phase shifting the up-downcounters is mapped into the sampling time distributionamong the nearest three states thereby necessitating onlyone up-counter, yet producing the same output as in phase-shifted SVM. In the following subsections, MPS-SVM forthree, five and seven levels is explained and then general-ised to the m-level inverter.

3.1.1 Three-level mapped phase-shifted SVM: InPS-SVM for the three-level cascaded-type inverter (thefirst cell of each phase shown in Fig. 2), there are twogroups of semiconductor switches. The first group is Sa1,Sb1 and Sc1 and their complement are Sa3, Sb3 and Sc3.The second group is Sa4, Sb4 and Sc4 and their complementare Sa2, Sb2 and Sc2. Note that the main switches of eachgroup are in grey. These two groups can be treated as ifthey are separate two two-level inverters controlled by con-ventional two-level SVM but with two up-down countersshifted by 1/2 Tsw, as shown in Fig. 6.As shown in Fig. 6a, to effectively obtain two shifted

up-down counters in PS-SVM using only one up-counter,

Fig. 11 Groups lower than (m2 1)/2


Fig. 12 Groups higher than (mþ 1)/2

where i is defined as in Table 4. The maximum value of i is ı̂ ¼ int(m-2/4)where int is the function that rounds down to the nearest integer

the switching cycle starts from t0, t1, t2, 2t7, t2, t1, then t0(for the first effective up-down counter). In Fig. 6b toeffect a 180 8 phase-shifted carrier (the second effectiveup-down counter) using the same up-counter, the sequencestarts from t7, t2, t1, 2t0, t1, t2, to t7. Thus, the oneup-counter effectively gives the two shifted carriers indi-cated in Figs. 6a and b.So for three-level SVM, the sequence is reversed to effect

the second up-down counter with respect to the firstup-down counter, using only one up-counter. Mapping thetwo up-down counters into one up-counter results in a rotat-ing sequence (for sector 1) for the two groups as shownin Fig. 6.

3.1.2 Five-level mapped phase-shifted SVM: Inphase-shifted SVM for the five-level cascaded-type inverter(the first two cells of each phase shown in Fig. 2), there arefour groups of semiconductor switches.

Group 1 is Sa1, Sb1 and Sc1 and their complement are Sa3,Sb3 and Sc3..Group 2 is Sa4, Sb4 and Sc4 and their complement are Sa2,Sb2 and Sc2..Group 3 is Sa5, Sb5 and Sc5 and their complement are Sa7,Sb7 and Sc7..Group 4 is Sa8, Sb8 and Sc8 and their complement are Sa6,Sb6 and Sc6..


The main switches of each group are shown in grey. Thefour groups can be treated as if forming four separate two-level inverters controlled by conventional two-level SVMbut with four up-down counters each shifted by (1/4) Tsw,as shown in Fig. 3b. Mapping of the up-down counters forthe first and fourth groups is the same as in Section 3.1.1.Mapping of the up-down counters for the second and thirdgroups involves two cases

Case (1): t7 þ t2 , ð1=2ÞTs

Fig. 7a illustrates case (1) for the second and third groups,over one switching cycle such that t7 þ t2 , ð1=2ÞTs.

The third group sequence starts and ends with a state cor-responding to time (t1), as shown in Fig. 7a. The start time(t1start) is defined as

t1start ¼1

2Ts � t0 (18)

whereas the end time (t1end) is defined as

t1end ¼1

2Ts � t7 � t2 (19)

and the state sequence is indicated in Fig. 7a.For the second group, the sequence starts and ends with

the state corresponding to time (t1), as shown in Fig. 7a.

631

Fig. 13 Simulated power density spectrum using MPS-SVM

a Threeb Fivec Seven levels at ma ¼ 0.9, fSW ¼ 3 kHz

The start time (t=1start) is defined as

t=1start ¼

1

2Ts � t7 � t2 (20)

whereas the end time (t=1end) is defined as

t=1end ¼

1

2Ts � t0 (21)

and the state sequence is indicated in Fig. 7a.

Case (2): t7 þ t2 � ð1=2ÞTs

Fig. 7b illustrates case (2) for the second and third groups,over one switching cycle, where t7 þ t2 � ð1=2ÞTs.

The third group sequence starts and ends with a state cor-responding to time (t2), as shown in Fig. 7b. The start time(t2start) is defined as

t2start ¼1

2Ts � t0 � t1 (22)

whereas the end time (t2end) is defined as

t2end ¼1

2Ts � t7 (23)

and the state sequence is indicated in Fig. 7b.For the second group, the sequence starts and ends with

the state corresponding to time (t2), as shown in Fig. 7b.

632

The start time (t=2start) is defined as

t=2start ¼

1

2Ts � t7 (24)

whereas the end time (t=2end) is defined as

t=2start ¼

1

2Ts � t7 (25)

and the sequence of states is indicated in Fig. 7b.

3.1.3 Seven-level mapped phase-shifted SVM: Theseven-level cascaded-type inverter is shown in Fig. 2and as with three- and five-level SVM, this inverter canbe divided into six groups. The main switches ofthese groups are shaded grey. These six groups can betreated as if they are six separate two-level inverters, con-trolled by conventional two-level SVM but with sixup-down counters each shifted by 1/6 Tsw, as shown inFig. 3c.The first and sixth groups are mapped as in three-level

SVM. Mapping of the remaining four groups involves threecases. Fig. 8 indicates one switching cycle for each ofthese groups, for the three different cases and Fig. 9 summar-ises the conditions and sequences for each case.

3.1.4 m-level mapped phase-shifted SVM: To gener-alise the SVM concept to the m-level inverter

† There are (m2 1) up-down counters;


† If the up-down counters are classified according to theintersection with the y-axis (in Fig. 10) as follows:

† The first point on the y-axis (reference point) rep-resents the first group (1st) and the last point representsthe (m2 1)th group (as shown in Fig. 10).† For the remaining (m2 3) groups, the even groups(Figs. 11 and 12) have a positive slope and the oddgroups have negative slope at the intersection with they-axis.

† The first group (1st) and the last group [(m2 1)-th] areas for three-level MPS-SVM, as explained in Section3.1.1.† If 1/2 (m2 1) is even, the 1/2 (m2 1)th and 1/2(m2 1) groups are the same as the corresponding groups

Table 4: Generalisation of parameter i

i k ¼ Groups lower

than (m2 1)/2

k ¼ Groups higher

than (mþ 1)/2

Levels

1 2nd, 3rd 4th, 5th 7

6th, 7th 9

1 2nd, 3rd 8th, 9th 11

10th, 11th 13

2 4th, 5th 6th, 7th 11

8th, 9th 13

1 2nd, 3rd 12th, 13th 15

14th, 15th 17

2 4th, 5th 10th, 11th 15

12th, 13th 17

3 6th, 7th 8th, 9th 15

10th, 11th 17

generally int(k/2) int(m2 k/2) m-level

where k is the group order number


for five-level MPS-SVM (second and third), in Section3.1.2.

Fig. 10 shows the interpretation when 1/2 (m2 1) is evenand odd, respectively.

3.2 Simulation

MPS-SVM is simulated using Matlab/Simulink.Figs. 13a–c show the power density spectrum forMPS-SVM with three, five and seven levels at a modulationindex of 0.9 and 3 kHz switching frequency. The harmonicsare concentrated at (m2 1)fsw and its multiples (at 6, 12 and18 kHz and their multiples for three, five and seven levels,respectively).

3.3 Practical results

The proposed MPS-SVM algorithm is implemented usingDSP software, which calculates the timing distribution ofthe states (t0, t1, t2 and t7) and the corresponding statesfor the FPGA-based AED106 daughterboard. The executiontime of the control algorithm for MPS-SVM is 26 ms (forTMS320C6701), whereas it is 44 ms for generalised multi-level SVM (and 18 ms for PS-SVM). PWM generation andthe underlap time for the switches (640 ns) are implementedin Xilinx. Figs. 14a and b show the output line voltage,phase current and spectrum for MPS-SVM at a modulationindex (ma) of 0.866 (linear modulation). Figs. 14c and dshow the same outputs but for ma ¼ 2 (over modulation).

4 Five-level APF results

Mapped phase-shifted SVM is implemented as a PWMtechnique for a shunt active power filter five-level basedinverter. As shown in Fig. 15, the line voltage has a

Fig. 14 Practical line voltage and phase current and spectrums for MPS-SVM

a and b For modulation index (ma) ¼ 0.866c and d For modulation index (ma) ¼ 2 (power factor of 0.938 lag) (100 v/div and 2 A/div)

633

Fig. 15 Practical results for the five-level active power filter

a Load current and its spectrum (5 A/div)b Supply current and its spectrum (5 A/div)c Active filter current and its spectrum (2.5 A/div)d Inverter output line voltage and its spectrum (400 V/div)

spectrum where the first harmonic component appears at 4fc(48 kHz where the switching frequency is 12 kHz). Table 5presents the filtering characteristics.

5 Conclusion

A variety of two-level modulation techniques have beenpreviously adopted for use in multi-level inverters,thereby simplify the process of PWM generation, at theexpense of increasing the switching losses when comparedto holistic modulation techniques. Previously, when extend-ing these two-level approaches, the timer burden becomessevere.

The proposed PS-SVM has the shortest execution timealthough retaining many of the advantages of SVM formulti-level inverters. The harmonic spectrum of thisscheme is poorer in terms of THD when compared tonormal multi-level SVM, but superior if a DF figure of

Table 5: Filtering characteristics for a three-phase,diode bridge feeding a resistive load

Load current, % Supply current

using MPS-SVM, %

Fundamental 100 118

5th 23 6.5

7th 12.9 1.3

11th 7.2 2.9

13th 7 2.6

17th 5.5 2

THD 28.7 5.8

634

merit is used. The penalty of using this technique is anincreased number of switching transitions, which givesincreased switching losses. In practice, this may be a deci-sive limiting feature.The advantage of MPS-SVM over PS-SVM is that it

needs only one up-counter for m-levels, which in turnsuits DSP-implementation. But DSP execution time forMPS-SVM is increased and increases as the number oflevels increases. Also an asymmetrical sampling character-istic is not a feature of MPS-SVM.In all cases, for a given switching frequency per switch,

conventional SVM is better in terms of THD and DF, butresults in the longest DSP execution time, which dependson the number of levels.

Fig. 16 Geometric wall model for three-level PS-SVM


6 References

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2 Veenstra, M., and Rufer, A.: ‘PWM-control of multi-levelvoltage-source inverters’. Proc. Conf. IEEE PESC, 2000, vol. 3,pp. 1387–1393

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7 Appendices

Appendix 7.1

As MPS-SVM is a mapping of symmetrical samplingPS-SVM, and PS-SVM is conventional two-level SVMwith (m2 1) shifted up-down counters, so a DFS is thesummation of (m2 1) level carrier shifted, two-levelSVM. The DFS of symmetrically sampled two-levelSVM has been previously considered in [19]. Thecoefficients of the side band harmonics have beenderived. The point of interest here is the effect of theequally shifted up-down counters on the DFS whenusing symmetrically sampled PS-SVM (and in turn, theeffect of MPS-SVM).Fig. 16 indicates the geometric wall model for three-level

PS-SVM (for simplicity) where there are two up-down


counters shifted by p. For m-levels there are (m2 1) linesrelating the y-axis to the x-axis. For natural sampling, thewalls are defined as

x� 2 gp ¼p

2�p

2vsvm( y)

x� 2 gp ¼3p

2þp

2vsvm( y) (26)

For all integers g [ [�1, þ1] andy ¼ ðvm=vcÞx ¼ (1=p)x

vsvm( y) ¼ma cos (vmt �

p

6) 0 � vmt ,

p

3ffiffiffi3

pma cos (vmt)

p

3� vmt ,

p

2

8<: (27)

where ma is the modulation index.The DFS coefficients (for per unit value of the cell

voltage) are defined as

Ckn ¼1

2p2

ð2p0

ð2p0

F(x, y)e j(kxþny) dx dy (28)

For symmetrical, regular sampling, the walls are definedas [applying the following variable transformation (x, y)to (x, y-x/p)] as [19]

x� 2 gp ¼p

2�p

2vsvm y�

x

p

� �

x� 2 gp ¼3p

2þp

2vsvm y�

x

p

� �(29)

and the DFS coefficients are defined as

Ckn ¼1

2p2

ð2p0

e jny

ð3p2þp

2vsvm(y)

p2�p

2vsvm(y)

e j(q=p)x dx dy (30)

where q ¼ kpþ n.Expanding (30) for all six sectors

Ckn ¼XVIi¼I

Ckn,i (31)

where to Ckn,i are the values of (31) over the rangey [ [p=3(i� 1), ðp=3Þi], where i ¼ 1, . . . , 6. Ckn,I can bewritten in the following form

Ckn,I ¼1

2p2

ðp=30

e jny

ð3p2þ

map

2cos (yðp=6Þ)

p2�

ma2cos (yðp=6Þ)

e j(q=p)xdx dy

!

(32)

For m-level PS-SVM, there are (m2 1) up-down countersshifted by 2p/(m2 1) so that in the geometrical wallmodel in Fig. 16, there are (m2 1) lines relating x to yand shifted from each other by 2p/(m2 1) with respectto the x-axis. Fig. 16 indicates the three-level case wherethe two lines are shifted byp. Using two-level SVM,(m2 1) shifted up-down counters are used in an m-levelinverter. So symmetrically sampled two-level SVMdouble Fourier integrals are used (m2 1) times but with

635

the following x-axis transformation

x� l2p

(m� 1)where l is 0, 1, 2, . . . , (m� 1) (33)

Generally, the following (x, y) variable transformation

x� l2p

(m� 1), y�

1

px (34)

for the (m2 1) shifted up-down counters is applied.Therefore Ckn,I ,l for the (lþ 1)th up-down counter can be

expressed as

Ckn,I ,l ¼1

2p2

ðp3

0

e jnye j(l(k2p=(m�1)))

�

�

ð 3p2ð Þþ

map

2ð Þ cos (y�(p=6))

p2ð Þ�

map

2ð Þ cos (y�(p=6))

e j(q=p)x dx dy

#(35)

Performing the integration in (35) with respect to x gives

Ckn,I ,l ¼1

2p2

� ðp3

0

e jnye j(l(k2p=(m�1)))

� e j{(ma=2p)( cos ( y�(p=6)))}� ��

� e j(3qp=2p)� e j(qp=2p)

� � dy

(36)

From the quarter symmetry of the modulating function, andgathering all terms in (31), results in

Ckn,l ¼ jp

qp2FknCkn e

j(l(k2p=(m�1))) (37)

where

Fkn ¼ e j(3qp=2p) � (�1)n e j(qp=2p) (38)

and

Ckn ¼

� ðp3

0

cos (ny) e j{(mapq=2p)( cos ( y�(p=6)))}�

þ(�1)n e j{(mapq=2p)( cos ( y�(p=6)))} dy

(39)

636

Note that Fkn and Ckn are not functions of l. Integration of(31) using the Jacobi–Anger series (in terms of a Besselfunction) and substituting in (37), the side bands can befound, as in [19]. For the total DFS coefficients

Ctotalkn ¼

Xm�2

l¼0

Ckn�l (40)

so that

Ctotalkn ¼ j

p

qp2FknCkn

Xm�2

l¼0

e j(l(k2p=(m�1))) (41)

Let

Lkn ¼ jp

qp2FknCkn (42)

then substitute (42) into (41) yields

Ctotalkn ¼ Lkn

Xm�2

l¼0

e j(l(k2p=(m�1))) (43)

The summation in (43) is zero except for k ¼ (m2 1) andits multiples, which means that the harmonics and theirside bands have been transferred to (m2 1) times thecarriers frequency.

Appendix 7.2

The THD and DF are defined as follows

THD ¼1

V1

ffiffiffiffiffiffiffiffiffiffiffiffiffiXh=1

V 2h

s(44)

DF ¼1

V1

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiXh=1

Vh

h

� 2vuut (45)

where h is the harmonic order.


mapped phase-shifted space vector modulation for multi-level voltage-source inverters

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