map notes_ chapter 2 part 2

7/24/2019 MAP Notes_ CHapter 2 Part 2

1/11

MAP notes

Chapter 2: 16 Bit Microprocessor: 8086 Part 2

MINIMUM MODE CONFIGUR!ION

In minimum mode configuration MN/MX = 1. It consists of 8284 clock generator and reset circuit.

Tree octal latces !I" 8282# are used to demulti$le% te address/data lines and 2 octal Transrecie&ers !I"

828'# are used as data am$lifiers for te transmission of data to te memor( or i/o from te

micro$rocessor and &ice &ersa.

In tis mode all te control signals are gi&en out )( te micro$rocessor itself. *nl( a single $rocessor is

$resent on te s(stem.

Te latces gets acti&ated +en te A,- signal from te micro$rocessor goes ig +ic is connected to

T0 $in of te *ctal latc. Tis allo+s address to )e a&aila)le on te out$ut of latc after T1 state.


2/11

Te Transrecie&ers a&e t+o $ins *- and T. Te Transrecie&ers gets acti&ated +en it recei&es a lo+

signal on te *- $in from te micro$rocessor $in -N.

To select te direction of data T/ is connected to T $in of te Transrecie&ers. 3en T/ = 1

direction of data is from te micro$rocessor and +en T/ = direction of data is to+ards te

micro$rocessor.

I" 8284 clock generator is used to $ro&ide clock signals !timing signals# to te $rocessor so tat all te

o$erations of te $rocessor are $ro$erl( s(ncroni5ed and +ork according to $ro$er timing signals.

Te +ait state generator is used to add +ait states +en a slo+ $eri$eral is connected to te $rocessor.

!IMING DIGRM OF MINIMUM MODE

Me"or# rea$ "achi%e c#c&e

uring T1 or te 1st clock $ulse. Te read )us c(cle starts and &alid address is latced togeter +it

setting minimum and ma%imum mode = 617 in$ut out$ut or memor( interface = 617 data transmit and

recei&e = 67 i.e. mode of )uffer I". uring T2 te ead control signals are issued and data ena)le signal

= 67 is asserted. Note tat during tis state te -A signal is also cecked to insert +ait status if

needed. uring T9 te data from te memor( is read )( sam$ling te data )us at te end of T1. uring

T4 all )us signals are deacti&ated in $re$aration for te ne%t clock c(cle.


3/11

Me"or# 'rite "achi%e c#c&e

uring T1 state or te 1st clock $ulse te +rite )us c(cle starts and &alid address is latced togeter +it


recei&e mode = 617 of )uffer I". uring T2 te +rite control signals are issued and data ena)le signal is

asserted. Note tat during tis state te -A signal is also cecked to insert +ait status if needed.

uring T9 te data from te memor( is +ritten )( sam$ling te data )us at te end of T1. uring T4 all

)us signals are deacti&ated in $re$aration for te ne%t clock c(cle.


4/11

IC 828( )C*OC+ GENER!OR,

Te 8284 clock generator consist of a reset circuitr( +ic is used to reset te micro$rocessor.

3en a lo+ signal is a$$lied to te - $in of te clock generator it sends a ig signal to te --T

$in of te $rocessor tere)( restarting te $rocessor !re)oot te $rocessor#.

*nce )ooted a logic 1 a$$ears on te - $in as te ca$acitor gets carged to :;


5/11

-(*./-/ )Octa& *!C,

An octal latc as 8 @latces and 8 tri@state )uffers.

Te 4,99 octal latc as t+o control in$uts 6-na)le7 !B# and 6*ut$ut "ontrol7 !*"#.

Te 6-na)le7 control is acti&e ig and is connected to ", in$uts of all 8 latces. ,ogic I in ", in$ut

+ill store te logic le&els $resent at in$uts in res$ecti&e latces.

Te 6*ut$ut "ontrol7 signal is acti&e@lo+ and is connected to control in$uts of all 8 tri@state )uffers.

,ogic * +ill ena)le te )uffers to out$ut data from res$ecti&e latces.

Te latc Intel 8282 $ro&ides te same functionalit( of 4,99


6/11

-(*.2( )Bi$irectio%a& B33er,

3e kno+ tat 4,24; is a )i@directional 8@)it )uffer.

It as I signal to control te direction of data flo+.

3en I signal is lo+ data flo+ is from 0 to A and +en it is ig data flo+ is from A to 0.

It also as B signal +ic +en acti&ated ena)les te )uffer.


7/11

8288 Bs co%tro&&er

Te in$ut to te )us controller are te status signals from te micro$rocessor in ma%imum mode.

Te out$ut of te )us controller are te control signals +ic are re?uired to dri&e te latces and

Transrecie&ers.

Also control signals suc as M-M M-M3 I* I*3 are also generated from te )us controller.

3ic signals sould )e generated de$ends on te status of te status signals to te )us controller.

efer 21 status signals section.


8/11

Ma4i"" "o$e operatio%

As +e can see in te )lock diagram ma%imum mode is te mode in +ic more tan one $rocessor is

$resent on te s(stem.

Terefore te control signals re?uired to dri&e te latces and Transrecie&ers are generated )( te )us

controller.

Also control signals re?uired for memor( selection and io selection are generated )( te )us controller.

Te )us controller gets status signals from te micro$rocessor +ic gi&es te status of te o$eration to

)e $erformed.

Te remaining $ins +ic +ere used in minimum mode )ut no+ teir functionalit( canged in ma%imum

mode are used for re?uest and grant signals to oter $rocessors on te s(stem.


9/11

!IMING DIGRM OF M5IMUM MODE

Me"or# rea$ "achi%e c#c&e

Te timing diagram for 88' ma%imum mode memor( read o$eration is so+n in >igure. In

ma%imum mode status codes need to )e acti&e to generate control signals from )us controller. Cere

M"@signal is used instead of as in case of minimum mode 2 1 and are acti&e and are used to

generate control signal troug te )us controller.

uring T1 or te 1st clock $ulse. Te read )us c(cle starts and &alid address is latced togeter +it


recei&e = 67 i.e. mode of )uffer I". uring T2 te ead control signals are issued and data ena)le signal

is asserted = 617. Note tat during tis state te -A signal is also cecked to insert +ait status if

needed. uring T9 te data from te memor( is read )( sam$ling te data )us at te end of T1. uring



10/11

Me"or# 'rite "achi%e c#c&e

The timing diagram for 8086 maximum mode memory write operation is

shown in Figure. The control signal logic levels and timing diagram are similar to

that of read operation, except for data transmit and receive, memory read and write

signals. Here the T-states correspond to the time during which !" is low, #$%T!

control goes low, T&$ is high and data output is availa'le from the processor on the

data 'us.

uring T1 state or te 1st clock $ulse te +rite )us c(cle starts and &alid address is latced togeter +it


recei&e mode = 617 of )uffer I". uring T2 te +rite control signals are issued and data ena)le signal =

617 is asserted. Note tat during tis state te -A signal is also cecked to insert +ait status if


11/11

needed. uring T9 te data from te memor( is +ritten )( sam$ling te data )us at te end of T1. uring


map notes_ chapter 2 part 2

Documents