magazine spring99 improvedyield

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Spring 1999 Yield Management Solutions 33 found that s-polarization and high sensitivity provided the best results, especially in open areas of low pattern density (figure 1). The second step of the process involved collecting data from the manufacturing line at that inspection point, to establish a baseline and determine what impact these defects had on yield. Analysis of the data indicated that defects introduced at the CMP steps produce a high potential for die loss. Based on this information, a team was formed to address the CMP processes as a source of high yield impact. At VLSI San Antonio, new inspection points were introduced to monitor inter- metallic oxide (IMO) chemical mechanical polish (CMP) layers, and tungsten CMP (WCMP) layers. A combination of defect monitoring using the AIT, defect review using the CRS and JEOL SEM stations, and analysis using Quest produced information that led VLSI to make changes to the way their CMP scrubbers and polishers are utilized. These changes provided significant benefit to the yield learning rate at the San Antonio facility. Introducing a new inspection point The process that VLSI used for determining whether a new inspection point should be introduced for post-CMP layers was comprised of several steps. First, the defect group characterized the proposed line moni- tor point. This involved setting up recipes on the AIT, and going through various combinations of polarizations and sensitivi- ty settings to determine which setup pro- vided the best capture of defects. In the case of CMP layers, success meant capturing the largest number of microscratches, shallow scratches, gouging and slurry residues while minimizing false counts. The defect group Improved Yield Learning Using CMP Equipment Monitors by Scott Hiemke, Dean Spaugh, John Givens, Albert Liu, Miguel Delgado, VLSI San Antonio; Rebecca Howland Pinto, Ph.D., KLA-Tencor When a new line monitoring point is introduced into a manufacturing line within a fab, it must be justified. This justification process involves careful experimentation to determine that process excursions are occurring at these points which have significant impact on yield. It involves verification that inspection and metrology tools are optimized to identify the relevant excursions, and it involves bringing together people from several different groups within the fab to cooperate on the solution. Finally, the solution must be implemented on the manufacturing line. cn pn sn CMP defects by polarization CMP defects high low CMP defects by sensitivity CMP defects Polarization Sensitivity Figure 1. A combination of s input polarization and high sensitivity set- tings on the AIT provided best capture of defects on CMP layers. Inspection F EATURES

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Page 1: Magazine spring99 improvedyield

Spring 1999 Yield Management Solutions 33

found that s-polarization and high sensitivity providedthe best results, especially in open areas of low patterndensity (figure 1).

The second step of the process involved collecting datafrom the manufacturing line at that inspection point,to establish a baseline and determine what impact thesedefects had on yield. Analysis of the data indicated thatdefects introduced at the CMP steps produce a highpotential for die loss. Based on this information, a teamwas formed to address the CMP processes as a source ofhigh yield impact.

At VLSI San Antonio, new inspectionpoints were introduced to monitor inter-metallic oxide (IMO) chemical mechanicalpolish (CMP) layers, and tungsten CMP(WCMP) layers. A combination of defectmonitoring using the AIT, defect reviewusing the CRS and JEOL SEM stations, andanalysis using Quest produced informationthat led VLSI to make changes to the way their CMP scrubbers and polishers are utilized. These changes provided significantbenefit to the yield learning rate at the San Antonio facility.

Introducing a new inspectionpointThe process that VLSI used for determiningwhether a new inspection point should be introduced for post-CMP layers wascomprised of several steps. First, the defectgroup characterized the proposed line moni-tor point. This involved setting up recipeson the AIT, and going through variouscombinations of polarizations and sensitivi-ty settings to determine which setup pro-vided the best capture of defects. In the caseof CMP layers, success meant capturing thelargest number of microscratches, shallowscratches, gouging and slurry residues whileminimizing false counts. The defect group

Improved Yield Learning Using CMP Equipment Monitors

by Scott Hiemke, Dean Spaugh, John Givens, Albert Liu, Miguel Delgado, VLSI San Antonio; Rebecca Howland Pinto, Ph.D., KLA-Tencor

When a new line monitoring point is introduced into a manufacturing line within a fab, it must be justified. Thisjustification process involves careful experimentation to determine that process excursions are occurring at these pointswhich have significant impact on yield. It involves verification that inspection and metrology tools are optimized toidentify the relevant excursions, and it involves bringing together people from several different groups within the fabto cooperate on the solution. Finally, the solution must be implemented on the manufacturing line.

cn pn sn

CMP defects by polarization

CM

P d

efec

ts

high low

CMP defects by sensitivity

CM

P d

efec

ts

Polarization Sensitivity

Figure 1. A combination of s input polarization and high sensitivity set -

tings on the AIT provided best capture of defects on CMP layers.

InspectionF E A T U R E S

Page 2: Magazine spring99 improvedyield

nine lots through the process flow, measuring filmthickness and defectivity after each CMP step. The AITwas particularly well suited to this application, becauseits high throughput meant that every wafer in the lotcould be scanned to enable characterization of wafer-to-wafer variation. Examples of defects found after WCMPand after IMOCMP are given in figure 3. Note that several defect types were captured well in areas of densepattern.

Following the defect inspection, the wafers were mea-sured on the UV-1280SE to characterize the variation

Spring 1999 Yield Management Solutions34

F E A T U R E S

The team and its charterThe team’s charter was to optimize the CMP processes:specifically, to minimize defects introduced at CMPsteps, and maximize true up-time of the CMP polishers.VLSI set goals and deliverables for the project, and setlimitations on allowable methods for addressing theproblems. For example, existing CMP consumables(pads and slurries) and equipment had to be utilized.Defect inspection and film thickness measurements werethe chief techniques employed to attack the problem.

The interdepartmental team, comprised of process engineers from the defect group, CMP engineering and CMP manufacturing, discovered that the first steptowards solution of the problem was to establish a control action system. This system is represented by aflow chart that documents ownership for each step ofthe decision of what to do with out-of-control lots. Theprocess of documenting responsibility through the con-trol action system proved invaluable in making progresstowards the goals of the project.

The culpritsOnce the control action system was in place, the teambegan its investigation by examining the effectivenessof the post-CMP scrub. They discovered that changingthe scrub process significantly reduced the number ofdefects left on the wafer. A comparison of the new andold scrub processes is given in figure 2, along withexamples of defects found after scrubbing. Introducingthe new scrub process made an immediate, positiveimpact on defectivity.

The second area investigated was the nonuniformity ofthe oxide layer after CMP. The team followed a set of

Def

ect n

umbe

r

Each pairstudent’s t0.05

•• •••••

•••

•••

•••

STD scrubprocess

New scrubprocess

Figure 2. Introducing a new scrub process made an immediate,

positive impact on defectivity.

Figure 4. Film thickness measurements (using the UV-1280SE) showed

a domed oxide profile, which negatively af fected edge die yield.

Figure 3. Examples of defects detected after WCMP and after

IMOCMP.

Film

Thi

ckne

ss

Defect from Old Scrub Recipe

Defect detected at IMO2CMP

Defect detected at WCMP1

Site on the Wafer

Page 3: Magazine spring99 improvedyield

CMP Manufacturing decided to change the pads morefrequently: three times more often to reduce the defectlevels. Introducing this inspection point has resulted ina dramatic change in the way maintenance is done onthe CMP polishers in this facility.

Faster yield learning now and in thefutureSince implementing the line monitoring methodologydescribed above, VLSI San Antonio has increased theiryield learning rate. A better yield learning rate trans-lates directly into higher profitability for the fab.Because of this success on their current products, VLSISan Antonio also elected to add an inspection point totheir below-0.25 µm development work, at shallow-trench isolation CMP (figure 6).

This paper is largely derived from a presentation first given in July 1998 atthe Yield Management Solutions Seminar during SEMICON/West.

Spring 1999 Yield Management Solutions 35

F E A T U R E S

in oxide thickness across the wafer (figure 4). The film thickness measurements showed that the oxide profile was domed, and as a result, edge die yield was negatively affected. This prompted the team to recommend tightening the specifications for post-CMPoxide uniformity.

Transfer to manufacturingThe last part of the team’s responsibility was to transferthe improved process to manufacturing. This meantthat the AIT had to be interfaced to PROMIS, VLSI’sWork In Progress (WIP) tracking system. Fortunately,more than 90 percent of the GEM/SECS code writtenoriginally for the Surfscan 7700 was transferable to theAIT. This ensured that the correct lot numbers, processlevels, recipes and data were being sent to Quest andtransferred to VLSI’s SPC system.

The line monitor was set up to monitor WIP in thequeue for a tool, and skip lots past the inspection stepsif more than a certain number of lots are waiting, or ifa recipe is missing. As a result of this setup, more than60 percent of the total volume are currently inspectedpost-CMP by scanning lots across 10 to 12 part types.In addition, over 50 percent of the other process layersare inspected on the AIT. At VLSI San Antonio, over19 process layers throughout the line are inspected bythe AIT.

The final step in transferring the process to manufac-turing involved training the CMP engineers and manu-facturing personnel to use Quest and the various reviewstations at their disposal.

The learning continuedOnce the improved process was successfully transferredto manufacturing, some other important discoverieswere made. One defectivity excursion at oxide CMPwas traced to a change in a drum of slurry, when thelines had been improperly flushed out (figure 5).

Another discovery was that just before a polishing padwas changed the defectivity level increased. As a result

Figure 5. Introduction of a line monitoring point helped trace defect excur-

sions to a faulty drum of slurry and wear and tear of a polishing pad.

Figure 6. Examples of defects found at a shallow trench isolation

(STI) CMP layer.

Avg

. de

fect

/waf

er (

#)

Time

Lots ran on polisher

after drum changePad changes