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July 2011Revision: EB60_01.1
MachXO2 Control Development Kit
User’s Guide
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
IntroductionThank you for choosing the Lattice Semiconductor MachXO2™ Control Development Kit!
This guide describes how to start using the MachXO2 Control Development Kit, an easy-to-use platform for rapidly prototyping system control designs using MachXO2 PLDs. Along with the evaluation board and accessories, this kit includes a pre-loaded control system-on-chip (Control SoC) design that demonstrates board diagnostic functions including I/O control, voltage monitoring, time-stamps and data logging to non-volatile memory. The Power Man-ager II ispPAC®-POWR1014A and 8-bit LatticeMico8™ microcontroller are featured in the board and demonstration design.
The contents of this user’s guide include demo operation, top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, switches, a complete set of schematics and bill of materials for the MachXO2 Control Evaluation Board.
Note: Static electricity can severely shorten the lifespan of electronic components. See the MachXO2 Control Development Kit QuickSTART Guide for handling and storage tips.
FeaturesThe MachXO2 Control Development Kit includes:
• MachXO2 Control Evaluation Board – The MachXO2 Control Evaluation Board features the following on-board components and circuits:
– MachXO2 LCMXO2-1200HC-csBGA132 PLD. The board is designed for density migration, allowing a higher-density MachXO2 device (up to 4000 LUTs) to be assembled on the board.
- Part number LCMXO2-1200HC-C-EVN is populated with the R1 silicon. For more information on the R1 to Standard migration refer to the AN8086, Designing for Migration from MachXO2-1200-R1 to Stan-dard (Non-R1) Devices.
– Power Manager II POWR1014A mixed-signal PLD – 4 Mbit SPI Flash memory– microSD (micro Secure Digital) memory socket– 60-ball VFBGA footprint for LPDDR memory. When populated, 128-Mbit LPDDR memory will be added to
the board.– Current and voltage sensor circuits– Voltage ramp circuits– Electret microphone– Audio amplifier and Delta-Sigma ADC– PWM analog output circuit– Audio output channel– Up to two DVI sources and one DVI output– Up to two 7:1 LVDS sources and one 7:1:VDS output– Expansion header for JTAG, SPI, I2C and PLD I/Os– LEDs and switches– Standard USB cable for device programming– RS-232/USB and JTAG/USB interface– RoHS-compliant packaging and process – AC adapter (international plugs)
• Pre-loaded Reference Designs and Demo – The kit includes the pre-loaded Control SoC demo design that integrates several Lattice reference designs including: the LatticeMico8 microcontroller, master WISHBONE bus controller, soft Delta-Sigma ADC, SPI master controller, UART peripheral, Embedded Block RAM and additional control functions.
• USB connector Cable – A mini B USB port provides a communication and debug port via a USB-to-RS-232 physical channel and programming interface to the MachXO2 JTAG port.
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
• AC Adapter (international plugs) with 5V DC output.
• QuickSTART Guide – Provides information on connecting the MachXO2 Control Evaluation Board, installing Windows hardware drivers, and running the Control SoC demo.
Figure 1 shows the top side of the MachXO2 Control Evaluation Board with comments on the specific features that are designed in the board.
Figure 1. MachXO2 Control Evaluation Board, Top Side
DVI Video Source USB 2.0Interface Socket
7:1 LVDSVideo Source
(Channel Link)
microSD Socket
MachXO2-1200/4000
DVIVideo Output
7:1 LVDSVideo Output
2x20 GPIO Header
GSR Push-buttonMachXO2 DIP Switches5V Power Indicator
Electret Microphone
Speaker/Headphone Jack
AC-DC Adapter Jack
MachXO2 LED Field
ADC Input (J9: Pin 2)POWR1014A
JTAG Device Select (J6),MachXO2 Position Shown
Note: The bill of materials of this board has the following limitations:
• Video Source 1 is available in both DVI and 7:1 LVDS interfaces. Video Source 2 is not populated.
• LPDDR memory component is not populated. This feature will be populated with greater MachXO2 device den-sity on the board.
• The initial MachXO2 device that is assembled on the board is LCMXO2-1200HC. The footprint is compatible with greater device densities and an LCMXO2-4000HC device is planned to be populated in future versions of the board.
Lattice Semiconductor DevicesMachXO2This board features a 3.3V MachXO2 PLD packaged in a 132-ball csBGA package. This package allows density migration to devices as large as 4340 LUTs. A complete description of this device can be found in the MachXO2 Family Handbook.
Power Manager IIThis board also features a Power Manager II mixed-signal PLD. The POWR1014A device serves as a general-purpose power supply monitor, reset generator, sequence controller, and high-voltage FET drivers. More information about Power Manager II devices can be found on the Lattice web site at www.latticesemi.com/products/powermanager.
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
Software RequirementsYou should install the following software before you begin developing designs for the evaluation board:
• Lattice Diamond™ 1.2 or higher
• ispVM™ System 17.9.1 or higher
Control SoC Demonstration DesignThe Control System-on-Chip (SoC) demonstration illustrates the use of the LatticeMico8 microcontroller, peripher-als, and firmware integrated to provide system control features such as power supply sequencing, voltage monitor-ing, data logging to nonvolatile memory, I/O control, embedded block RAM utilization, UART communication and PLL status monitoring.
• The Power Manager II device sequences the power-up of voltage rails on the board and performs reset distribu-tion.
• LatticeMico8 executable program initializes the peripherals that are embedded in the SoC design. During initial-ization, LatticeMico8 uploads the user menu on the HyperTerminal of a PC.
• Users interact with LatticeMico8 and the board through the HyperTerminal of a PC.
Figure 2. Control SoC Demo Block Diagram
MachXO2 Control Evaluation Board
MachXO2-1200
UART LEDs/DIP Switches
Timer/Counter
LatticeMico8Microcontroller
MasterSPI
SoftADC
SPIFlash
WISHBONE Bus
USB/RS232
AnalogSignal
PC
EmbeddedBlock RAM
Power management is handled in two phases by the MachXO2 Control Evaluation Board system:
1. Power On – After power is supplied to the board and the 3.3V rail is stable, the POWR1014A sequences four supply rails. Two circuits demonstrate the voltage ramp of 2N7002E power MOSFETs using the high-voltage (HVOUT) outputs and two demonstrate power rail enable of VCC_CORE and VCCP of the MachXO2 using digital outputs. Next, the POWR1014A asserts the MachXO2 reset. Finally, the POWR1014A enters a supply monitoring state.
2. Post Power On – During the second phase of power management, the board’s “condition” is monitored. Power supply rail voltage, and current is monitored by the POWR1014A. If any supply rail fails, the POWR1014A asserts a reset for the MachXO2.
MachXO2 Function – After the reset is de-asserted, LatticeMico8 initializes the peripherals embedded in the MachXO2 device and uploads the user menu onto the HyperTerminal window of a PC.
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 3. HyperTerminal User Menu
Users interact with LatticeMico8 microcontroller and the board by selecting the available options in the HyperTermi-nal menu. The available options are:
• ‘m’ – This option will re-display the main menu anytime during the demonstration.
• ‘a’ – This option will sample the voltage in the pin #2 of header J9. By default, the node is biased at 1.65V, which is half of the VCCIO = 3.30V. The voltage will be displayed in the HyperTerminal window. The ADC input voltage should be limited to the range 0 to 3.0V to avoid device damage.
• ‘s’ – This option will read the device ID of the SPI Flash on the board and display it in the HyperTerminal. The resulting ID is hexadecimal 0x44, which corresponds to AT25DF041A device.
• ‘t’ – This option samples and displays the elapsed time since the reset was de-asserted.
• ‘r’ - This option samples the DIP switches (reference designator SW1) on the board and displays the data in the HyperTerminal. Users can change the DIP switches on the board and press ‘r’ to display the new value.
• “0-9” – These are BCD numerical values that can be typed on the keyboard. The value will be received by LatticeMico8, which will update the LEDs (D0-D3) on the board.
• ‘l’ – This is a lower case ‘L’ character. Pressing ‘l’ will sample the voltage in pin #2 of header J9 and log the data in the SPI Flash device on the board. The WRITE page pointer will increment when ‘l’ is pressed. The initial value of the page pointer after power-up or after a reset is 0.
• ‘d’ – This option will read the data from SPI Flash device and display it on the HyperTerminal window. The READ page pointer will increment when ‘d’ is pressed. The initial value of the page pointer after power-up or after a reset is 0.
• ‘c’ – This option will clear (reset) the WRITE and READ page pointers.
• ‘e’ – This selection will perform a bulk-erase of the Flash memory in the SPI Flash device.
Setting up the BoardDrivers and FirmwareBefore you begin, you will need to obtain the necessary hardware drivers for Windows from the Lattice web site.
1. Browse to the www.latticesemi.com/MachXO2-control-kit and locate the hardware device drivers for the USB interface.
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
2. Download the ZIP file to your system and unzip it to a location on your PC.
Linux Support:
The USB interface drivers for the evaluation board are included in Linux kernel 2.4.20 or greater including distribu-tions compatible with Lattice Diamond design software (Red Hat Enterprise v.3, v.4 or Novell SUSE Enterprise v.10).
The Control SoC Demo is preprogrammed into the MachXO2 Control Evaluation Board, however over time it is likely that your board will be modified.
To download the demo source files and reprogram the MachXO2 Control Evaluation Board:
1. Download demo application source code from www.latticesemi.com/mxo2-control-kit.
2. Use .\Demo_MachXO2_Control_SoC\project\control_soc_demo.jed to restore the MachXO2280 Control SoC demo design.
3. Use .\Demo_PM_Control_BM\project\bm_demo.jed to restore the POWR1014A Board Management demo design.
Connecting to the MachXO2 Control Evaluation Board1. Plug the AC-DC adopter to an outlet.
2. Power the board by inserting the AC-DC adopter into the power jack with reference designator J11. Once the connection is made, a red LED with reference designator D12 will illuminate.
3. Connect the evaluation board to your PC using the USB cable provided. The USB connector in the board has reference designator J5.
4. If you are prompted, “Windows may connect to Windows Update”, select No, not this time from available options and click Next to proceed with the installation.
5. Choose the Install from specific location (Advanced) option and click Next.
6. Select Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder created earlier. Select the CDM 2.04.06 WHQL Certified folder and click OK.
7. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message indicating that the installation was successful.
Programming the PLDsThe three-pin header with reference designator J6 is used to select between the JTAG port of the MachXO2 or POWR1014A device. Installing a jumper in pins 1 and 2 of J6 will select the JTAG port of the POWR1014A device. Installing a jumper in pins 2 and 3 of J6 will select the JTAG port of the MachXO2 device.
Pin 1 of header J6 is marked on the silkscreen of the board with a white triangle as shown in Figure 4. This exam-ple shows the jumper installed in pins 2 and 3 of the J6 header and the JTAG port of the MachXO2 device has been selected.
Figure 4. J6 Header Used for Selecting the JTAG Port of the PLDs
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
Using ispVM System software, users can scan and perform JTAG operations, including programming, with the MachXO2 and POWR1014A devices.
Setting Up Windows HyperTerminalYou will use a terminal program to communicate with the evaluation board. The following instructions describe the Windows HyperTerminal program which is found on most Windows PCs. You may use another terminal program if desired although setup will be different. Windows 7 does not include HyperTerminal. Tera Term has been verified to work with Windows 7. For Linux, Minicom is a good alternative.
Note: This step uses the procedure for Windows XP users. Steps may vary slightly if using another Windows ver-sion.
1. From the Start menu, select Control Panel > System. The “System Properties” dialog appears.
2. Select the Hardware tab and click Device Manager. The “Device Manager” dialog appears.
Figure 5. Device Manager – COM Port
3. Expand the Ports (COM & LPT) entry and note the COM port number for the USB Serial Port.
4. From the Start menu, select Programs > Accessories > Communications > HyperTerminal. The HyperTer-minal application and a “Connection Description” dialog appear.
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 6. New Connection – COM Port
5. Specify a Name and Icon for the new connection. Click OK. The “Connect To” dialog appears.
6. Select the COM port identified in Step 3 from the Connect using: list. Click OK.
Figure 7. Selecting the COM Port
7. The “COMn Properties” dialog appears where n is the COM port selected from the list.
8. Select the following Port Settings and click OK.Bits per second: 115200Data bits: 8Parity: NoneStop bits: 1Flow control: None
Figure 8. COM Port Properties
9. The HyperTerminal window appears.
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
10. From the MachXO2 Control Evaluation Board, press the reset push-button with reference designator S1. The Control SoC demo main menu appears.
Setting Up Linux MinicomMinicom is a terminal program found with most Linux distributions. It can be used to communicate with the MachXO2 Control Evaluation Board.
To setup Minicom:
1. Check active serial ports:
#dmesg | grep tty
Note the tty label assigned to the USB port
2. From a command prompt, start Minicom:
#minicom –s
The configuration menu appears.
3. Highlight Serial port setup and press Enter. Serial port settings appear.
4. Press A (Serial Device). Specify the active serial device noted in Step 1 and press Enter.
5. Press E (Bps/Par/Bits). Specify 115200, None, 8 and press Enter.
6. Press F (Hardware Flow Control). Specify None and press Enter.
7. Press Esc. The configuration menu appears.
8. Select Save setup as dfl. Minicom saves the port setup as the new default.
9. Select Exit. The Minicom interface appears.
10. From the evaluation board, press the S1 push-button (GSR).The Control SoC demo main menu appears.
Ordering Information
Description Ordering Part NumberChina RoHS Environment-Friendly
Use Period (EFUP)
MachXO2 Control Development Kit LCMXO2-1200HC-C-EVN
Technical Support AssistanceHotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)e-mail: [email protected]: www.latticesemi.com
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
Revision HistoryDate Version Change Summary
April 2011 01.0 Initial release.
July 2011 01.1 Updated Features list with information on migration from MachXO2-1200-R1 to Standard (non-R1) devices.
© 2011 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
Appendix A. SchematicFigure 9. Architecture
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ispPAC POWR1014A
Power Manager II
MachXO2
Voltage Monitor
High Voltage Drivers
GPIO
2x20 Header
LPDDR 128Mb
SW & LEDs
Board Power
Managment
RESET
SW & LEDs
7:1LVDS Conn
DVI Conn
DVI to 7:1LVDS
Conversion
DVI Conn
DVI to 7:1LVDS
Conversion
7:1LVDS Conn
DVI Conn
7:1LVDS to DVI
Conversion
7:1LVDS Conn
7:1LVDS RX
7:1LVDS TX
ADC-DAC
SPI
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Crystal
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MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 10. VCC33, VCC18, VCC12
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Figure 11. ispPAC-POWR1014A
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15
HV
OU
T2
14
SM
BA
_OU
T3
13
OU
T4
12
OU
T5
11
OU
T6
10
OU
T7
9
OU
T8
8
OU
T9
6
OU
T10
5
OU
T11
4
OU
T12
3
OU
T13
2
OU
T14
1
TD
I18
AT
DI
17
TM
S16
TC
K22
TD
O21
TD
ISE
L19
SC
L39
SD
A38
VCCJ20
VCCD23
VCCPROG24
VCCA29VCCD41
VCCINP45
GN
DD
7G
ND
D31
GN
DA
30
RE
SE
TB
40M
CLK
43P
LDC
LK42
C83
1uF
DI
C83
1uF
DI
IO18
IO18
D10
LED
DI
D10
LED
DI
R19
820
0D
IR19
820
0D
I
C99
0_1u
FD
I
C99
0_1u
FD
I
C10
70_
1uF
DI
C10
70_
1uF
DI
C35
1uF
DI
C35
1uF
DI
SW
2
SW
DIP
_2D
I
SW
2
SW
DIP
_2D
I
R17
920
0D
IR17
920
0D
I
C89
0_1u
FD
I
C89
0_1u
FD
I
D9
LED
DI
D9
LED
DI
RN
4R
N2_
4_47
0D
I
RN
4R
N2_
4_47
0D
I
1234
8765
R19
6
1KD
I
R19
6
1KD
I
Q5
2N70
02E
DI
Q5
2N70
02E
DI
3
1
2
14
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 12. Power Current Sense
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
ICC
IO33
_NIC
CIO
33_P
ICC
_NIC
C_P
ICC
IO33
_P
ICC
IO33
_N
ICC
_P
ICC
_N
ICC
IO18
_NIC
CIO
18_P
ICC
IO18
_P
ICC
IO18
_N
VC
CIO
33
VC
C_C
OR
E
VC
CIO
18
VC
C33
VC
C33
VC
C18
VC
C12
VC
C33
VC
C33
VC
C33
VC
C33
PM
_OU
T8
[3,4
]
PM
_OU
T9
[4]
ICC
_Sen
se[4
]
ICC
IO33
_Sen
se[4
]IC
CIO
18_S
ense
[4]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Pow
er C
urre
nt S
ense
B
514
Tue
sday
, Feb
ruar
y 22
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Pow
er C
urre
nt S
ense
B
514
Tue
sday
, Feb
ruar
y 22
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Pow
er C
urre
nt S
ense
B
514
Tue
sday
, Feb
ruar
y 22
, 201
1
Mac
hXO
2 P
ower
Rai
ls
MachXO2 - Core Current
Cur
rent
Sen
se
MachXO2 - ICCIO18 Current
MachXO2 - ICCIO33 Current
C142, C143 to limit Vcc, Vccio
ramp rates to data sheet spec.
R19
110
0D
I
R19
110
0D
I
R18
410
0D
I
R18
410
0D
I
R60
220
DI
R60
220
DI
C91
0_01
uFD
I
C91
0_01
uFD
I
R23
52 D
I
R23
52 D
I
R18
93_
92K
DI
R18
93_
92K
DI
C10
5
0_1u
FD
I
C10
5
0_1u
FD
I
R58
0 DN
I
R58
0 DN
I
R59
1 DI
R59
1 DI
-+
U16
D AD
8604
AR
Z
-+
U16
D AD
8604
AR
Z12 13
14
4 11
IO15
IO15
-+
U16
CA
D86
04A
RZ
-+
U16
CA
D86
04A
RZ
10 98
4 11
IO9
IO9
R20
42K D
I
R20
42K D
I
R19
33_
92K
DI
R19
33_
92K
DI
IO7
IO7
Q7B
ZD
T75
8
DI
Q7B
ZD
T75
8
DI
1
27
8
R18
510
0D
I
R18
510
0D
I
R20
610
0D
I
R20
610
0D
I
-+
U16
B
AD
8604
AR
Z
-+
U16
B
AD
8604
AR
Z5 6
7
4 11C
380_
01uF
DI
C38
0_01
uFD
I
-+
U16
A
AD
8604
AR
Z
-+
U16
A
AD
8604
AR
Z3 2
1
4 11
R19
03_
92K
DI
R19
03_
92K
DI
C46
0_1u
FD
I
C46
0_1u
FD
I
IO14
IO14
R23
21K D
I
R23
21K D
I
R19
23_
92K
DI
R19
23_
92K
DI
R20
110
0D
I
R20
110
0D
I
IO8
IO8
R14
82 D
I
R14
82 D
I
C14
210
uF DI
C14
210
uF DI
C14
310
uF DI
C14
310
uF DI
C41
0_01
uFD
I
C41
0_01
uFD
I
R19
410
0D
I
R19
410
0D
I
C44
0_1u
FD
I
C44
0_1u
FD
I
R21
922
0
DI
R21
922
0
DI
Q7A
ZD
T75
8D
I
Q7A
ZD
T75
8D
I3
45
6
R19
72K D
I
R19
72K D
I
R67
1K DI
R67
1K DI
IO11
IO11
15
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 13. Configuration USB Port5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SH
LD_D
ebug
PM
_TD
I
PM
_TM
S
XO
2_T
DI
XO
2_T
MS
PM
_TD
OX
O2_
TD
O
PM
_TC
K
XO
2_T
CK
PM
_TD
I
PM
_TD
O
PM
_TM
S
XO
2_T
DI
XO
2_T
DO
XO
2_T
MS
PM
_TC
KX
O2_
TC
K
Dp
FT
_EE
CS
FT
_EE
CLK
FT
_EE
DA
TA
Dm
FT
_EE
DA
TA
FT
_EE
CS
FT
_EE
CLK
VB
US
VB
US
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C18
FT
VC
C33
VC
C33
US
B_U
AR
T_T
X[1
4]U
SB
_UA
RT
_RX
[14]
PM
_TC
K[4
]
XO
2_T
CK
[7,1
3,14
]
PM
_TD
I[4
]
PM
_TD
O[4
]
PM
_TM
S[4
]
XO
2_T
DI
[13,
14]
XO
2_T
DO
[13]
XO
2_T
MS
[7,1
3,14
]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Con
figur
atio
n U
SB
Por
t
C
614
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Con
figur
atio
n U
SB
Por
t
C
614
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Con
figur
atio
n U
SB
Por
t
C
614
Tue
sday
, Feb
ruar
y 15
, 201
1
US
B P
ort:
CP
LD C
onfig
urat
ion
& U
SB
<->
UA
RT
Com
mun
icat
ion
����������������������
�����������������������
The USB interface draws no power from
the USB bus. It is self-powered.
C14
44u
7C
144
4u7
1 2
C32
0_01
uFD
IC
320_
01uF
DI
C31
0.1u
Fcc
0402
C31
0.1u
Fcc
0402
1 2
C27
0.1u
FC
270.
1uF
1 2
R85
4_7K
DI
R85
4_7K
DI
R62
0D
IR
620
DI
C23
18pF
C23
18pF
12
R20
210
kR
202
10k
21
R55
4_7K
DI
R55
4_7K
DI
C48
0.1u
Fcc
0402
C48
0.1u
Fcc
0402
1 2
X3
12M
HZ
X3
12M
HZ
11
33
G1
2G
24
J6
Jum
per_
2way
DIJ6
Jum
per_
2way
DI
1 2 3
R71
0D
IR
710
DI
R88
4_7K
DI
R88
4_7K
DI
C82
0.1u
Fcc
0402
C82
0.1u
Fcc
0402
1 2
R80
68D
IR
8068
DI
R75
0D
IR
750
DI
C28
10u
C28
10u
1 2
R76
0D
IR
760
DI
C85
0.1u
Fcc
0402
C85
0.1u
Fcc
0402
1 2
C29
18pF
C29
18pF
12
R87
0D
IR
870
DI
R20
310
kR
203
10k
21
J5U
SB
_MIN
I_B
DI
J5U
SB
_MIN
I_B
DI
VC
C1
D-
2
D+
3
GN
D5
NC
4
CA
SE
7
CA
SE
8
CA
SE
9
CA
SE
6
MH
110
MH
211
R24
110
kR
241
10k
21
U5 S
TG
3693
QT
R
U5 S
TG
3693
QT
R
1S2
1
123S
EL
3
2S1
4D
25
2S2
6
GN
D11
3S1
7
D3
8
3S2
9
4SE
L10
4S1
12
D4
13
4S2
14
VC
C2
1S1
15
D1
16
R65
4_7K
DI
R65
4_7K
DI
R66
4_7K
DI
R66
4_7K
DI
R84
4_7K
DI
R84
4_7K
DI
R56
2k2
R56
2k2
21
R24
02k
2R
240
2k2
21
R39
0D
IR
390
DI
R24
910
kR
249
10k
21
R83
0D
IR
830
DI
R54
4_7K
DI
R54
4_7K
DI
R68
0D
IR
680
DI
R86
68D
IR
8668
DI
R89
4_7K
DI
R89
4_7K
DI
C14
50.
1uF
C14
50.
1uF
1 2
R79
100K
DI
R79
100K
DI
R38
0D
IR
380
DI
R20
54_
7KD
I
R20
54_
7KD
I
R70
0D
IR
700
DI
C10
90_
1uF
DI
C10
90_
1uF
DI
L3
600o
hm 5
00m
A
L3
600o
hm 5
00m
A12
R78
0D
IR
780
DI
FTD
I Hig
h-S
peed
US
B
F
T223
2H
FT
2232
HL
U20
FTD
I Hig
h-S
peed
US
B
F
T223
2H
FT
2232
HL
U20
VR
EG
IN50
VR
EG
OU
T49
DM
7
DP
8
RE
F6
RE
SE
T#
14
EE
CS
63
EE
CLK
62
EE
DA
TA
61
OS
CI
2
OS
CO
3
TE
ST
13
AD
BU
S0
16
AD
BU
S1
17
AD
BU
S2
18
AD
BU
S3
19
VPHY4
VPLL9
VCORE12
VCORE37
VCORE64
VCCIO20
VCCIO31
VCCIO42
VCCIO56
AGND 10
GND 1
GND 5
GND 11
GND 15
GND 25
GND 35
GND 47
GND 51PW
RE
N#
60
SU
SP
EN
D#
36
AD
BU
S4
21
AD
BU
S5
22
AD
BU
S6
23
AD
BU
S7
24
AC
BU
S0
26
AC
BU
S1
27
AC
BU
S2
28
AC
BU
S3
29
AC
BU
S4
30
AC
BU
S5
32
AC
BU
S6
33
AC
BU
S7
34
BD
BU
S0
38
BD
BU
S1
39
BD
BU
S2
40
BD
BU
S3
41
BD
BU
S4
43
BD
BU
S5
44
BD
BU
S6
45
BD
BU
S7
46
BC
BU
S0
48
BC
BU
S1
52
BC
BU
S2
53
BC
BU
S3
54
BC
BU
S4
55
BC
BU
S5
57
BC
BU
S6
58
BC
BU
S7
59
R82
0D
IR
820
DI
C12
60.
1uF
C12
60.
1uF
1 2
93LC
56-S
O8
U21
93LC
56-S
O8
U21
CS
1
CLK
2
DI
3
DO
4V
SS
5O
RG
6N
U7
VC
C8
C30
0.1u
Fcc
0402
C30
0.1u
Fcc
0402
1 2
R37
0D
IR
370
DI
R61
0D
IR
610
DI
C11
90.
1uF
C11
90.
1uF
1 2
C10
40.
1uF
C10
40.
1uF
1 2
R63
0D
IR
630
DI
R19
912
k1%
R19
912
k1% 2
1
R36
0D
IR
360
DI
16
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 14. Software, LED, Crystal, Header
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
XO
2_LE
D1
XO
2_LE
D2
XO
2_LE
D3
XO
2_LE
D0
SW
1S
W2 3
WS
3W
S
X_2
X_1
SW
0
XO
2_G
PIO
_0X
O2_
GP
IO_1
XO
2_G
PIO
_2X
O2_
GP
IO_3
XO
2_G
PIO
_4X
O2_
GP
IO_5
XO
2_G
PIO
_6X
O2_
GP
IO_7
PM
_MC
LKP
M_P
LDC
LK
HV
OU
T2
HV
OU
T1
VM
ON
9
VM
ON
10
PM
_OU
T14
SC
LS
DA
XO
2_G
PIO
_8X
O2_
GP
IO_9
XO
2_G
PIO
_10
XO
2_S
PI_
INX
O2_
SP
I_C
LK
XO
2_S
PI_
OU
T
XO
2_A
DC
_IN
XO
2_G
PIO
_11
VC
C33
VC
C33
VC
C33
VC
C33
VC
C33
VC
C12
VC
C18
XO
2_R
ES
ET
n[4
,14]
X_1
[14]
X_2
[14]
SW
0[1
4]
XO
2_LE
D0
[14]
XO
2_LE
D1
[14]
XO
2_LE
D2
[14]
XO
2_LE
D3
[14]
SW
1[1
4]S
W2
[14]
SW
3[1
4]
PM
_MC
LK[4
,14]
PM
_PLD
CLK
[4,1
4]
HV
OU
T2
[4]
HV
OU
T1
[4]
XO
2_G
PIO
_0[1
4]X
O2_
GP
IO_1
[14]
XO
2_G
PIO
_2[1
4]X
O2_
GP
IO_3
[14]
XO
2_G
PIO
_4[1
4]X
O2_
GP
IO_5
[14]
XO
2_G
PIO
_6[1
4]X
O2_
GP
IO_7
[14]
VM
ON
9[4
]
VM
ON
10[4
]
TM
S_H
DR
[6,1
3,14
]T
DI_
HD
R[1
3]T
DO
_HD
R[1
3]
TC
K_H
DR
[6,1
3,14
]
PM
_OU
T14
SC
L[4
,14]
SD
A[4
,14]
XO
2_G
PIO
_8[1
4]
XO
2_S
PI_
OU
T[8
,14]
XO
2_S
PI_
IN[8
,14]
XO
2_S
PI_
CLK
[8,1
4]
XO
2_G
PIO
_9[1
4]X
O2_
GP
IO_1
0[1
4]
XO
2_A
DC
_IN
[14]
XO
2_G
PIO
_11
[14]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
SW
, LE
D, C
ryst
al, H
eade
r
B
714
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
SW
, LE
D, C
ryst
al, H
eade
r
B
714
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
SW
, LE
D, C
ryst
al, H
eade
r
B
714
Tue
sday
, Feb
ruar
y 15
, 201
1
XO
2 LE
Ds
CT1934MS-ND
����������������������������������
Res
et P
ush-
But
ton
Sw
itch
4-D
IP S
witc
h
2x20
Hea
der
24 M
Hz
Cry
stal
25 M
Hz
OS
C
R12
810
K
DI
R12
810
K
DI
X2
HC
M49
24.
000M
AB
J-U
T
DI
X2
HC
M49
24.
000M
AB
J-U
T
DI
12
R12
410
KD
I
R12
410
KD
I
R1
10K
DI
R1
10K
DI
C11
12pF
DI
C11
12pF
DI
IO3
IO3
IO2
IO2
R12
610
KD
I
R12
610
KD
I
RN
1R
N2_
4_47
0D
I
RN
1R
N2_
4_47
0D
I
1234
8765
R12
510
KD
I
R12
510
KD
I
C63
0_1u
FD
IC63
0_1u
FD
I
S1
XO
2 G
loba
l Res
et
DIS
1
XO
2 G
loba
l Res
et
DI
14
23
D3
LED
DI
D3
LED
DI
R12
710
KD
I
R12
710
KD
I
R2
1M DI
R2
1M DI
C4
12pF
DI
C4
12pF
DI
D1
LED
DI
D1
LED
DI
J4 CO
N40
AD
NI
2x20
x100
mil
J4 CO
N40
AD
NI
2x20
x100
mil
12
34
56
78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
SW
1
SW
DIP
_4
DI
SW
1
SW
DIP
_4
DI
1 2 3 4
8 7 6 5D
2LE
D
DI
D2
LED
DI
CT
S-C
B3L
V-3
C-2
5MH
z
X1
CT
S-C
B3L
V-3
C-2
5MH
z
X1
EO
H1
GN
D2
VC
C4
OU
TP
UT
3
D4
LED
DI
D4
LED
DI
C8
0_1u
FD
IC8
0_1u
FD
I
R4
1KD
I
R4
1KD
I
R3
0 DN
I
R3
0 DN
I
17
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 15. Memory LPDDR, SD, SPI
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
XO
2_S
PI_
INX
O2_
SP
I_C
LK
XO
2_S
PI_
OU
T
XO
2_S
PI_
CS
0
LPD
DR
_DQ
0LP
DD
R_D
Q1
LPD
DR
_DQ
2LP
DD
R_D
Q3
LPD
DR
_DQ
4LP
DD
R_D
Q5
LPD
DR
_DQ
6LP
DD
R_D
Q7
LPD
DR
_LD
MLP
DD
R_L
DQ
S
LPD
DR
_A0
LPD
DR
_A1
LPD
DR
_A2
LPD
DR
_A3
LPD
DR
_A4
LPD
DR
_A5
LPD
DR
_A6
LPD
DR
_A7
LPD
DR
_A8
LPD
DR
_A9
LPD
DR
_A10
LPD
DR
_A11
LPD
DR
_A12
LPD
DR
_CK
LPD
DR
_CK
nLP
DD
R_C
KE
LPD
DR
_CS
n
LPD
DR
_WE
n
LPD
DR
_RA
Sn
LPD
DR
_CA
Sn
LPD
DR
_BA
0LP
DD
R_B
A1
uSD
_DA
T2
uSD
_DA
T1
uSD
_DA
T3
uSD
_CM
DuS
D_C
LKuS
D_D
AT
0
LPD
DR
_DQ
0LP
DD
R_D
Q1
LPD
DR
_DQ
2LP
DD
R_D
Q3
LPD
DR
_DQ
4LP
DD
R_D
Q5
LPD
DR
_DQ
6LP
DD
R_D
Q7
XO
2_S
PI_
INX
O2_
SP
I_C
LK
XO
2_S
PI_
OU
T
XO
2_S
PI_
CS
0
VC
C33
VC
C18
VC
C18
VC
C33
VC
C18
VC
C33
LPD
DR
_DQ
0[1
4]LP
DD
R_D
Q1
[14]
LPD
DR
_DQ
2[1
4]LP
DD
R_D
Q3
[14]
LPD
DR
_DQ
4[1
4]LP
DD
R_D
Q5
[14]
LPD
DR
_DQ
6[1
4]LP
DD
R_D
Q7
[14]
LPD
DR
_LD
M[1
4]LP
DD
R_L
DQ
S[1
4]
LPD
DR
_A0
[14]
LPD
DR
_A1
[14]
LPD
DR
_A2
[14]
LPD
DR
_A3
[14]
LPD
DR
_A4
[14]
LPD
DR
_A5
[14]
LPD
DR
_A6
[14]
LPD
DR
_A7
[14]
LPD
DR
_A8
[14]
LPD
DR
_A9
[14]
LPD
DR
_A10
[14]
LPD
DR
_A11
[14]
LPD
DR
_A12
[14]
LPD
DR
_CK
[14]
LPD
DR
_CK
n[1
4]LP
DD
R_C
KE
[14]
LPD
DR
_CS
n[1
4]
LPD
DR
_WE
n[1
4]
LPD
DR
_RA
Sn
[14]
LPD
DR
_CA
Sn
[14]
LPD
DR
_BA
0[1
4]LP
DD
R_B
A1
[14]
XO
2_S
PI_
OU
T[7
,14]
XO
2_S
PI_
IN[7
,14]
XO
2_S
PI_
CLK
[7,1
4]X
O2_
SP
I_C
S0
[14]
uSD
_DA
T1
[14]
uSD
_DA
T2
[14]
uSD
_DA
T3
[14] uS
D_C
MD
[14]
uSD
_CLK
[14]
uSD
_DA
T0
[14]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Mem
ory
LPD
DR
, SD
, SP
I
B
814
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Mem
ory
LPD
DR
, SD
, SP
I
B
814
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Mem
ory
LPD
DR
, SD
, SP
I
B
814
Tue
sday
, Feb
ruar
y 15
, 201
1
4MB
it S
PI
Mic
ro S
D C
ard
Soc
ket
LPD
DR
- 1
28M
b (4
Meg
x 4
ban
ks x
8 d
ata)
Low
er B
yte
Mas
k &
Str
obe
Em
pty
Ext
erna
l Pul
l-UP
res
isto
rs.
The
inte
rnal
XO
2 re
sist
ors
are
used
for
bias
.
Pac
kage
: UD
FN
Pac
kage
: SO
IC8
(WID
E)
RN
3R
N1_
8_10
KD
IR
N3
RN
1_8_
10K
DI
123456789 10 11 12 13 14 15 16 R15
810
KD
IR
158
10K
DI
C71
0_00
1uF
DI
C71
0_00
1uF
DI
C79
0_1u
FD
I
C79
0_1u
FD
I
RN
2R
N1_
8_10
KD
NI
RN
2R
N1_
8_10
KD
NI
123456789 10 11 12 13 14 15 16
U15
AT
25D
F04
1A-M
H-B
U15
AT
25D
F04
1A-M
H-B
S1
Q2
W3
Vss
4
Vcc
8
D5
C6
Res
et7
mic
roS
D S
ocke
t
U1
mic
roS
D S
ocke
t
U1
DA
T2
1
CD
/DA
T3
2
CM
D3
CLK
5
DA
T0
7
DA
T1
8
VD
D4
VS
S6
MT
46H
16M
16LF
BF
U6
MT
46H
16M
16LF
BF
U6
A0
J8
A1
J9
A10
J7
A11
H2
A12
H3
A2
K7
A3
K8
A4
K2
A5
K3
A6
J1
A7
J2
A8
J3
A9
H1
BA
0H
8
BA
1H
9
CA
S#
G8
CK
G2
CK
#G
3
CK
EG
1
CS
#H
7
RA
S#
G9
WE
#G
7
DQ
0A
8
DQ
1B
7
DQ
10D
3
DQ
11C
2
DQ
12C
3
DQ
13B
2
DQ
14B
3
DQ
15A
2
DQ
2B
8
DQ
3C
7
DQ
4C
8
DQ
5D
7
DQ
6D
8
DQ
7E
7
DQ
8E
3
DQ
9D
2
LDM
F8
LDQ
SE
8
UD
MF
2
UD
QS
E2
NC
D9
NC
F3
NC
F7
VDDA9
VDDF9
VDDK9
VDDQA7
VDDQB1
VDDQC9
VDDQD1
VDDQE9
VSS A1
VSS F1
VSS K1
VSSQ A3
VSSQ B9
VSSQ C1
VSSQ E1
C81
0_1u
FD
I
C81
0_1u
FD
I
R15
910
KD
IR
159
10K
DI
U14
AT
25D
F04
1A-S
H-B
U14
AT
25D
F04
1A-S
H-B
S1
Q2
W3
Vss
4
Vcc
8
D5
C6
Res
et7
C72
0_01
uFD
I
C72
0_01
uFD
I
C75
0_1u
FD
I
C75
0_1u
FD
I
C74
0_1u
FD
IC74
0_1u
FD
I
R18
60 D
I
R18
60 D
I
18
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 16. Video Input 15 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
TM
DS
_1_D
AT
A0_
NT
MD
S_1
_DA
TA
0_P
TM
DS
_1_D
AT
A2_
PT
MD
S_1
_DA
TA
2_N
TM
DS
_1_C
LK_N
TM
DS
_1_C
LK_N
TM
DS
_1_C
LK_P
TM
DS
_1_C
LK_P
TI_
PV
DD
_1
DV
DD
_1
OC
K_I
NV
_1D
FO
_1P
IXS
_1S
TA
GN
_1S
T_1
PD
N_1
PD
ON
_1
TI_
OV
DD
_1
NS
_LV
CC
_1
NS
_PV
CC
_1
DV
DD
_1
TI_
AV
DD
_1
DV
DD
_1
SC
DT
_1
DV
DD
_1
SC
DT
_1
TX
IN26
_1T
XIN
25_1
TX
IN24
_1T
XIN
23_1
TX
IN22
_1T
XIN
21_1
TX
IN20
_1T
XIN
19_1
TX
IN18
_1T
XIN
17_1
TX
IN16
_1T
XIN
15_1
TX
IN14
_1T
XIN
13_1
TX
IN12
_1T
XIN
11_1
TX
IN10
_1T
XIN
9_1
TX
IN8_
1T
XIN
7_1
TX
IN6_
1T
XIN
5_1
TX
IN4_
1T
XIN
3_1
TX
IN2_
1T
XIN
1_1
TX
IN0_
1
TX
CLK
IN_1
TX
CLK
IN_1
TX
IN18
_1
TX
IN15
_1T
XIN
14_1
PW
RD
WN
_1
OC
K_I
NV
_1
PD
N_1
PD
ON
_1
PW
RD
WN
_1
ST
_1
DF
O_1
PIX
S_1
ST
AG
N_1
DV
DD
_1
TX
IN7_
1C
TL1
_1
CT
L2_1
CT
L3_1
CT
L1_1
CT
L3_1
CT
L2_1
TI_
AV
DD
_1
DV
DD
_1
TI_
OV
DD
_1
TI_
PV
DD
_1
NS
_LV
CC
_1
NS
_PV
CC
_1
TX
_OU
T0_
N_1
TX
_OU
T0_
P_1
TX
_OU
T1_
N_1
TX
_OU
T1_
P_1
TX
_OU
T2_
N_1
TX
_OU
T2_
P_1
TX
_OU
T3_
N_1
TX
_OU
T3_
P_1
TX
_CLK
OU
T_N
_1T
X_C
LKO
UT
_P_1
TM
DS
_1_D
AT
A1_
NT
MD
S_1
_DA
TA
1_P
TM
DS
_1_D
AT
A2_
NT
MD
S_1
_DA
TA
2_P
TM
DS
_1_D
AT
A1_
PT
MD
S_1
_DA
TA
1_N
TM
DS
_1_D
AT
A0_
PT
MD
S_1
_DA
TA
0_N
TX
IN1_
1T
XIN
0_1
TX
IN17
_1
TX
IN11
_1
TX
IN5_
1
TX
IN16
_1
TX
IN10
_1
TX
IN27
_1
TX
IN3_
1T
XIN
2_1
TX
IN24
_1
TX
IN21
_1
TX
IN19
_1
TX
IN22
_1
TX
IN20
_1
TX
IN23
_1
TX
IN6_
1T
XIN
4_1
TX
IN13
_1
TX
IN9_
1
TX
IN26
_1
TX
IN12
_1
TX
IN8_
1
TX
IN25
_1
TX
IN27
_1
MD
R_T
X_O
UT
0_N
_1
MD
R_T
X_O
UT
0_P
_1
MD
R_T
X_O
UT
1_P
_1
MD
R_T
X_O
UT
1_N
_1
MD
R_T
X_O
UT
2_P
_1
MD
R_T
X_O
UT
2_N
_1
MD
R_T
X_C
LKO
UT
_P_1
MD
R_T
X_C
LKO
UT
_N_1
MD
R_T
X_O
UT
3_P
_1
MD
R_T
X_O
UT
3_N
_1
MD
R_T
X_O
UT
0_P
_1
MD
R_T
X_O
UT
1_P
_1M
DR
_TX
_OU
T1_
N_1
MD
R_T
X_O
UT
2_P
_1M
DR
_TX
_OU
T2_
N_1
MD
R_T
X_C
LKO
UT
_P_1
MD
R_T
X_C
LKO
UT
_N_1
MD
R_T
X_O
UT
0_N
_1
MD
R_T
X_O
UT
3_P
_1M
DR
_TX
_OU
T3_
N_1
TX
_OU
T0_
N_1
TX
_OU
T0_
P_1
TX
_OU
T1_
N_1
TX
_OU
T1_
P_1
TX
_OU
T2_
N_1
TX
_OU
T2_
P_1
TX
_OU
T3_
N_1
TX
_OU
T3_
P_1
TX
_CLK
OU
T_N
_1T
X_C
LKO
UT
_P_1
OC
K_I
NV
_1
NS
_ST
B_1
NS
_ST
B_1
DD
C_C
LKD
DC
_DA
TA
NS
_ST
B_1
Hot
_Plu
g_V
ideo
VC
C33
VC
C33
XO
2_IN
0_1_
N[1
4]X
O2_
IN0_
1_P
[14]
XO
2_IN
1_1_
N[1
4]X
O2_
IN1_
1_P
[14]
XO
2_IN
2_1_
N[1
4]X
O2_
IN2_
1_P
[14]
XO
2_IN
3_1_
N[1
4]X
O2_
IN3_
1_P
[14]
XO
2_C
LKIN
_1_N
[14]
XO
2_C
LKIN
_1_P
[14]
DD
C_C
LK
[10,
11]
DD
C_D
AT
A
[10,
11]
Hot
_Plu
g_V
ideo
[14]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
A
Vid
eo In
put 1
C
914
Tue
sday
, Feb
ruar
y 15
, 201
1
Mac
hXO
2 C
ontr
ol B
oard
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
A
Vid
eo In
put 1
C
914
Tue
sday
, Feb
ruar
y 15
, 201
1
Mac
hXO
2 C
ontr
ol B
oard
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
A
Vid
eo In
put 1
C
914
Tue
sday
, Feb
ruar
y 15
, 201
1
Mac
hXO
2 C
ontr
ol B
oard
LED will be ON
when link is
active.
(SCDT high)
(1) Gate
(2) Source
(3) Drain
SOT-23
3 21
R G B
DV
I Con
nect
orD
VI -
TM
DS
Dec
oder
LVD
S T
rans
lato
r
MD
R C
onne
ctor
Vid
eo In
put S
ourc
e 1
: D
VI o
r M
DR
for
dire
ct 7
:1LV
DS S
uppo
rtin
g C
ircui
ts
Res
isto
r M
UX
OD
CK
opp
osite
edg
e fr
om V
ideo
Sou
rce
2
TO
P P
acka
ge V
iew
Cha
nnel
Lin
k -
RX
IO5
IO5
DS
90C
R28
7U
19D
S90
CR
287
U19LV
DS
GN
D43
TxO
UT
3P37
TxO
UT
3N38
TxO
UT
2P41
TxO
UT
2N42
TxO
UT
1P45
TxO
UT
1N46
TxO
UT
0P47
TxO
UT
0N48
LVD
SV
CC
44
LVD
SG
ND
36
LVD
SG
ND
49
TxC
LKO
UT
P39
TxC
LKO
UT
N40
PW
RD
WN
32
TxI
N0
51T
xIN
152
TxI
N2
54T
xIN
355
TxI
N4
56T
xIN
52
TxI
N6
3T
xIN
74
TxI
N8
6T
xIN
97
TxI
N10
8T
xIN
1110
TxI
N12
11T
xIN
1312
TxI
N14
14T
xIN
1515
TxI
N16
16T
xIN
1718
TxI
N18
19T
xIN
1920
TxI
N20
22T
xIN
2123
TxI
N22
24T
xIN
2325
TxI
N24
27T
xIN
2528
TxI
N26
30T
xIN
2750
GN
D53
GN
D21
GN
D29
VC
C1
GN
D5
PLL
GN
D35
GN
D13
PLL
VC
C34
PLL
GN
D33
VC
C9
VC
C17
VC
C26
TxC
LKIN
31
R5
0D
NI
R5
0D
NI
Q1
BS
S13
8LT
1Q
1B
SS
138L
T1
C19
0_1u
FD
I
C19
0_1u
FD
I
R-even R-odd G-even G-odd B-even B-odd
R-in
G-in
B-in
Clk-in
TF
P40
1AU
2
R-even R-odd G-even G-odd B-even B-odd
R-in
G-in
B-in
Clk-in
TF
P40
1AU
2
AG
ND
79
Rx2
P80
Rx2
N81
AV
DD
82
AG
ND
83
AV
DD
84
Rx1
P85
Rx1
N86
AG
ND
87
AV
DD
88
AG
ND
89
Rx0
P90
Rx0
N91
AG
ND
92
RxC
P93
RxC
N94
AV
DD
95
EX
T_R
ES
96
DF
O1
RS
VD
(T
ie h
igh)
99
OC
K_I
NV
100
PD
N2
PD
ON
9
PIX
S4
ST
3S
TA
GN
7
QE
414
QE
515
QE
616
QE
717
QO
859
QO
960
QO
1061
QO
1162
QO
1263
QO
1364
QO
1465
QO
1566
QE
820
QE
921
QE
1022
QE
1123
QE
1224
QE
1325
QE
1426
QE
1527
QO
1669
QO
1770
QO
1871
QO
1972
QO
2073
QO
2174
QO
2275
QO
2377
QE
1630
QE
1731
QE
1832
QE
1933
QE
2034
QE
2135
QE
2236
QE
2337
QE
212
QE
313
QE
010
QE
111
QO
655
QO
150
QO
049
QO
352
QO
756
QO
453
QO
251
QO
554
CT
L342
CT
L241
CT
L140
DE
46
HS
YN
C48
OD
CK
44
VS
YN
C47
SC
DT
8
OV
DD
18
OV
DD
29
OV
DD
43
OV
DD
57
OV
DD
78
OG
ND
76
OG
ND
45
OG
ND
58
OG
ND
19
OG
ND
28
DG
ND
5
DG
ND
39
DV
DD
67
DG
ND
68
DV
DD
6
DV
DD
38
PV
DD
97
PG
ND
98
C15
0_01
uFD
I
C15
0_01
uFD
I
C12
5
0_00
1uF
DI
C12
5
0_00
1uF
DI
R21
00
DN
IR
210
0D
NI
C11
5
0_1u
FD
I
C11
5
0_1u
FD
I
R21
10K
DI
R21
10K
DI
R18
10K
DI
R18
10K
DI
J1 1022
6-1A
10P
E-N
D
J1 1022
6-1A
10P
E-N
D
DD
C_G
nd_1
1R
xIn3
+14
RxI
n3G
nd2
RxI
n3-
15D
DC
_+5V
DC
3U
SB
_+5V
DC
16R
xClk
In+
4R
xClk
InG
nd17
RxC
lkIn
-5
DD
C/S
CL
18U
SB
-6
US
B_S
hiel
d19
US
B+
7R
xIn2
+20
RxI
n2G
nd8
RxI
n2-
21D
DC
/SD
A9
RxI
n1+
22R
xIn1
Gnd
10R
xIn1
-23
US
B/D
DC
_Gnd
11S
ense
24R
xIn0
+12
RxI
n0G
nd25
RxI
n0-
13D
DC
_Gnd
_26
26
Mou
ntin
g_R
27
Mou
ntin
g_L
28
C13
5
0_00
1uF
DI
C13
5
0_00
1uF
DI
C11
3
0_00
1uF
DI
C11
3
0_00
1uF
DI
R21
50
DN
IR
215
0D
NI
R22
80
DI
R22
80
DI
R22
20
DI
R22
20
DI
R24
210
KD
IR
242
10K
DI
R24
80
DI
R24
80
DI
R21
10
DN
IR
211
0D
NI
C17
0_00
1uF
DI
C17
0_00
1uF
DI
D5
LED
_Gre
enD
5LE
D_G
reen
C11
2
0_1u
FD
I
C11
2
0_1u
FD
I
C13
7
0_00
1uF
DI
C13
7
0_00
1uF
DI
C14
0
10uF
DI
C14
0
10uF
DI
C21
10uF
DI
C21
10uF
DI
R21
60
DN
IR
216
0D
NI
R22
90
DI
R22
90
DI
R22
30
DI
R22
30
DI
R21
20
DN
IR
212
0D
NI
C20
10uF
DI
C20
10uF
DI
C12
1
10uF
DI
C12
1
10uF
DI
C14
0_00
1uF
DI
C14
0_00
1uF
DI
DVI-Integrated
J2D
VI_
I
DVI-Integrated
J2D
VI_
I
TM
DS
_Dat
a2+
2T
MD
S_D
ata2
-1
TM
DS
_Dat
a4-
4
TM
DS
_Dat
a4+
5
TM
DS
_Dat
a2/4
_Shi
eld
3
DD
C_C
lock
6
DD
C_D
ata
7
Ana
log_
Ver
tical
_Syn
c8
TM
DS
_Dat
a1-
9
TM
DS
_Dat
a1+
10
TM
DS
_Dat
a1/3
_Shi
eld
11
TM
DS
_Dat
a3-
12
TM
DS
_Dat
a3+
13
+5V
_Pow
er14
GN
D(f
or +
5V)
15
Hot
_Plu
g_D
etec
t16
TM
DS
_Dat
a0-
17
TM
DS
_Dat
a0+
18
TM
DS
_Dat
a0/5
_Shi
eld
19
TM
DS
_Dat
a5-
20
TM
DS
_Dat
a5+
21
TM
DS
_Clo
ck_S
hiel
d22
TM
DS
_Clo
ck+
23
TM
DS
_Clo
ck-
24
Ana
log_
Red
C1
Ana
log_
Gre
enC
2
Ana
log_
Blu
eC
3
Ana
log_
Hor
izon
tal_
Syn
cC
4
Ana
log_
Gro
und_
1C
5
Ana
log_
Gro
und_
2C
6
R27
470
DI
R27
470
DI
R21
30
DN
IR
213
0D
NI
R23
610
KD
IR
236
10K
DI
R21
80
DN
IR
218
0D
NI
C12
4
0_01
uFD
I
C12
4
0_01
uFD
I
R22
40
DI
R22
40
DI
R20
10K
DI
R20
10K
DI
R22
60
DI
R22
60
DI
C22
10uF
DI
C22
10uF
DI
R8
0D
NI
R8
0D
NI
C13
6
0_01
uFD
I
C13
6
0_01
uFD
I
R21
40
DN
IR
214
0D
NI
C5
0_01
uFD
I
C5
0_01
uFD
I
C12
2
10uF
DI
C12
2
10uF
DI
R23
710
KD
NI
R23
710
KD
NI
R22
10K
DN
IR
2210
KD
NI
R19
10K
DI
R19
10K
DI
C12
3
0_1u
FD
I
C12
3
0_1u
FD
I
R22
50
DI
R22
50
DI
R23
310
KD
IR
233
10K
DI
C18
0_01
uFD
I
C18
0_01
uFD
I
IO4
IO4
R22
70
DI
R22
70
DI
R21
70
DN
IR
217
0D
NI
R6
0D
IR
60
DI
C6
0_01
uFD
I
C6
0_01
uFD
IR
244
10K
DI
R24
410
KD
I
R23
00
DI
R23
00
DI
R20
90
DN
IR
209
0D
NI
R23
10
DI
R23
10
DI
C14
1
0_1u
FD
I
C14
1
0_1u
FD
I
C16
0_1u
FD
I
C16
0_1u
FD
I
R23
910
KD
IR
239
10K
DI
19
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 17. Video Input 25 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DV
DD
_2
TX
IN11
_2T
XIN
10_2
TX
IN9_
2T
XIN
8_2
TX
IN7_
2T
XIN
6_2
TX
IN5_
2T
XIN
4_2
TX
IN3_
2T
XIN
2_2
TX
IN1_
2T
XIN
0_2
TX
CLK
IN_2
TI_
AV
DD
_2
DV
DD
_2
PIX
S_2
DV
DD
_2
CT
L1_2
CT
L3_2
CT
L2_2
TI_
OV
DD
_2
ST
AG
N_2
TM
DS
_2_D
AT
A1_
PT
MD
S_2
_DA
TA
1_N
TX
IN7_
2C
TL1
_2
CT
L2_2
CT
L3_2
PW
RD
WN
_2
SC
DT
_2
TM
DS
_2_D
AT
A2_
P
TM
DS
_2_D
AT
A1_
N
TI_
PV
DD
_2
TM
DS
_2_D
AT
A1_
P
TM
DS
_2_D
AT
A0_
N
TI_
AV
DD
_2
TX
IN1_
2
ST
_2
TX
IN0_
2
TM
DS
_2_D
AT
A0_
P
NS
_LV
CC
_2
TM
DS
_2_D
AT
A0_
N
TX
IN17
_2T
MD
S_2
_DA
TA
2_N
TX
_OU
T0_
N_2
TX
IN11
_2
TX
_OU
T0_
P_2
PD
N_2
TX
IN3_
2T
XIN
2_2
TX
IN24
_2
TX
IN21
_2
TX
IN19
_2
TX
IN22
_2
TX
IN5_
2
TX
IN20
_2
TX
IN23
_2
TX
_OU
T1_
N_2
NS
_PV
CC
_2
TM
DS
_2_D
AT
A2_
NT
MD
S_2
_DA
TA
2_P
TM
DS
_2_C
LK_N
TX
_OU
T1_
P_2
TX
IN16
_2
TX
IN6_
2T
XIN
4_2
TX
IN13
_2
TX
IN9_
2
TX
IN26
_2
TX
IN12
_2
TX
IN8_
2
TX
IN25
_2
TX
_OU
T2_
N_2
TX
IN10
_2
TX
IN18
_2
TX
IN15
_2T
XIN
14_2
DV
DD
_2
TX
_OU
T2_
P_2
TX
IN27
_2
PD
ON
_2
TI_
PV
DD
_2
TX
CLK
IN_2
TM
DS
_2_C
LK_N
TM
DS
_2_D
AT
A0_
P
TX
_OU
T3_
N_2
TX
_OU
T3_
P_2
TX
IN27
_2
TX
_CLK
OU
T_N
_2
TM
DS
_2_C
LK_P
MD
R_T
X_O
UT
0_P
_2
MD
R_T
X_O
UT
1_P
_2M
DR
_TX
_OU
T1_
N_2
MD
R_T
X_O
UT
2_P
_2
DV
DD
_2
MD
R_T
X_O
UT
2_N
_2
MD
R_T
X_C
LKO
UT
_P_2
MD
R_T
X_C
LKO
UT
_N_2
MD
R_T
X_O
UT
0_N
_2
MD
R_T
X_O
UT
3_P
_2M
DR
_TX
_OU
T3_
N_2
MD
R_T
X_O
UT
0_P
_2
TX
IN26
_2
TX
_CLK
OU
T_P
_2
TX
_OU
T0_
N_2
TX
_OU
T0_
P_2
TX
_OU
T1_
N_2
TX
_OU
T1_
P_2
TX
_OU
T2_
N_2
TX
_OU
T2_
P_2
TX
_OU
T3_
N_2
TX
_OU
T3_
P_2
TX
_CLK
OU
T_N
_2T
X_C
LKO
UT
_P_2
TM
DS
_2_C
LK_P
MD
R_T
X_O
UT
1_P
_2
MD
R_T
X_O
UT
1_N
_2
DV
DD
_2
TX
IN25
_2T
XIN
24_2
MD
R_T
X_O
UT
2_P
_2
MD
R_T
X_O
UT
2_N
_2
MD
R_T
X_C
LKO
UT
_P_2
MD
R_T
X_C
LKO
UT
_N_2
OC
K_I
NV
_2
OC
K_I
NV
_2
MD
R_T
X_O
UT
0_N
_2
MD
R_T
X_O
UT
3_P
_2
MD
R_T
X_O
UT
3_N
_2
TX
IN23
_2T
XIN
22_2
TX
IN21
_2T
XIN
20_2
PW
RD
WN
_2
PD
N_2
SC
DT
_2
TI_
OV
DD
_2
PD
ON
_2
TX
IN19
_2T
XIN
18_2
TX
IN17
_2T
XIN
16_2
TX
IN15
_2T
XIN
14_2
TX
IN13
_2T
XIN
12_2
DF
O_2
ST
_2
DF
O_2
PIX
S_2
ST
AG
N_2
NS
_LV
CC
_2
NS
_PV
CC
_2
OC
K_I
NV
_2
NS
_ST
B_2
NS
_ST
B_2
NS
_ST
B_2
DD
C_C
LKD
DC
_DA
TA
Hot
_Plu
g_V
ideo
VC
C33
VC
C33
XO
2_IN
0_2_
N[1
4]X
O2_
IN0_
2_P
[14]
XO
2_IN
1_2_
N[1
4]X
O2_
IN1_
2_P
[14]
XO
2_IN
2_2_
N[1
4]X
O2_
IN2_
2_P
[14]
XO
2_IN
3_2_
N[1
4]X
O2_
IN3_
2_P
[14]
XO
2_C
LKIN
_2_N
[14]
XO
2_C
LKIN
_2_P
[14]
DD
C_D
AT
A
[9,1
1]
DD
C_C
LK
[9,1
1]
Hot
_Plu
g_V
ideo
[14]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Vid
eo In
put 2
C
1014
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Vid
eo In
put 2
C
1014
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Vid
eo In
put 2
C
1014
Tue
sday
, Feb
ruar
y 15
, 201
1
LED will be ON
when link is
active.
(SCDT high)
3 21
Res
isto
r M
UX
Vid
eo In
put S
ourc
e 2
: D
VI o
r M
DR
for
dire
ct 7
:1LV
DS
DV
I Con
nect
orD
VI -
TM
DS
Dec
oder
LVD
S T
rans
lato
r
MD
R C
onne
ctor
R G
Sup
port
ing
Circ
uits
B
(1) Gate
(2) Source
(3) Drain
SOT-23
TO
P P
acka
ge V
iew
Cha
nnel
Lin
k -
RX
Q8
BS
S13
8LT
1Q
8B
SS
138L
T1
R11
447
0D
IR
114
470
DI
R22
10
DI
R22
10
DI
R10
70
DI
R10
70
DI
C43
10uF
DI
C43
10uF
DI
DVI-Integrated
J10
DV
I_I
DVI-Integrated
J10
DV
I_I
TM
DS
_Dat
a2+
2T
MD
S_D
ata2
-1
TM
DS
_Dat
a4-
4
TM
DS
_Dat
a4+
5
TM
DS
_Dat
a2/4
_Shi
eld
3
DD
C_C
lock
6
DD
C_D
ata
7
Ana
log_
Ver
tical
_Syn
c8
TM
DS
_Dat
a1-
9
TM
DS
_Dat
a1+
10
TM
DS
_Dat
a1/3
_Shi
eld
11
TM
DS
_Dat
a3-
12
TM
DS
_Dat
a3+
13
+5V
_Pow
er14
GN
D(f
or +
5V)
15
Hot
_Plu
g_D
etec
t16
TM
DS
_Dat
a0-
17
TM
DS
_Dat
a0+
18
TM
DS
_Dat
a0/5
_Shi
eld
19
TM
DS
_Dat
a5-
20
TM
DS
_Dat
a5+
21
TM
DS
_Clo
ck_S
hiel
d22
TM
DS
_Clo
ck+
23
TM
DS
_Clo
ck-
24
Ana
log_
Red
C1
Ana
log_
Gre
enC
2
Ana
log_
Blu
eC
3
Ana
log_
Hor
izon
tal_
Syn
cC
4
Ana
log_
Gro
und_
1C
5
Ana
log_
Gro
und_
2C
6
R20
80
DN
IR
208
0D
NI
C45
0_1u
FD
I
C45
0_1u
FD
I
C34
0_01
uFD
I
C34
0_01
uFD
I
C36
0_01
uFD
I
C36
0_01
uFD
I
R11
20
DI
R11
20
DI
C13
8
0_01
uFD
I
C13
8
0_01
uFD
I
R10
110
KD
NI
R10
110
KD
NI
R96
0D
NI
R96
0D
NI
R97
10K
DI
R97
10K
DI
C40
0_01
uFD
I
C40
0_01
uFD
I
R10
80
DI
R10
80
DI
R93
0D
IR
930
DI
C11
4
0_00
1uF
DI
C11
4
0_00
1uF
DI
R10
60
DN
IR
106
0D
NI
C13
0
0_01
uFD
I
C13
0
0_01
uFD
I
C11
0
0_1u
FD
I
C11
0
0_1u
FD
I
R11
30
DN
IR
113
0D
NI
R11
910
KD
IR
119
10K
DI
R11
710
KD
IR
117
10K
DI
R11
00
DN
IR
110
0D
NI
R11
510
KD
IR
115
10K
DI
R10
50
DN
IR
105
0D
NI
R95
0D
IR
950
DI
R10
90
DN
IR
109
0D
NI
C42
0_1u
FD
I
C42
0_1u
FD
I
C11
6
0_1u
FD
I
C11
6
0_1u
FD
I
R12
010
KD
IR
120
10K
DI
C12
8
0_1u
FD
I
C12
8
0_1u
FD
I
R10
30
DI
R10
30
DI
C13
3
0_1u
FD
I
C13
3
0_1u
FD
I
C11
8
10uF
DI
C11
8
10uF
DI
C37
0_00
1uF
DI
C37
0_00
1uF
DI
R24
310
KD
NI
R24
310
KD
NI
R98
0D
NI
R98
0D
NI
R11
10
DI
R11
10
DI
R94
10K
DI
R94
10K
DI
R-even R-odd G-even G-odd B-even B-odd
R-in
G-in
B-in
Clk-in
TF
P40
1AU
9
R-even R-odd G-even G-odd B-even B-odd
R-in
G-in
B-in
Clk-in
TF
P40
1AU
9
AG
ND
79
Rx2
P80
Rx2
N81
AV
DD
82
AG
ND
83
AV
DD
84
Rx1
P85
Rx1
N86
AG
ND
87
AV
DD
88
AG
ND
89
Rx0
P90
Rx0
N91
AG
ND
92
RxC
P93
RxC
N94
AV
DD
95
EX
T_R
ES
96
DF
O1
RS
VD
(T
ie h
igh)
99
OC
K_I
NV
100
PD
N2
PD
ON
9
PIX
S4
ST
3S
TA
GN
7
QE
414
QE
515
QE
616
QE
717
QO
859
QO
960
QO
1061
QO
1162
QO
1263
QO
1364
QO
1465
QO
1566
QE
820
QE
921
QE
1022
QE
1123
QE
1224
QE
1325
QE
1426
QE
1527
QO
1669
QO
1770
QO
1871
QO
1972
QO
2073
QO
2174
QO
2275
QO
2377
QE
1630
QE
1731
QE
1832
QE
1933
QE
2034
QE
2135
QE
2236
QE
2337
QE
212
QE
313
QE
010
QE
111
QO
655
QO
150
QO
049
QO
352
QO
756
QO
453
QO
251
QO
554
CT
L342
CT
L241
CT
L140
DE
46
HS
YN
C48
OD
CK
44
VS
YN
C47
SC
DT
8
OV
DD
18
OV
DD
29
OV
DD
43
OV
DD
57
OV
DD
78
OG
ND
76
OG
ND
45
OG
ND
58
OG
ND
19
OG
ND
28
DG
ND
5
DG
ND
39
DV
DD
67
DG
ND
68
DV
DD
6
DV
DD
38
PV
DD
97
PG
ND
98
R11
610
KD
IR
116
10K
DI
C39
0_00
1uF
DI
C39
0_00
1uF
DI
J13
1022
6-1A
10P
E-N
D
J13
1022
6-1A
10P
E-N
D
DD
C_G
nd_1
1R
xIn3
+14
RxI
n3G
nd2
RxI
n3-
15D
DC
_+5V
DC
3U
SB
_+5V
DC
16R
xClk
In+
4R
xClk
InG
nd17
RxC
lkIn
-5
DD
C/S
CL
18U
SB
-6
US
B_S
hiel
d19
US
B+
7R
xIn2
+20
RxI
n2G
nd8
RxI
n2-
21D
DC
/SD
A9
RxI
n1+
22R
xIn1
Gnd
10R
xIn1
-23
US
B/D
DC
_Gnd
11S
ense
24R
xIn0
+12
RxI
n0G
nd25
RxI
n0-
13D
DC
_Gnd
_26
26
Mou
ntin
g_R
27
Mou
ntin
g_L
28
C13
1
0_00
1uF
DI
C13
1
0_00
1uF
DI
C13
2
0_00
1uF
DI
C13
2
0_00
1uF
DI
R99
0D
IR
990
DI
C13
9
0_00
1uF
DI
C13
9
0_00
1uF
DI
R10
00
DN
IR
100
0D
NI
C12
7
10uF
DI
C12
7
10uF
DI
C11
1
10uF
DI
C11
1
10uF
DI
C11
7
0_01
uFD
I
C11
7
0_01
uFD
I
R10
40
DN
IR
104
0D
NI
R22
00
DI
R22
00
DI
D11
LED
_Gre
enD
11LE
D_G
reen
DS
90C
R28
7U
18D
S90
CR
287
U18LV
DS
GN
D43
TxO
UT
3P37
TxO
UT
3N38
TxO
UT
2P41
TxO
UT
2N42
TxO
UT
1P45
TxO
UT
1N46
TxO
UT
0P47
TxO
UT
0N48
LVD
SV
CC
44
LVD
SG
ND
36
LVD
SG
ND
49
TxC
LKO
UT
P39
TxC
LKO
UT
N40
PW
RD
WN
32
TxI
N0
51T
xIN
152
TxI
N2
54T
xIN
355
TxI
N4
56T
xIN
52
TxI
N6
3T
xIN
74
TxI
N8
6T
xIN
97
TxI
N10
8T
xIN
1110
TxI
N12
11T
xIN
1312
TxI
N14
14T
xIN
1515
TxI
N16
16T
xIN
1718
TxI
N18
19T
xIN
1920
TxI
N20
22T
xIN
2123
TxI
N22
24T
xIN
2325
TxI
N24
27T
xIN
2528
TxI
N26
30T
xIN
2750
GN
D53
GN
D21
GN
D29
VC
C1
GN
D5
PLL
GN
D35
GN
D13
PLL
VC
C34
PLL
GN
D33
VC
C9
VC
C17
VC
C26
TxC
LKIN
31
R11
810
KD
IR
118
10K
DI
R20
70
DN
IR
207
0D
NI
C12
9
10uF
DI
C12
9
10uF
DI
IO17
IO17
R24
70
DI
R24
70
DI
R12
110
KD
IR
121
10K
DI
R10
20
DI
R10
20
DI
C12
0
10uF
DI
C12
0
10uF
DI
IO16
IO16
R92
0D
NI
R92
0D
NI
20
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 18. Video Output5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DV
DD
NS
_DV
DD
RX
OU
T7
CT
L2
PW
RD
WN
TI_
PV
DD
TI_
TV
DD
NS
_LV
CC
NS
_PV
CC
DV
DD
BS
EL
PD
N
ISE
L
DS
EL
MD
R_R
X_I
N2_
NM
DR
_RX
_IN
2_P
MD
R_R
X_I
N3_
NM
DR
_RX
_IN
3_P
MD
R_R
X_I
N0_
NM
DR
_RX
_IN
0_P
MD
R_R
X_C
LKO
UT
_NM
DR
_RX
_CLK
OU
T_P
MD
R_R
X_I
N1_
NM
DR
_RX
_IN
1_P
MD
R_R
X_I
N0_
N
MD
R_R
X_I
N0_
P
MD
R_R
X_I
N1_
N
MD
R_R
X_I
N1_
P
MD
R_R
X_I
N2_
N
MD
R_R
X_I
N2_
P
MD
R_R
X_I
N3_
N
MD
R_R
X_I
N3_
P
MD
R_R
X_C
LKO
UT
_N
MD
R_R
X_C
LKO
UT
_P
RX
_IN
0_N
RX
OU
T26
RX
OU
T24
RX
OU
T25
RX
_IN
0_P
RX
OU
T22
RX
OU
T20
RX
OU
T21
RX
OU
T23
RX
_IN
3_N
RX
_IN
1_N
RX
OU
T18
RX
OU
T16
RX
OU
T17
RX
OU
T14
RX
OU
T12
RX
OU
T13
RX
OU
T15
RX
OU
T19
RX
OU
T10
RX
OU
T8
RX
OU
T9
RX
OU
T6
RX
OU
T4
RX
OU
T5
RX
OU
T7
RX
OU
T11
RX
_IN
3_P
RX
OU
T3
RX
OU
T1
RX
OU
T2
RX
_IN
1_P
RX
CLK
OU
T
RX
_IN
2_N
RX
_IN
2_P
RX
_CLK
IN_N
RX
OU
T0
RX
_CLK
IN_P
NS
_LV
CC
NS
_PV
CC
PW
RD
WN
RX
OU
T27
NS
_DV
DD
DV
DD
TM
DS
_DA
TA
0_N
TI_
TV
DD
TM
DS
_CLK
_PT
MD
S_C
LK_N
RX
OU
T18
RX
OU
T14
RX
OU
T15
MS
EN
TI_
TV
DD
TM
DS
_DA
TA
2_P
ED
GE
ISE
L
BS
EL
DS
EL
PD
N
VR
EF
DK
EN
TM
DS
_DA
TA
2_N
TI_
PV
DD
TM
DS
_DA
TA
1_P
CT
L3
TM
DS
_DA
TA
1_N
TM
DS
_DA
TA
0_P
RX
OU
T25
RX
OU
T26
RX
OU
T8
RX
OU
T9
RX
OU
T12
RX
OU
T13
RX
OU
T4
RX
OU
T6
RX
OU
T23
RX
OU
T19
RX
OU
T20
RX
OU
T21
RX
OU
T22
RX
OU
T24
RX
OU
T2
RX
OU
T3
RX
OU
T27
RX
OU
T10
RX
OU
T5
RX
OU
T11
RX
OU
T16
RX
OU
T17
RX
OU
T0
RX
OU
T1
RX
CLK
OU
T
CT
L2C
TL1
DV
DD
MS
EN
VR
EF
DK
EN
ED
GE
CT
L1
CT
L3
TM
DS
_DA
TA
2_P
TM
DS
_DA
TA
2_N
TM
DS
_DA
TA
1_N
TM
DS
_DA
TA
1_P
TM
DS
_DA
TA
0_P
TM
DS
_DA
TA
0_N
TM
DS
_CLK
_PT
MD
S_C
LK_N
ED
GE
DD
C_C
LKD
DC
_DA
TA
RX
_IN
2_N
RX
_IN
2_P
RX
_IN
3_N
RX
_IN
3_P
RX
_IN
0_N
RX
_IN
0_P
RX
_CLK
IN_N
RX
_CLK
IN_P
RX
_IN
1_N
RX
_IN
1_P
VC
C33
VC
C33
VC
C5
DD
C_D
AT
A
[9,1
0]
DD
C_C
LK
[9,1
0]
Hot
_Plu
g_V
ideo
[14]
XO
2_O
UT
2_P
[14]
XO
2_O
UT
3_N
[14]
XO
2_O
UT
3_P
[14] X
O2_
CLK
OU
T_N
[14]
XO
2_C
LKO
UT
_P[1
4]
XO
2_O
UT
0_N
[14]
XO
2_O
UT
0_P
[14]
XO
2_O
UT
1_N
[14]
XO
2_O
UT
1_P
[14]
XO
2_O
UT
2_N
[14]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Vid
eo O
utpu
t
C
1114
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Vid
eo O
utpu
t
C
1114
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
Vid
eo O
utpu
t
C
1114
Tue
sday
, Feb
ruar
y 15
, 201
1
Vid
eo O
utpu
t : D
VI o
r M
DR
for
dire
ct 7
:1LV
DS
TM
DS
- D
VI D
ecod
erLV
DS
Tra
nsla
tor
MD
R C
onne
ctor
Sup
port
ing
Circ
uits
Res
isto
r D
e-M
UX
LED will be OFF when
a powered receiver is
attached to DVI.
(MSEN low)
3 21
TM
DS
- D
VI C
onne
ctor
(1) Gate
(2) Source
(3) Drain
SOT-23
TO
P P
acka
ge V
iew
Cha
nnel
Lin
k -
TX
021
RD
I0
21R
DI
R50
0D
IR
500
DI
0271
RD
NI
0271
RD
NI
C13
4
0_1u
FD
I
C13
4
0_1u
FD
I
C7
0_00
1uF
DI
C7
0_00
1uF
DI
C60
10uF
DI
C60
10uF
DI
R24
510
KD
NI
R24
510
KD
NI
R43
10K
DI
R43
10K
DI
R/HVSync
G/CTL1
B/CTL3:2
Clk Out
TF
P41
0
U3
R/HVSync
G/CTL1
B/CTL3:2
Clk Out
TF
P41
0
U3 ID
CK
P57
IDC
KN
56
DE
2
DS
EL/
SD
A14
ISE
L/R
ST
N13
PD
N10
N/C
49
DK
EN
35
RE
SE
RV
ED
(T
ie to
GN
D)
34
BS
EL/
SC
L15
TX
CN
21T
XC
P22
TV
DD
23
TX
0N24
TX
0P25
TG
ND
26
TX
1N27
TX
1P28
TV
DD
29
TX
2N30
TX
2P31
TG
ND
32
MS
EN
/PO
111
DA
TA
162
DA
TA
261
DA
TA
360
DA
TA
459
DA
TA
558
DA
TA
655
DA
TA
754
DA
TA
853
DA
TA
952
DA
TA
1051
DA
TA
1150
DA
TA
1247
DA
TA
1346
DA
TA
1445
DA
TA
1544
DA
TA
1643
DA
TA
1742
DA
TA
1841
DA
TA
1940
DA
TA
2039
DA
TA
2138
DA
TA
2237
DA
TA
2336
TG
ND
20
CT
L3/A
3/D
K3
6
CT
L2/A
2/D
K2
7
CT
L1/A
1/D
K1
8
VR
EF
3
HS
YN
C4
TF
AD
J19
VS
YN
C5
ED
GE
/HT
PLG
9D
GN
D16
DG
ND
48
DV
DD
33
DG
ND
64
DV
DD
1
DV
DD
12
PV
DD
18
PG
ND
17
DA
TA
063
C3
10uF
DI
C3
10uF
DI
R12
910
0S
M_R
_060
3
R12
910
0S
M_R
_060
3
C50
0_00
1uF
DI
C50
0_00
1uF
DI
R64
470
DI
R64
470
DI
R48
10K
DN
IR
4810
KD
NI
0471
RD
I0
471R
DI
0861
RD
NI
0861
RD
NI
051
RD
NI
051
RD
NI
C12
0_00
1uF
DI
C12
0_00
1uF
DI
R24
610
KD
NI
R24
610
KD
NI
0171
RD
I0
171R
DI
R7
10K
DI
R7
10K
DI
011
RD
NI
011
RD
NI
C25
0_01
uFD
I
C25
0_01
uFD
I
R31
510,
1%
SM
_R_0
603
R31
510,
1%
SM
_R_0
603
R12
310
KD
I
R12
310
KD
I
Q3
BS
S13
8LT
1Q
3B
SS
138L
T1
R44
10K
DI
R44
10K
DI
DS
90C
R28
8AU
10D
S90
CR
288A
U10
LVD
SG
ND
14
RxI
N3P
20R
xIN
3N19
RxI
N2P
16R
xIN
2N15
RxI
N1P
12R
xIN
1N11
RxI
N0P
10R
xIN
0N9
LVD
SV
CC
13
LVD
SG
ND
8
LVD
SG
ND
21
RxC
LKIN
P18
RxC
LKIN
N17
PW
RD
WN
25
RxO
UT
027
RxO
UT
129
RxO
UT
230
RxO
UT
332
RxO
UT
433
RxO
UT
534
RxO
UT
635
RxO
UT
737
RxO
UT
838
RxO
UT
939
RxO
UT
1041
RxO
UT
1142
RxO
UT
1243
RxO
UT
1345
RxO
UT
1446
RxO
UT
1547
RxO
UT
1649
RxO
UT
1750
RxO
UT
1851
RxO
UT
1953
RxO
UT
2054
RxO
UT
2155
RxO
UT
221
RxO
UT
232
RxO
UT
243
RxO
UT
255
RxO
UT
266
RxO
UT
277
GN
D52
GN
D36
GN
D44
VC
C31
GN
D4
PLL
GN
D24
GN
D28
PLL
VC
C23
PLL
GN
D22
VC
C40
VC
C48
VC
C56
RxC
LKO
UT
26
R51
0D
IR
510
DI
C9
10uF
DI
C9
10uF
DI
C62
10uF
DI
C62
10uF
DI
061
RD
NI
061
RD
NI
031
RD
I0
31R
DI
C49
10uF
DI
C49
10uF
DI
C61
0_1u
FD
I
C61
0_1u
FD
I
C2
0_01
uFD
I
C2
0_01
uFD
I
C59
0_1u
FD
I
C59
0_1u
FD
I
C24
0_01
uFD
I
C24
0_01
uFD
I
C52
0_01
uFD
I
C52
0_01
uFD
I
0071
RD
I0
071R
DI
071
RD
I0
71R
DI
DVI-Integrated
J3 DV
I_I
DVI-Integrated
J3 DV
I_I
TM
DS
_Dat
a2+
2T
MD
S_D
ata2
-1
TM
DS
_Dat
a4-
4
TM
DS
_Dat
a4+
5
TM
DS
_Dat
a2/4
_Shi
eld
3
DD
C_C
lock
6
DD
C_D
ata
7
Ana
log_
Ver
tical
_Syn
c8
TM
DS
_Dat
a1-
9
TM
DS
_Dat
a1+
10
TM
DS
_Dat
a1/3
_Shi
eld
11
TM
DS
_Dat
a3-
12
TM
DS
_Dat
a3+
13
+5V
_Pow
er14
GN
D(f
or +
5V)
15
Hot
_Plu
g_D
etec
t16
TM
DS
_Dat
a0-
17
TM
DS
_Dat
a0+
18
TM
DS
_Dat
a0/5
_Shi
eld
19
TM
DS
_Dat
a5-
20
TM
DS
_Dat
a5+
21
TM
DS
_Clo
ck_S
hiel
d22
TM
DS
_Clo
ck+
23
TM
DS
_Clo
ck-
24
Ana
log_
Red
C1
Ana
log_
Gre
enC
2
Ana
log_
Blu
eC
3
Ana
log_
Hor
izon
tal_
Syn
cC
4
Ana
log_
Gro
und_
1C
5
Ana
log_
Gro
und_
2C
6
R46
10K
DI
R46
10K
DI
052
RD
NI
052
RD
NI
C55
0_00
1uF
DI
C55
0_00
1uF
DI
R32
10K
DI
R32
10K
DI
R47
10K
DI
R47
10K
DI
R13
510
0S
M_R
_060
3
R13
510
0S
M_R
_060
3
C64
0_1u
FD
I
C64
0_1u
FD
I
C51
0_01
uFD
I
C51
0_01
uFD
I
032
RD
I0
32R
DI
R45
10K
DI
R45
10K
DI
0131
RD
I0
131R
DI
C26
0_00
1uF
DI
C26
0_00
1uF
DI
R13
010
0S
M_R
_060
3
R13
010
0S
M_R
_060
3
0371
RD
NI
0371
RD
NI
043
RD
I0
43R
DI
092
RD
NI
092
RD
NI
0761
RD
I0
761R
DI
C13
10uF
DI
C13
10uF
DI
C10
0_1u
FD
I
C10
0_1u
FD
I
R13
410
0S
M_R
_060
3
R13
410
0S
M_R
_060
3
041
RD
I0
41R
DI
IO13
IO13
C1
0_00
1uF
DI
C1
0_00
1uF
DI
C57
0_1u
FD
I
C57
0_1u
FD
I
D6
LED
_Gre
enD
6LE
D_G
reen
09
RD
I0
9R
DI
J810
226-
1A10
PE
-ND
J810
226-
1A10
PE
-ND
DD
C_G
nd_1
1
TxO
ut0-
14
TxO
ut0G
nd2
TxO
ut0+
15
Sen
se3
US
B/D
DC
_Gnd
16
TxO
ut1-
4
TxO
ut1G
nd17
TxO
ut1+
5
DD
C/S
DA
18
TxO
ut2-
6
TxO
ut2G
nd19
TxO
ut2+
7
US
B+
20
US
B_S
hiel
d8
US
B-
21
DD
C/S
CL
9
TxC
lkO
ut-
22
TxC
lkO
utG
nd10
TxC
lkO
ut+
23
US
B_+
5VD
C11
DD
C_+
5VD
C24
TxO
ut3-
12
TxO
ut3G
nd25
TxO
ut3+
13
DD
C_G
nd_2
626
Mou
ntin
g_R
27
Mou
ntin
g_L
28
R49
0D
IR
490
DI
R13
310
0S
M_R
_060
3
R13
310
0S
M_R
_060
3
IO10
IO10
C58
0_1u
FD
I
C58
0_1u
FD
I
001
RD
NI
001
RD
NI
R13
210
KD
IR
132
10K
DI
0961
RD
NI
0961
RD
NI
C56
0_01
uFD
I
C56
0_01
uFD
I
21
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 19. Audio In/Audio Out
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
AU
DIO
_SIG
AU
DIO
_OU
T
D2A
_OU
T
AU
DIO
_SIG
AU
DIO
_IN
AU
DIO
_SIG
VC
C33
VC
C5
VC
C33
VC
C33
AU
DIO
_OU
T[1
4]
AU
DIO
_IN
[14]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
AU
DIO
IN /
AU
DIO
OU
T
B
1214
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
AU
DIO
IN /
AU
DIO
OU
T
B
1214
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
AU
DIO
IN /
AU
DIO
OU
T
B
1214
Tue
sday
, Feb
ruar
y 15
, 201
1
PW
M A
nalo
g S
igna
l Out
put
Mic
roph
one
Aud
io A
mpl
ifier
Opt
iona
l Byp
ass
J12
PH
ON
EJA
CK
ST
ER
EO
J12
PH
ON
EJA
CK
ST
ER
EO
2 3 1
R14
72_
2KD
I
R14
72_
2KD
I
R15
1
10K
DIR
151
10K
DI
C68
0_1u
FD
NI
C68
0_1u
FD
NI
C70
10uF
DI
C70
10uF
DI
R14
610
0D
I
R14
610
0D
I
- +
U13
MC
P6L
71R
- +
U13
MC
P6L
71R
341
52
C47
0_1u
F
DI
C47
0_1u
F
DI
C73
10uF
DI
C73
10uF
DI
R16
210
00K
DI
R16
210
00K
DI
R13
610
0 DI
R13
610
0 DI
R14
910
00K
DI
R14
910
00K
DI
R14
533
0
DI
R14
533
0
DI
R15
010
KD
IR
150
10K
DI
R16
068
0KD
IR
160
680K
DI
R15
40
DI
R15
40
DI
C69
0_1u
FD
I
C69
0_1u
FD
I
C67
10uF
DI
C67
10uF
DI
CM
A-4
544P
F-W
U8
CM
A-4
544P
F-W
U8
TE
RM
11
TE
RM
22
R16
10 D
NI
R16
10 D
NI
Q4
2N23
69A
DI
Q4
2N23
69A
DI
3 1
2
22
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 20. MachXO2 Supplies, JTAG
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
XO
2_T
DO
XO
2_T
CK
XO
2_T
DI
XO
2_T
MS
XO
2_T
DO
XO
2_T
DO
_PIN
XO
2_T
CK
XO
2_T
MS
XO
2_T
DI
XO
2_T
DO
XO
2_T
MS
XO
2_T
CK
XO
2_T
DO
_PIN
VC
C_C
OR
E
VC
C33
VC
CIO
33
VC
CIO
33
VC
CIO
33V
CC
IO18
XO
2_T
DI
[6,1
4]
XO
2_T
DO
[6]
XO
2_T
CK
[6,7
,14]
XO
2_T
MS
[6,7
,14]
TD
I_H
DR
[7]
TD
O_H
DR
[7]
TM
S_H
DR
[6,7
,14]
TC
K_H
DR
[6,7
,14]
XO
2_T
DO
_PIN
[14]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
XO
2 S
uppl
ies,
JT
AG
B
1314
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
XO
2 S
uppl
ies,
JT
AG
B
1314
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
XO
2 S
uppl
ies,
JT
AG
B
1314
Tue
sday
, Feb
ruar
y 15
, 201
1
MachXO2 JTAG Port
MachXO2 Power
Expand JTAG Chain to Prototype Header:
NOT Populated
So
cket
(08
0SQ
132
U66
18A
) M
ou
nti
ng
Ho
les
TDI
TDO
TDI
TDO
MachXO2
R203
R202
R201
JTAG Header
J12
To Prototype Header
Expand JTAG Chain to Prototype Header:
R15
50
DN
IR
155
0D
NI
C94
0_1u
F
DN
I
C94
0_1u
F
DN
I
MH
16
M_H
OLE
1D
IIW
_MN
T0
MH
16
M_H
OLE
1D
IIW
_MN
T0
1
C96
0_1u
FD
I
C96
0_1u
FD
I
C88
0_1u
FD
NI
C88
0_1u
FD
NI
XO
2 JT
AG
HD
J7
XO
2 JT
AG
HD
J7
PO
WE
R1
TD
O2
TD
I3
NC
4
TR
ST
5
TM
S6
GN
D7
TC
K8
R15
60 D
NI
R15
60 D
NI
LCM
XO
2-12
00-C
SB
GA
132
U4E
LCM
XO
2-12
00-C
SB
GA
132
U4E G
ND
L2
GN
DG
2
GN
DD
2
GN
DB
11
GN
DD
13
GN
DH
13
VC
CP
14
VC
CA
1
NC
C7
GN
DA
5
VC
CA
14
GN
DL1
3
GN
DP
10
GN
DP
5
VC
CN
1
VC
CIO
0C
5
VC
CIO
0A
8
VC
CIO
0B
10
VC
CIO
1L1
2
VC
CIO
1H
14
VC
CIO
1D
14
VC
CIO
2N
11
VC
CIO
2M
6
VC
CIO
2P
1
VC
CIO
3L1
VC
CIO
3D
3
VC
CIO
3G
1
C98
0_1u
FD
I
C98
0_1u
FD
I
C92
0_1u
FD
I
C92
0_1u
FD
I
C10
0
0_1u
F DI
C10
0
0_1u
F DI
C84
0_1u
FD
I
C84
0_1u
FD
I
C77
0_1u
FD
I
C77
0_1u
FD
I
C10
3
0_1u
F DI
C10
3
0_1u
F DI
C90
0_1u
FD
I
C90
0_1u
FD
I
C80
0_1u
FD
I
C80
0_1u
FD
I
C76
0_1u
FD
I
C76
0_1u
FD
I
C10
10_
1uF
DN
I
C10
10_
1uF
DN
I
C87
0_1u
F
DN
I
C87
0_1u
F
DN
I
MH
13
M_H
OLE
1D
IIW
_MN
T0
MH
13
M_H
OLE
1D
IIW
_MN
T0
1
C93
0_1u
F
DN
I
C93
0_1u
F
DN
I
MH
2
M_H
OLE
1D
IIW
_MN
T0
MH
2
M_H
OLE
1D
IIW
_MN
T0
1
R15
70
DI
R15
70
DI
C10
20_
1uF
DN
I
C10
20_
1uF
DN
I
C95
0_1u
F
DN
I
C95
0_1u
F
DN
I
C97
0_1u
FD
I
C97
0_1u
FD
I
C86
0_1u
FD
NI
C86
0_1u
FD
NI
MH
1
M_H
OLE
1D
IIW
_MN
T0
MH
1
M_H
OLE
1D
IIW
_MN
T0
1
23
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Figure 21. MachXO2 Top, Bottom5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
uSD
_DA
T0
AU
DIO
_IN
PW
M_F
B_D
elta
_Sig
ma
LVD
S_C
OM
P_N
LVD
S_C
OM
P_P
_VR
EF
AD
C_I
N
XO
2_O
UT
0_N
XO
2_O
UT
0_P
XO
2_O
UT
1_N
XO
2_O
UT
1_P
XO
2_O
UT
2_N
XO
2_O
UT
2_P
XO
2_O
UT
3_N
XO
2_O
UT
3_P
XO
2_C
LKO
UT
_N
PW
M_F
B_D
elta
_Sig
ma
US
B_U
AR
T_T
XU
SB
_UA
RT
_RX
uSD
_CLK
LVD
S_C
OM
P_P
_VR
EF
XO
2_C
LKO
UT
_P
SC
LS
DA
SW
1S
W2
SW
0
SW
3
LPD
DR
_WE
n
LPD
DR
_CK
LPD
DR
_CK
n
LPD
DR
_CK
E_3
p3
LPD
DR
_CS
n
LPD
DR
_DQ
0
LPD
DR
_DQ
1
LPD
DR
_DQ
2
LPD
DR
_DQ
3
LPD
DR
_DQ
4LP
DD
R_D
Q5
LPD
DR
_DQ
6LP
DD
R_D
Q7
LPD
DR
_LD
M
LPD
DR
_LD
QS
LPD
DR
_RA
Sn
LPD
DR
_BA
0_3p
3
LPD
DR
_BA
1_3p
3
LPD
DR
_CA
Sn
LPD
DR
_RA
Sn
LPD
DR
_CA
Sn
LPD
DR
_CS
n
LPD
DR
_WE
n
LPD
DR
_BA
1_3p
3LP
DD
R_B
A0_
3p3
LPD
DR
_CK
E_3
p3
XO
2_T
CK
XO
2_T
DI
XO
2_T
MS
LPD
DR
_CK
E_1
p8LP
DD
R_B
A1_
1p8
LPD
DR
_BA
0_1p
8
LPD
DR
_A0
LPD
DR
_A1
LPD
DR
_A2
LPD
DR
_A3
LPD
DR
_A4
LPD
DR
_A5
LPD
DR
_A6
LPD
DR
_A7
LPD
DR
_A8
LPD
DR
_A10
LPD
DR
_A11
XO
UT
XIN
XO
2_R
ES
ET
n
LPD
DR
_A12
LPD
DR
_A9
LPD
DR
_LD
QS
MIS
O
MO
SI
XO
2_S
PI_
CLK
XO
2_S
PI_
CS
0P
M_S
MB
A_O
UT
3
PM
_OU
T13
PM
_OU
T11
PM
_OU
T12
LVD
S_C
OM
P_N
AU
DIO
_OU
T
PM
_PLD
CLK
PM
_MC
LK
XO
2_LE
D1
XO
2_LE
D2
XO
2_LE
D3
XO
2_LE
D0
uSD
_DA
T2
uSD
_DA
T3
uSD
_CM
D
uSD
_DA
T1
XO
2_T
DO
_PIN
SC
L
SD
A
XO
2_IN
3_2_
N
XO
2_IN
3_2_
P
XO
2_IN
0_2_
N
XO
2_IN
0_2_
P
XO
2_IN
1_2_
N
XO
2_IN
1_2_
P
XO
2_IN
2_2_
N
XO
2_IN
2_2_
P
XO
2_C
LKIN
_2_N
XO
2_C
LKIN
_2_P
XO
2_G
PIO
_0
XO
2_G
PIO
_1
XO
2_G
PIO
_2
XO
2_G
PIO
_3
XO
2_G
PIO
_4
XO
2_G
PIO
_5
XO
2_G
PIO
_6
XO
2_G
PIO
_7
XO
2_G
PIO
_8
XO
2_G
PIO
_9
XO
2_G
PIO
_10
XO
2_IO
_7
XO
2_IO
_8
XO
2_IO
_9
XO
2_IO
_0
XO
2_IO
_1
XO
2_IO
_2
XO
2_IO
_3
XO
2_IO
_4
XO
2_IO
_5
XO
2_IO
_6
XO
2_IO
_7
XO
2_IO
_8
XO
2_IO
_9
XO
2_IO
_0
XO
2_IO
_1
XO
2_IO
_2
XO
2_IO
_3
XO
2_IO
_4
XO
2_IO
_5
XO
2_IO
_6
XO
2_G
PIO
_11
XO
2_IO
_0X
O2_
IO_1
XO
2_IO
_4X
O2_
IO_5
XO
2_IO
_7X
O2_
IO_6
XO
2_IO
_8X
O2_
IO_9
XO
2_IN
3_1_
PX
O2_
IN3_
1_N
XO
2_IN
1_1_
NX
O2_
IN1_
1_P
XO
2_C
LKIN
_1_N
XO
2_C
LKIN
_1_P
XO
2_IN
2_1_
NX
O2_
IN2_
1_P
PM
_IN
1P
M_I
N2
XO
2_IO
_2X
O2_
IO_3
XO
2_IN
0_1_
NX
O2_
IN0_
1_P
VC
CIO
33
VC
C18
VC
C18
VC
C33
uSD
_DA
T0
[8]
XO
2_O
UT
2_P
[11]
XO
2_O
UT
3_N
[11]
XO
2_O
UT
3_P
[11] X
O2_
CLK
OU
T_N
[11]
XO
2_O
UT
0_N
[11]
XO
2_O
UT
0_P
[11]
XO
2_O
UT
1_N
[11]
XO
2_O
UT
1_P
[11]
XO
2_O
UT
2_N
[11]
US
B_U
AR
T_T
X[6
]U
SB
_UA
RT
_RX
[6] uS
D_C
LK[8
]
XO
2_C
LKO
UT
_P[1
1]
SC
L[4
,7]
SD
A[4
,7]
SW
1[7
]S
W2
[7]
SW
0[7
]
SW
3[7
]
LPD
DR
_WE
n[8
]
LPD
DR
_CK
[8]
LPD
DR
_CK
n[8
]
LPD
DR
_CS
n[8
]
LPD
DR
_DQ
0[8
]
LPD
DR
_DQ
1[8
]
LPD
DR
_DQ
2[8
]
LPD
DR
_DQ
3[8
]
LPD
DR
_DQ
4[8
]LP
DD
R_D
Q5
[8]
LPD
DR
_DQ
6[8
]LP
DD
R_D
Q7
[8]
LPD
DR
_LD
M[8
]
LPD
DR
_LD
QS
[8]
LPD
DR
_RA
Sn
[8]
LPD
DR
_CA
Sn
[8]
LPD
DR
_BA
0[8
]LP
DD
R_B
A1
[8]
LPD
DR
_CK
E[8
]
XO
2_T
DI
[6,1
3]
XO
2_T
CK
[6,7
,13]
XO
2_T
MS
[6,7
,13]
LPD
DR
_A0
[8]
LPD
DR
_A1
[8]
LPD
DR
_A2
[8]
LPD
DR
_A3
[8]
LPD
DR
_A4
[8]
LPD
DR
_A5
[8]
LPD
DR
_A6
[8]
LPD
DR
_A7
[8]
LPD
DR
_A8
[8]
LPD
DR
_A10
[8]
LPD
DR
_A11
[8]
X_1
[7]
XO
2_R
ES
ET
n[4
,7]
LPD
DR
_A12
[8]
LPD
DR
_A9
[8]
XO
2_S
PI_
OU
T[7
,8]
XO
2_S
PI_
IN[7
,8]
XO
2_S
PI_
CLK
[7,8
]
XO
2_S
PI_
CS
0[8
]P
M_S
MB
A_O
UT
3[4
]
PM
_OU
T13
[4]
PM
_OU
T11
[4]
PM
_OU
T12
[4]
X_2
[7]
AU
DIO
_OU
T[1
2]
PM
_PLD
CLK
[4,7
]
PM
_MC
LK[4
,7]
XO
2_LE
D0
[7]
XO
2_LE
D1
[7]
XO
2_LE
D2
[7]
XO
2_LE
D3
[7]
uSD
_DA
T2
[8]
uSD
_DA
T3
[8]
uSD
_CM
D[8
]
uSD
_DA
T1
[8]
XO
2_T
DO
_PIN
[13]
XO
2_IN
3_2_
N[1
0]
XO
2_IN
3_2_
P[1
0]
XO
2_IN
2_2_
P[1
0]XO
2_C
LKIN
_2_N
[10]
XO
2_IN
0_2_
N[1
0]
XO
2_IN
0_2_
P[1
0]
XO
2_IN
1_2_
N[1
0]
XO
2_IN
1_2_
P[1
0]
XO
2_IN
2_2_
N[1
0]XO
2_C
LKIN
_2_P
[10]
XO
2_G
PIO
_0[7
]
XO
2_G
PIO
_1[7
]
XO
2_G
PIO
_2[7
]
XO
2_G
PIO
_3[7
]
XO
2_G
PIO
_4[7
]
XO
2_G
PIO
_5[7
]
XO
2_G
PIO
_6[7
]
XO
2_G
PIO
_7[7
]
XO
2_G
PIO
_8[7
]
XO
2_G
PIO
_9[7
]
XO
2_G
PIO
_10
[7]
XO
2_G
PIO
_11
[7]
AU
DIO
_IN
XO
2_A
DC
_IN
XO
2_IN
3_1_
P[9
]X
O2_
IN3_
1_N
[9]
XO
2_IN
1_1_
N[9
]X
O2_
IN1_
1_P
[9] X
O2_
CLK
IN_1
_N[9
]X
O2_
CLK
IN_1
_P[9
]X
O2_
IN2_
1_N
[9]
XO
2_IN
2_1_
P[9
]
PM
_IN
1[4
]P
M_I
N2
[4]
XO
2_IN
0_1_
N[9
]X
O2_
IN0_
1_P
[9]
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
XO
2 T
OP
, B
OT
TO
M
C
1414
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
XO
2 T
OP
, B
OT
TO
M
C
1414
Tue
sday
, Feb
ruar
y 15
, 201
1
Titl
e
Siz
eD
ocum
ent N
umbe
rR
ev
Dat
e:S
heet
of
Mac
hXO
2 C
ontr
ol B
oard
A
XO
2 T
OP
, B
OT
TO
M
C
1414
Tue
sday
, Feb
ruar
y 15
, 201
1
Mac
hXO
2 B
ank
2
AD
C D
elta
-Sig
ma
Inte
rfac
e
Mac
hXO
2 B
ank
0M
achX
O2
Ban
k 1
Mac
hXO
2 B
ank
3
Inte
rfac
e be
twee
n LV
CM
OS
33 a
nd L
PD
DR
1.8V
LVC
MO
S33
Ope
n D
rain
LVC
MO
S33
Vol
tage
Dev
ider
I2C
Bus
Pul
l-up
Res
isto
rs
Res
isto
r M
ux b
etw
een
Pro
toty
pe H
eade
ran
d V
ideo
Cha
nnel
2 (
7:1L
VD
S)
075
RD
NI
075
RD
NI
R904_7K
DIR904_7K
DI
R16
60
DI
R16
60
DI
003
RD
NI
003
RD
NI
R69820
DIR69820
DI
J9
Jum
per_
2way
DI
J9
Jum
per_
2way
DI
1 2 3
R18
010
KD
IR
180
10K
DI
053
RD
NI
053
RD
NI
0141
RD
I0
141R
DI
R53
10K
DI
R53
10K
DI
Bank2
LCM
XO
2-12
00-C
SB
GA
132
U4C
Bank2
LCM
XO
2-12
00-C
SB
GA
132
U4C
PB
20D
/SI/S
ISP
I/IO
0P
13P
B20
C/S
NN
12
PB
20B
P12
PB
20A
M11
PB
18D
P11
PB
18C
M10
PB
18B
N10
PB
18A
M9
PB
15D
N9
PB
15C
P9
PB
15B
M8
PB
15A
P8
PB
11B
/PC
LKC
2_1
N8
PB
11A
/PC
LKT
2_1
M7
PB
11D
N7
PB
11C
P7
PB
9B/P
CLK
C2_
0P
6P
B9A
/PC
LKT
2_0
N6
PB
9DM
5P
B9C
N5
PB
6D/S
O/S
PIS
O/IO
1N
4P
B6C
/MC
LK/C
CLK
M4
PB
6BP
4P
B6A
N3
PB
4DM
3P
B4C
/CS
SP
INP
3
PB
4BN
2P
B4A
P2
R1821K
DIR1821K
DI
0931
RD
I0
931R
DI
R41
10K
DI
R41
10K
DI
0831
RD
I0
831R
DI
0351
RD
I0
351R
DI
R1831K
DIR1831K
DI
C78
3300
pFD
I
C78
3300
pFD
I
033
RD
NI
033
RD
NI
R1771K
DIR1771K
DI
R188820
DIR188820
DI
004
RD
NI
004
RD
NI
025
RD
NI
025
RD
NI
R1781K
DIR1781K
DI
062
RD
NI
062
RD
NI
0441
RD
I0
441R
DI
R914_7K
DIR914_7K
DI
Bank1
LCM
XO
2-12
00-C
SB
GA
132
U4B
Bank1
LCM
XO
2-12
00-C
SB
GA
132
U4B
PR
2AB
14
PR
2BC
13
PR
2CC
14
PR
2DD
12
PR
3AE
12
PR
3BE
14
PR
4AE
13
PR
4BF
12
PR
4CF
13
PR
4DF
14
PR
5AG
12
PR
5BG
14
PR
5C/P
CLK
T1_
0G
13
PR
5D/P
CLK
C1_
0H
12
PR
8AJ1
2
PR
8BJ1
4
PR
8CJ1
3
PR
8DK
12
PR
9AK
13
PR
9BK
14
PR
9CL1
4
PR
9DM
13
PR
10A
M12
PR
10B
M14
PR
10C
N13
PR
10D
N14
042
RD
NI
042
RD
NI
0241
RD
I0
241R
DI
R741K
DIR741K
DI
0041
RD
I0
041R
DI
R16
50
DI
R16
50
DI
Bank0
LCM
XO
2-12
00-C
SB
GA
132
U4A
Bank0
LCM
XO
2-12
00-C
SB
GA
132
U4A
PT
9AA
2
PT
9BB
3
PT
10A
A3
PT
10B
C4
TD
OA
4
TD
IB
4
PT
11A
B5
PT
11B
C6
TC
KB
6
TM
SA
6
PT
12A
/PC
LKT
0_1
A7
PT
12B
/PC
LKC
0_1
B7
PT
12C
/SC
L/IO
2/P
CLK
T0_
0C
8
PT
12D
/SD
A/IO
3/P
CLK
C0_
0B
8
PT
15A
C9
PT
15B
A9
PT
15C
B9
PT
15D
/PR
OG
RA
MN
C10
PT
16A
A10
PT
16B
C11
PT
16C
A11
PT
16D
B12
PT
17A
C12
PT
17B
A12
PT
17C
/INIT
NB
13
PT
17D
/DO
NE
A13
0731
RD
I0
731R
DI
R187820
DIR187820
DI
K0137
RD
IK01
37R
DI
0251
RD
I0
251R
DI
R1761K
DIR1761K
DI
IO12
IO12
R18
110
KD
IR
181
10K
DI
082
RD
NI
082
RD
NI
R1751K
DIR1751K
DI
0341
RD
I0
341R
DI
Bank3
LCM
XO
2-12
00-C
SB
GA
132
U4D
Bank3
LCM
XO
2-12
00-C
SB
GA
132
U4D
PL1
0DM
2P
L10C
M1
PL1
0BL3
PL9
B/P
CLK
C3_
0K
3P
L9A
/PC
LKT
3_0
K1
PL8
DK
2P
L8C
J3
PL8
BJ2
PL8
AJ1
PL5
DH
3P
L5C
H1
PL5
B/P
CLK
C3_
1H
2P
L5A
/PC
LKT
3_1
G3
PL4
DF
3P
L4C
F1
PL4
BF
2P
L4A
E3
PL3
DE
2P
L3C
E1
PL3
B/P
CLK
C3_
2D
1P
L3A
/PC
LKT
3_2
C2
PL2
D/L
_GP
LLC
_IN
C3
PL2
C/L
_GP
LLT
_IN
C1
PL2
B/L
_GP
LLC
_FB
B2
PL2
A/L
_GP
LLT
_FB
B1
024
RD
NI
024
RD
NI
24
MachXO2 Control Development KitLattice Semiconductor User’s Guide
Appendix B. Bill of MaterialsTable 1. Bill of Materials
Item Quantity Reference Value PCB Footprint Mfr Part Number Manufacturer
1 19 C1, C7, C12, C14, C17, C26, C37, C39, C50, C55, C71, C113, C114, C125, C131, C132, C135, C137, C139
0_001uF SM_C_0201
2 23 C2, C5, C6, C15, C18, C24, C25, C32, C34, C36, C38, C40, C41, C51, C52, C56, C72, C91, C117, C124, C130, C136, C138
0_01uF SM_C_0201
3 18 C3, C9, C13, C20, C21, C22, C43, C49, C60, C62, C111, C118, C120, C121, C122, C127, C129, C140
10uF SM_C_0603 C1608Y5V0J106Z TDK
4 2 C4, C11 12pF SM_C_0603
5 32 C8, C10, C16, C19, C42, C44, C45, C46, C47, C57, C58, C59, C61, C63, C64, C69, C74, C81, C89, C99, C105, C107, C109, C110, C112, C115, C116, C123, C128, C133, C134, C141
0_1uF SM_C_0603
6 2 C23, C29 18pF cc0402 C0402C180K3GACTU Kemet
7 3 C27, C30, C31 0.1uF cc0402 C0402C104K4RACTU Kemet
8 1 C28 10u cc0603 ECJ-1VB0J106M Panasonic
9 4 C33, C106, C142, C143 10uF SM_C_0805 JMK212BJ106KD-T TAIYO YUDEN
10 2 C35, C83 1uF SM_C_0805
11 7 C48, C82, C85, C104, C119, C126, C145 0.1uF cc0402 C0402C104K4RACTU Kemet
12 2 C53, C65 22uF SM_C_0805 LMK212BJ226MG-T TAIYO YUDEN
13 4 C54, C66, C70, C73 10uF SM_C_0805
14 1 C67 10uF SM_C_0603
15 1 C68 0_1uF SM_C_0603
16 13 C75, C76, C77, C79, C80, C84, C90, C92, C96, C97, C98, C100, C103
0_1uF SM_C_0201
17 1 C78 3300pF SM_C_0603
18 8 C86, C87, C88, C93, C94, C95, C101, C102
0_1uF SM_C_0201
19 1 C108 0_01uF SM_C_0201 EMK107BJ103K TAIYO YUDEN
20 1 C144 4u7 cc0603 ECJ-1VB0J475K
21 8 D1, D2, D3, D4, D7, D8, D9, D10 LED SM_D_0603 LTST-C190CKT LITE ON
22 2 D5, D6 LED_Green SM_D_0603 LTST-C190KGKT LITE ON
22a 1 D11 LED_Green SM_D_0603 LTST-C190KGKT LITE ON
23 1 D12 LED SM_D_0603 LTST-C190CKT LITE ON
24 15 IO2, IO3, IO4, IO5, IO9, IO10, IO11, IO12, IO13, IO14, IO16, IO17, IO18, IO19, IO20
T POINT R TP
25 3 IO7, IO8, IO15 T POINT R TP
26 2 J1, J8 10226-1A10PE-ND 10226-1A10PE-ND 10226-1A10PE 3M
26a 1 J13 10226-1A10PE-ND 10226-1A10PE-ND 10226-1A10PE 3M
27 2 J2, J3 DVI_I DVI_I 74320-1004 Molex
27a 1 J10 DVI_I DVI_I 74320-1004 Molex
28 1 J4 CON40A 2x20x100mil TSW-120-07-G-D Samtec
29 1 J5 USB_MINI_B TYPE_B UX60-MB-5ST Hirose
30 1 J6 Jumper_2way JP_2WY TSW-103-07-G-S Samtec Inc.
30 1 J9 Jumper_2way JP_2WY TSW-103-07-G-S Samtec Inc.
31 1 J7 XO2 JTAG HD XO2_JTAG_HD
32 1 J11 PWR_JACK PWR_CON RAPC712 Switchcraft
33 1 J12 PHONEJACK STEREO
SM MJ1-3510-SMT CUI
34 1 L3 600ohm 500mA FB0603 BLM18AG601SN1D Murata
35 4 MH1, MH2, MH13, MH16 M_HOLE1 IW_MNT0 SJ-5003 (BLACK)
36 4 Q1, Q3, Q6, Q8 BSS138LT1 SOT_23 BSS138LT3G ON Semi
37 2 Q2, Q5 2N7002E SM_SOT23 2N7002ET1G ON_Semi
25
MachXO2 Control Development KitLattice Semiconductor User’s Guide
38 1 Q4 2N2369A 2N2369A_SOT23 MMBT2369A Fairchild
39 1 Q7 ZDT758 SM_8_DUAL_PNP ZDT758 Diodes/Zetex
40 2 RN1, RN4 RN2_4_470 RN2_4_470_0603 TC164-JR-07470RL Yageo
41 1 RN2 RN1_8_10K RN1_8_10K_0603 MNR18E0APJ103 Rohm Semi
42 1 RN3 RN1_8_10K RN1_8_10K_0603 MNR18E0APJ103 Rohm Semi
43 45 R1, R7, R18, R19, R20, R21, R32, R41, R43, R44, R45, R46, R47, R53, R73, R81, R94, R97, R115, R116, R117, R118, R119, R120, R121, R123, R124, R125, R126, R127, R128, R132, R151, R158, R159, R163, R164, R180, R181, R200, R233, R236, R239, R242, R244
10K SM_R_0402
44 1 R2 1M SM_R_0603
45 48 R3, R5, R8, R10, R11, R15, R16, R24, R25, R26, R28, R29, R30, R33, R35, R40, R42, R52, R57, R92, R96, R98, R100, R104, R105, R106, R109, R110, R113, R155, R156, R161, R168, R169, R172, R173, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218
0 SM_R_0402
46 5 R4, R67, R195, R196, R232 1K SM_R_0603
47 68 R6, R9, R12, R13, R14, R17, R23, R34, R36, R37, R38, R39, R49, R50, R51, R61, R62, R70, R71, R75, R76, R78, R82, R83, R87, R93, R95, R99, R102, R103, R107, R108, R111, R112, R131, R137, R138, R139, R140, R141, R142, R143, R144, R152, R153, R154, R157, R165, R166, R167, R170, R171, R174, R186, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R247, R248
0 SM_R_0402
48 7 R22, R48, R101, R237, R243, R245, R246
10K SM_R_0402
49 4 R27, R64, R114, R122 470 SM_R_0603 ERJ-3EKF4700V Panasonic ECG
50 1 R31 510, 1% SM_R_0603
51 9 R54, R55, R65, R66, R84, R85, R88, R89, R205
4_7K SM_R_0603
52 1 R56 2k2 cr0402 TNPW04022K20BEED Vishay/Dale
53 1 R58 0 SM_R_0805
54 1 R59 1 SM_R_0805
55 2 R60, R219 220 SM_R_0603
56 2 R63, R68 0 SM_R_0603
57 3 R69, R187, R188 820 SM_R_0402
58 8 R74, R175, R176, R177, R178, R182, R183, R240
1K SM_R_0402
59 1 R79 100K SM_R_0603
60 2 R80, R86 68 SM_R_0402
61 2 R90, R91 4_7K SM_R_0402
62 5 R129, R130, R133, R134, R135 100 SM_R_0603
63 8 R136, R146, R184, R185, R191, R194, R201, R206
100 SM_R_0603
64 1 R145 330 SM_R_0603
65 1 R147 2_2K SM_R_0603
66 2 R148, R235 2 SM_R_0805
67 2 R149, R162 1000K SM_R_0603
68 1 R150 10K SM_R_0603
69 1 R160 680K SM_R_0603
70 2 R179, R198 200 SM_R_0603
71 4 R189, R190, R192, R193 3_92K SM_R_0603
72 2 R197, R204 2K SM_R_0603
Table 1. Bill of Materials (Continued)
Item Quantity Reference Value PCB Footprint Mfr Part Number Manufacturer
26
MachXO2 Control Development KitLattice Semiconductor User’s Guide
73 1 R199 12k cr0402 RC0402FR-0712KL Yageo
74 4 R202, R203, R241, R249 10k cr0402 RC0402FR-0710KL Yageo
75 0 R240 2k2 cr0402 RC0402FR-072K2L Yageo
76 1 SW1 SWDIP_4 SMD_8check 3-5435640-5 Tyco
77 1 SW2 SW DIP_2 SP_75 195-2MST CTS
78 1 S1 XO2 Global Reset SMT_SW EVQ-Q2K03W Panasonic
79 1 U1 microSD Socket SM_SD 460DE08C3 MULTICOMP
80 1 U2 TFP401A HTQFP_100 TFP401APZPG4 TI
80 1 U9 TFP401A HTQFP_100 TFP401APZPG4 TI
81 1 U3 TFP410 HTQFP_64 TFP410PAP TI
82 1 U4 LCMXO2-1200-CSBGA132
CSBGA132 LCMXO2-1200-CSBGA132
Lattice Semi
83 1 U5 STG3693QTR QFN STG3693QTR STMicro-electronics
84 1 U6 MT46H16M16LFBF SM/60VFBGA MT46H16M16LFBF Micron
85 1 U7 ispPAC-POWR1014A TQFP_48 ispPAC-POWR1014A-01TN48I
Lattice
86 1 U8 CMA-4544PF-W 2 Solder Pins (TH) CMA-4544PF-W CUI Inc
87 1 U10 DS90CR288A TSSOP_56 DS90CR288AMTD/NOPB
National Semi
88 1 U11 NCP1117ST33 SOT_223 NCP1117ST33T3G ONSemi
89 1 U12 NCP1117ST18 SOT_223 NCP1117ST18T3G ONSemi
90 1 U13 MCP6L71R SOT_23_5_MC MCP6L71RT-E/OT Microchip
91 1 U14 AT25DF041A-SH-B SOIC8 AT25DF041A-SH-B Atmel
92 1 U15 AT25DF041A-MH-B UDFN AT25DF041A-MH-B Atmel
93 1 U16 AD8604ARZ 14_SOIC AD8604ARZ Analog Devices
95 1 U17 Value MRA08A_M LP3879MR-1.2 National
96 1 U18 DS90CR287 TSSOP_56 DS90CR287MTD/NOPB TI
96 1 U19 DS90CR287 TSSOP_56 DS90CR287MTD/NOPB TI
97 1 U20 FT2232HL tqfp64_0p5_12p2x12p2_h1p6
FT2232HL FTDI
98 1 U21 93LC56-SO8 so8_50_244 93LC56T-I/SN Microchip
99 1 X1 CTS-CB3LV-3C-25MHz SMD 7.00mm x 5.00mm
CB3LV-3C-25M0000 CTS
100 1 X2 HCM49 24.000MABJ-UT SMD HCM49 24.000MABJ-UT Citizen Finetech
101 1 X3 12MHZ crystal_4p_3p2x2p5 7M-12.000MAAJ-T TXC CORP
102 1 XO2_Control_board_RevE_PCB 305-PD-11-XXX
Table 1. Bill of Materials (Continued)
Item Quantity Reference Value PCB Footprint Mfr Part Number Manufacturer