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Lucas-Lehmer Primality TesterPresentation 6March 1st 2006

Team: W-4

Nathan Stohs W4-1

Brian Johnson W4-2

Joe Hurley W4-3

Marques Johnson W4-4

Design Manager:

Prateek Goenka

Overall Objective: Modular Arithmetic unit with a creative use

This is my presentation, there are others like it but this one is mine

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Status• Finished

– Project Chosen– C simulations– Behavioral Verilog– Structural Verilog– Revised Floor Plan– Schematics– Pathmill Simulation of Top Level

• In Progress– Layout– Layout Simulations

• To Do– More Layout– Layout Simulations

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Transistor CountsModule Transistor Count

Count 2,664

Mod_Multiply 11,120

Mod_Add 1282

Partial Products 8,676

Counter 266

Dff_re (16) 896

Sub_16 704

Compare 36

Mod_P 1,280

Top Level Flops 896

FSM 700

Total 17,400

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Power ConsumptionModule Power

Count 53.81 uW

Mod_Multiply ?

Mod_Add 128.8 uW

Partial Products 368 uW

Counter 36.77 uW

Dff_re (16) 260 uW

Compare 149.2 pW

Mod_P 397.6 uW

Top Level Flops 39.6 uW

FSM ?

Top (100ns) 636.2 uW

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Sub_16

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X = 32 Y = 7 OUT = 25

Sub_16 Simulation

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Top SimulationS1 = (4 * 4 - 2) mod 127 = 14

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Top SimulationS2 = (14 * 14 - 2) mod 127 = 67

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Pathmill Results

• Shift_Left = .610 ns• Shift_Right = .610 ns• Mod_P = .610 ns• Mod_Add = 8.993 ns• Partial_Products = 5.135 ns• Longest Path from Top Simulation = 12.703ns

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Block Area Estimates (Updated)

Module Area (μm2)

Count 13,200

Mod_Mult 54,500

Sub_16 3,500

Compare 200

Mod_P 6,500

Top Level Flops 4,400

Mod_add 6,528

FSM 3,500

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Updated Floorplan

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What’s Next

• Continue Layout

• Simulate Layout

• Power Estimations for Layout

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Questions?