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Ericsson Review No. 1, 2007

Background

In September 2006, 3GPP nalized a studyitem called Evolved UTRA and UTRAN.The purpose of the study was to dene thelong-term evolution (LTE) of 3GPP accesstechnology in order to keep it competitiveeven in the distant future.1-2 A correspond-ing work item is scheduled for completion inthe second half of 2007. The 3GPP also con-ducted a parallel study, calledSystem Architec-ture Evolution (SAE), to outline the evolutionof the core network.3

Introduction to LTE

The 3GPP study item began by setting re-quirements and dening the scope of LTE.Examples of these requirements are improved instantaneous peak data rates

100Mbps in the downlink and 50Mbpsin the uplink;

reduced latency less than 100ms tran-sition from camped state to active state,less than 50ms transition from dormantstate to active state, and less than 5ms IPpacket latency in the user plane in an un-loaded system;

improved system performance two- to

four-fold increase in downlink bit ratescompared with a basic release 6 system(HSDPA), and two- to three-fold increasein uplink bit rates compared with a basicrelease 6 system (E-DCH); and

improved spectrum exibility abilityto deploy the system in many differentfrequency bands, in paired and unpairedspectrum, and with different spectrumallocations (for example, 1.25, 2.5, 5.0,10.0, 15.0 and 20MHz).4

The requirements were also used as inputfor determining the choice of air interface.To fulll the requirements put on spectrum

exibility and peak data rates, the studyitem concluded that the air interface in thedownlink should be based on orthogonalfrequency-division multiplexing (OFDM).This approach yields a frequency structure

that splits data over a large number of indi-vidual subcarriers with a spacing of 15kHz.

The smallest addressable unit, called a re-source block, is dened as 12 consecutivesubcarriers in frequency and 14 consecutivesymbols in time. The resource block is thus180kz in the frequency domain and equal to1ms (or one subframe) in the time domain.A subframe is also the minimum transmis-sion time interval (TTI). Short TTIs favorthe requirements put on latency in the userplane. The main method of fullling therequirements for peak data rates calls forthe transmission of parallel streams of datato a single terminal using multiple-inputmultiple-output (MIMO) techniques.

For the uplink, the study item recom-mended a single-carrier-based frequency-division multiple access (FDMA) solutionwith dynamic bandwidth. This approach

allows for a power-efcient implementationof the user terminal. The basic parameters,such as subframe and TTI, match those ofthe downlink.

Ericssons LTE test bed thus uses cyclic-prex OFDM (CP-OFDM) technology inthe downlink and localized or interleavedFDMA technology in the uplink. At pres-ent, in a single-stream conguration froma single mobile user to the radio base sta-tion (RBS), it supports transmission ratesof up to nearly 80Mbps in the downlink

and 25Mbps in the uplink. The additionof three more streams in the downlink willgive the test bed a peak data rate of nearly300Mbps.

The LTE test bed is currently limited toa single cell conguration without supportfor radio resource management, admissioncontrol, or handover between cells or sec-tors. Apart from basic radio and baseband(BB) capabilities, it implements mediumaccess control (MAC), radio link control(RLC), and a simple interface to applica-tions and services. It has also been preparedto work with advanced antenna solutions.

Therefore, the LTE access network can op-timize transmission according to a userslocation and needs that is, it can combineseveral streams, form beams (beamform-

The Third Generation Partnership Project (3GPP) is specifying the long-

term evolution of third-generation cellular systems to meet demands for

higher user bit rates. Ericsson has thus developed a test bed to evaluate

new access technologies and to investigate the suitability of new imple-

mentation technologies for future radio-access products.

The authors explain the access concept and anticipated requirements

for LTE and describe the test-bed system, architecture, subsystems, and

technology.

LTE test bed

Bernt Johansson and Tomas Sundin

TERMS AND ABBREVIATIONS

3GPP Third Generation Partnership

Project AMC Advanced mezzanine card ATCA Advanced TCA

ATL Application transport layer AUM Auxiliary unit moduleBB Baseband

CBU Cello basic unitCP-OFDM Cyclic-prex orthogonal

frequency-division multiplexingCPP Cello processor platformDPD Digital pre-distortion

DSP Digital signal processoreNB Evolved Node-BFDMA Frequency-division multiple accessFFT Fast Fourier TransformFTP File transfer protocol

FU Filter unitGPS Global positioning systemI2C Intelligent interface controllerIFFT Inverse FFT

IO Input-outputIP Internet protocolL1, L2 Layer-1, layer-2LTE Long-term evolution of

third-generation cellular systemsLTU Local timing unit

MAC Media access control

MCPA Multicarr ier power amplierMIMO Multiple input, multiple outputMP Main processor

MTU Main timing unitOAM Operation, administration and

maintenancePA Power amplierPEC Processor element clusterRAS Radio and antenna subsystemRBS Radio base station

RF Radio frequencyRLC Radio link controllerRUIF Radio unit interfaceRX ReceiverRXIF Receiver interface

RXRF1 Receiver RF1RXRF2 Receiver RF2SIMO Single input, multiple outputSISO Single input, single outputTCA Telecom computing architecture

TCP Transport control protocolTOR Transmit observation receiverTRX TransceiverTX TransmitterUE User equipment

VoIP Voice over IP

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ing) for longer range, or employ other com-binations of transmission.

The LTE test bed

Ericsson designed the LTE test bed aroundcommercially available technology to pro-

vide a exible, high-performance platformthat can serve as the basis for the develop-

ment of layer-1, layer-2, and in time, layer-3(L1, L2, L3) software functionality. The useof serial RapidIO technology, in particular,helps ensure platform exibility.

The platform is based on advancedtelecom computing architecture (ATCA)and advanced mezzanine card (AMC) pro-

cessing boards. Together, these form a pro-cessor cluster. The test bed connects to an

application server and client via TCP/IPover Ethernet.

LTE test bed structure

The LTE test bed is composed of an applica-tion server, radio base station, user equip-ment (UE), and host (Figure 1). From ahardware perspective, the base station anduser equipment are more or less identical ex-cept that the antenna system in the UE haslower radio frequency (RF) output power.

A host processor, which handles the

loading of software, debugging, and so on,is connected to both the RBS and UE. Aserver, which is connected to the RBS, anda client, which is connected to the UE, fa-cilitate simultaneous applications, such asle transfer, VoIP, and streaming. In addi-tion, the base station and UE have a highlystable timing and frequency reference thatcan be synchronized by means of GPS. Thebase station and UE are composed of an antenna subsystem that hosts power

ampliers, lters and antennas; an ATCA subsystem that hosts L1 and

L2 processing, timing and calibration, a

monitor, and the main processor (MP);and

a radio subsystem that hosts up to fourtransceiver (TRX) units and a congu-rable 4x20W power amplier (PA) mod-ule. The RBS may even support oneadditional radio subsystem (four trans-ceiver units and congurable 4x20W PAmodule).

Evolved node-B and UEarchitecture

Figure 2 shows the layered architecture ofthe LTE test bed. The ATCA (Ensamblesystem) platform provides serial RapidIOand Gigabit Ethernet; and from a referencesource, it distributes timing between vari-ous processing elements, such as CPUs andDSP AMCs.

The application transport layer providesuniform communication between proces-sor elements including the radio transceiv-er. Software applications, for instance, useit to communicate with one another.

The CBU generates a timing reference sig-nal that radio unit interface (RUIF) boards

distribute to the ATCA and transceiver. L1and L2 signal processing is performed ontop of the application transport layer.

Figure 3 shows an overview of the LTEnode-B and UE architecture.

Figure 1

Hardware architecture of the node-B and user equipment (UE).

Figure 2

Overview of the layered LTE test bed architecture.

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Ericsson Review No. 1, 2007 11

System architecture

Figure 4 shows the hardware architecture ofthe LTE test bed, which is composed of fourmain building blocks: Cello processor platform (CPP); processor element cluster (PEC); radio and antenna subsystem (RAS);

and mechanical structure.Apart from some radio parts, the platformis completely programmable. It is thus veryexible in terms of adding or changing func-

tionality. For instance, depending on equip-ment and cabling, the hardware architecturecan support the following congurations: 1xSISO/SIMO (single input, single out-

put/single input, multiple output); 2xMIMO (multiple input, multiple out-

put); or 4xMIMO.

CPP

CPP includes standard product boards,such as CBU and RUIF. Looking ahead, itmight also host special-purpose processorand Gigabit Ethernet interface boards. At

present, CPP is solely used for distribut-ing timing signals provided by CBU andRUIF.

The CBU selects either an internal CBUreference source or an optional externalfrequency reference source, such as a GPSdevice or a stable, free-running oscillator.

PEC

The processing element cluster (PEC) plat-form, which implements L1 and L2 func-tionality, is composed of a digital signalprocessor cluster, a main timing unit, and

general-purpose processors. It has been builtusing ATCA technology to permit scalingand exibility. The ATCA subrack containsmadatory connections made up of GiganetEthernet and intelligent interface control-lers (I2C). In addition, serial RapidIO withfour lanes, running at 3.125GHz per lane, isused as a fat pipe. It also holds several car-rier boards, each of which has four slots forAMCs. the AMCs are interconnected viaRapidIO and Gigabit Ethernet switch fab-rics and an I2C hub. The AMC slots maybe equipped with general-purpose processorAMCs, DSP AMCs, and interface AMCs.

The PEC platform uses Gigabit Ethernetand the I2C system-management bus forOAM, software loading, and tracing anddebugging purposes; the serial RapidIO isused as an interconnect for application data.

Figure 3

Overview of the S3G node-B and UE architecture.

Figure 4

Hardware architecture of the LTE test bed.

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The development and host system connectto the ATCA subrack via Gigabit Ethernet.The radio subsystem connects to the PECplatform by means of a cable to an AMCwith external interface. One AMC interfaceis required for each transceiver connectedto the PEC.

The clock reference subrack, which con-sists of CBU and RUIF boards from stan-dard RBS products, is connected to a maintiming unit (MTU) allocated to an AMCin the ATCA subsystem. the MTU distrib-utes clock and sync reference signals in theATCA backplane and to the radio subrack.

Radio and antenna subsystem

The radio subsystem is composed of a

transceiver, power amplier, lter, and op-tional calibration unit. One radio tran-sciever, which supports two transmitter(TX) and receiver (RX) chains, can sup-port 2xMIMO per transceiver board. Thepower amplier, which delivers up to 80Wover 20MHz of operational bandwidth,

can support SISO/SIMO, 2xMIMO or4xMIMO congurations.

Management subsystem

The test bed employs a host processor with agraphical user interface (GUI) for control ofsoftware loading, system setup, debugging,and logging of data. All communicationwith the test bed is performed through theGUI. The GUI may also display a variety of

graphs. The host processor connects to thetest bed via Gigabit Ethernet.

Application transport layer

The application transport layer constitutesan interface between the application layerand RapidIO logic layer. The application lay-er handles data message units; the RapidIOlogic layer handles RapidIO packets. Themain task of the application transport layer isto reassemble packets into message units andto segment message units into packets. The

ATL implementation differs from proces-sor element to processor element. The mainfunctions of the application transport layerare message segmentation and reassembly,destination decoding, buffering, and inter-rupt handling.

Radio implementation

Figure 5 shows a block diagram of the trans-ceiver and how it is connected to the poweramplier and lters.

The radio unit schematic shows units fortransmitter up-conversion, receiver down-conversion, digital baseband process-

ing, a digital signal interface, and control.Transmitter amplication is implementedthrough an external amplier with a built-in linearization function. At present, lin-earization is carried out using feed-forwardtechniques and by subtracting the distortionsignal. This robust technique gives excellentRF performance. A transmit observation re-ceiver (TOR) is used for correcting imbal-ance in the transmitter analog mixer. Theradio unit also includes receiver chains fortwo-way diversity.

The baseband radio DSP unit contains

clipping and ltering functions. In addi-tion, it has been prepared for digital pre-distortion (DPD) as a means of linearizingfuture, more power-efcient ampliers.In this event, the TOR functionality canalso be used for computing a proper pre-distortion signal. The local timing unit(LTU) functional block distributes a com-mon reference clock in the radio unit for lo-cal oscillator synthesizers, such as TX, TOR,RXRF1, RXRF2 and RXIF.

The main components of the transceiverare the auxiliary unit module (AUM), l-ter unit (FU), transmit observation re-

ceiver (TOR), local timing unit (LTU), andmulticarrier power amplier (MCPA).

Baseband implementation

Figure 6 shows the L1 and L2 implementa-

Figure 5

Block diagram of the transciever.

Figure 6

L1 and L2 implementation for the uplink.

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Ericsson Review No. 1, 2007 13

tion for the uplink. Figure 7 shows the L1 andL2 implementation for the downlink. Theseimplementations are realized in softwarerunning on DSPs and general-purpose pro-cessors. The functionality, which makes useof the PEC platform and the ATL and serialRapidIO for interconnection between pro-cessors, is mapped onto the PEC platform atcompile time.

The exible mapping of functionality toprocessors makes it easy to scale the systemto support more antenna branches for real-

izing 2xMIMO or 4xMIMO, or for addingsupport for more users or for higher bit rates.More DSP or general-purpose resources canbe added by inserting more AMCs into theATCA subrack.

System start

At startup, the system executes the OAMapplication, which communicates viaRapidIO maintenance transfers with everydevice in the system, including endpoints,switches and bridges.

The main processor application usesthe ATL message format to communicate

through control channels with other func-tional units.

After hardware initialization and afterOAM software and main processor applica-tion software have been loaded, the OAMapplication sets up the RapidIO transport layer; and loads and starts other applications for

example, it loads applications in the DSPplatform, radio link controller (RLC), me-dia access control (MAC), and transceiver,and starts the main processor application.

Once the system is set up, the main processor

application confgures the transceiver and startsthe RLC, MAC, and baseband applications.

Software-dened functionality is allo-cated to processors at compile time. Onceinitialization is complete, the RBS beginstransmitting synchronization pilot signalsand the UE begins scanning for the synchro-nization channel.

Integration

To demonstrate LTE, Ericsson has deployed asmall radio access network with one evolvednode-B that handles one cell. When onetransmit antenna is used, the test bed sup-

ports up to 80Mbps in the downlink. Whenfour transmit antennas are used it supportsup to 300Mbps in the downlink and can beused for concurrent FTP, VoIP and stream-ing data applications.

LTE Evaluation

Ericsson will use the test bed to demonstratethe LTE concept, and to analyze performance

and algorithms. The analysis will be basedon measurements of radio channels and theradio link performance of various congura-tions.

Benets

The architecture of the LTE test bed is veryexible, making it easy to allocate and updatefunctionality for a variety of congurations.It is also scalable, which translates into sup-port for a wide variety of congurations withdifferent hardware capability and capacity

requirements. The test-bed architecture alsoeasily supports logging and the storage ofdata for line evaluation.

Conclusion

Ericsson has designed and built a test bed todemonstrate the LTE concept, and to analyzeperformance and algorithms. The analy-sis will be based on measurements of radiochannels and the radio link performance ofvarious congurations.

The LTE test bed is composed of an appli-cation server, radio base station, user equip-

ment, and host. From a hardware perspec-tive, the base station and user equipment aremore or less identical.

The hardware architecture of the LTEtest bed is composed of four main build-

ing blocks: CPP, processor element cluster,radio and antenna subsystem, and mechani-cal structure. Apart from some radio parts,the platform is completely programmable.

The air interface in the downlink is basedon OFDM, which yields a frequency struc-ture that splits data over a large number ofindividual subcarriers. The main methodof fullling the requirements for peak datarates calls for the transmission of parallelstreams of data to a single terminal usingMIMO techniques.

The uplink uses a single-carrier-basedFDMA solution with dynamic bandwidth.This approach allows for a power-efcientimplementation of the user terminal.

REFERENCES AND TRADEMARKS

TR 25.814, Physical layer aspect forevolved UTRATR 25.813, Evolved UniversalTerrestrial Radio Access (E-UTRA) andEvolved Universal Terrestrial Radio Access

Network (E-UTRAN); Radio interfaceprotocol aspectsTR 23.882, 3GPP System ArchitectureEvolution (SAE): Report on TechnicalOptions and Conclusions

TR 25.13, Requirements for EvolvedUTRA (E-UTRA) and Evolved UTRAN(E-UTRAN)

RapidIO is a registered trademark of theRapidIO Trade Association

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Figure 7

L1 and L2 implementation for the downlink.

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