ltc6416 - 2 ghz low noise differential 16-bit adc...

LTC6416

16416f

The LTC®6416 is a differential unity gain buffer designed to drive 16-bit ADCs with extremely low output noise and excellent linearity beyond 300MHz. Differential input impedance is 12kΩ, allowing 1:4 and 1:8 transformers to be used at the input to achieve additional system gain.

With no external biasing or gain setting components and a fl ow-through pinout, the LTC6416 is very easy to use. It can be DC-coupled and has a common mode output offset of –40mV. If the input signals are AC-coupled, the LTC6416 input pins are internally biased to provide an output common mode voltage that is set by the voltage on the VCM pin.

In addition the LTC6416 has high speed, fast recovery clamping circuitry to limit output signal swing. Both the high and low clamp voltages are internally biased to allow maximum output swing but are also user programmable via the CLLO and CLHI pins.

Supply current is nominally 42mA and the LTC6416 oper-ates on supply voltages ranging from 2.7V to 3.9V.

The LTC6416 is packaged in a 10-lead 3mm × 2mm DFN package. Pinout is optimized for placement directly adjacent to Linear’s high speed 12-, 14- and 16-bit ADCs.L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

DESCRIPTION

2 GHz Low Noise Differential 16-Bit ADC Buffer

LTC6416 Driving LTC2208 ADC – 140MHz IF

FEATURES

APPLICATIONS

n 2GHz –3dB Small Signal Bandwidthn 300MHz ±0.1dB Bandwidthn 1.8nV/√Hz Output Noisen 46.25dBm Equivalent OIP3 at 140MHzn 40.25dBm Equivalent OIP3 Up to 300MHzn –81dBc/–72dBc HD2/HD3 at 140MHz, 2VP-P Outn –84.5dBc IM3 at 140MHz, 2VP-P Out Compositen –74dBc/–67.5dBc HD2/HD3 at 300MHz, 2VP-P Outn –72.5dBc IM3 at 300MHz, 2VP-P Out Compositen Programmable High Speed, Fast Recovery

Output Clampingn DC-Coupled Signal Pathn Operates on Single 2.7V to 3.9V Supplyn Low Power: 150mW on 3.6Vn 2mm × 3mm 10-Pin DFN Package

n Differential ADC Drivern IF Sampling Receiversn Impedance Transformern SAW Filter Interfacen CCD Buffer

25Ω200Ω

200Ω

1pF

V+

GNDGND

VCM

OUT–

6416 TA01a

OUT+

1.5pF

1.5pF

0.1μF

0.1μF

3.6V

2.2μF

25Ω

3.3V

1:8

MINI-CIRCUITSTCM8-1+

50Ω

+–

AIN+

AIN–

PGA = 1

LTC2208

IN+

CLHI

CLLO

IN–

LTC6416

680pF

CLOCK(130MHz)

16

FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 TA01b

–120–110

–100

–90–80

–70

–60

–50

–40

–30–20

–10

10 3020 40 50

0V+ = 3.6V

HD2 = –94dBcHD3 = –89.1dBcSFDR = 89.1dBSNR = 70.7dB

MEASURED USING DC1257BWITH MINI-CIRCUIT TCM8-1+

1:8 TRANSFORMER

LTC6416 Driving LTC2208 ADC with 1:8 Transformer fIN =140MHz,

fS = 130MHz, –1dBFS, PGA = 1

LTC6416

26416f

PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS

Total Supply Voltage (V+ to GND)................................4VInput Current (CLLO, CLHI, VCM, IN+, IN–) ...........±10mAOutput Current (OUT+, OUT–) ...........................±22.5mAOperating Temperature Range (Note 2).... –40°C to 85°CSpecifi ed Temperature Range (Note 3) .... –40°C to 85°CStorage Temperature Range ................... –65°C to 150°CJunction Temperature ........................................... 150°C

(Note 1)TOP VIEW

11

DDB PACKAGE10-LEAD (3mm 2mm) PLASTIC DFN

VCM

CLHI

IN+

IN–

CLLO

V+

GND

OUT+

OUT–

GND6

8

7

9

10

5

4

2

3

1

TJMAX = 150°C, θJA = 76°C/W, θJC = 13.5°C/WEXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

3.6V ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3.6V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defi ned as (IN+ + IN–)/2. VOUTCM is defi ned as (OUT+ + OUT–)/2. VINDIFF is defi ned as (IN+ – IN–). VOUTDIFF is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input/Output Characteristics

GDIFF Differential Gain VINDIFF = ±1.2V Differentiall

–0.3–0.4

–0.15 00

dBdB

TCGDIFF Differential Gain Temperature Coeffi cient l –0.00033 dB/°C

VSWINGDIFF Differential Output Voltage Swing VOUTDIFF, VINDIFF = ±2.3Vl

3.73.3

4.2 VP-P VP-P

VSWINGMIN Output Voltage Swing Low Single-Ended Measurement of OUT+, OUT–. VINDIFF = ±2.3V l

0.2 0.30.35

VV

VSWINGMAX Output Voltage Swing High Single-Ended Measurement of OUT+, OUT–. VINDIFF = ±2.3V l

2.152

2.3 VV

IOUT Output Current Drive Single-Ended Measurement of OUT+, OUT– l ±20 mA

VOS Differential Input Offset Voltage IN+ = IN– = 1.25V, VOS = VOUTDIFF/GDIFF l

–5–10

–0.5 510

mVmV

TCVOS Differential Input Offset Voltage Drift l 1 μV/°C

VIOCM Common Mode Offset Voltage, Input to Output

VOUTCM – VINCMl

–65–75

–47 –15–5

mVmV

Lead Free Finish

TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC6416CDDB#TRMPBF LTC6416CDDB#TRPBF LDDY 10-Lead (3mm × 2mm) Plastic DFN 0°C to 70°C

LTC6416IDDB#TRMPBF LTC6416IDDB#TRPBF LDDY 10-Lead (3mm × 2mm) Plastic DFN –40°C to 85°C

TRM = 500 pieces. *Temperature grades are identifi ed by a label on the shipping container.

Consult LTC Marketing for parts specifi ed with wider operating temperature ranges.

Consult LTC Marketing for information on lead based fi nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/

LTC6416

36416f

3.6V ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3.6V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defi ned as (IN+ + IN–)/2. VOUTCM is defi ned as (OUT+ + OUT–)/2. VINDIFF is defi ned as (IN+ – IN–). VOUTDIFF is defi ned as (OUT+ – OUT–). See DC test circuit schematic.


IVRMIN Input Voltage Range, IN+, IN– (Minimum) (Single-Ended)

Defi ned by Output Voltage Swing Test l 0.1 V

IVRMAX Input Voltage Range IN+, IN– (Maximum) (Single-Ended)


IB Input Bias Current, IN+, IN– IN+ = IN– = 1.25V l –15 –5 15 μA

RINDIFF Differential Input Resistance VINDIFF = ±1.2V l 9 12 15 kΩ

CINDIFF Differential Input Capacitance 1 pF

RINCM Input Common Mode Resistance IN+ = IN– = 0.65V to 1.85V 6 kΩ

CMRR Common Mode Rejection Ratio IN+ = IN– = 0.65V to 1.85V,CMRR = (VOUTDIFF/GDIFF/1.2V) l

63.559.6

83 dBdB

eN Input Noise Voltage Density f = 100kHz 1.8 nV/√Hz

iN Input Noise Current Density f = 100kHz 6.5 pA/√Hz

Output Common Mode Voltage Control

GCM VCM Pin Common Mode Gain VCM = 0.65V to 1.85V l 0.9 0.96 1.05 V/V

VINCMDEFAULT Default Input Common Mode Voltage VINCM. IN+, IN–, VCM Pin Floating l 1.3 1.38 1.45 V

VOS (VCM – VINCM) Offset Voltage, VCM to VINCM VCM – VINCM, VCM = 1.25V l –70 –28 70 mV

VOUTCMDEFAULT Default Output Common Mode Voltage Inputs Floating, VCM Pin Floating l 1.25 1.34 1.45 V

VOS (VCM – VOUTCM) Offset Voltage, VCM to VOUTCM VCM – VOUTCM, VCM = 1.25V l –60 15 60 mV

VOUTCMMIN Output Common Mode Voltage Range (Minimum)

VCM = 0.1Vl

0.37 0.50.55

VV

VOUTCMMAX Output Common Mode Voltage Range (Maximum)

VCM = 2.7Vl

2.32.25

2.46 VV

VCMDEFAULT VCM Pin Default Voltage l 1.325 1.36 1.425 V

RVCM VCM Pin Input Resistance l 2.5 3.8 5.1 kΩ

CVCM VCM Pin Input Capacitance 1 pF

IBVCM VCM Pin Bias Current VCM = 1.25V l –50 –32 50 μA

DC Clamping Characteristics

VCLHIDEFAULT Default Output Clamp Voltage, High l 2.3 2.45 2.6 V

VOS (CLHI – VOUTCM) Offset Voltage, CLHI to VOUTCM l –55 13 55 mV

VCLLODEFAULT Default Output Clamp Voltage, Low l 0.125 0.265 0.425 V

VOS (CLLO – VOUTCM) Offset Voltage, CLLO to VOUTCM l –120 –70 0 mV

RCLHI CLHI Pin Input Resistance VCLHI = 2.45V l 3 4.1 5 kΩ

IBCLHI CLHI Pin Bias Current VCLHI = 2.45V l –25 –1 25 μA

RCLLO CLLO Pin Input Resistance VCLLO = 0.275V l 1.5 2.3 3.2 kΩ

IBCLLO CLLO Pin Bias Current VCLLO = 0.275V l –25 4.5 25 μA

Power Supply

VS Supply Voltage Range l 2.7 3.9 V

IS Supply Currentl

33 42 5154

mAmA

PSRR Power Supply Rejection Ratio VS = 2.7V to 3.6V l 57.5 80 dB

LTC6416

46416f

3.3V ELECTRICAL CHARACTERISTICS


Input/Output Characteristics

GDIFF Differential Gain VINDIFF = ±1.2Vl

–0.3–0.4

–0.15 00

dBdB

TCGDIFF Differential Gain Temperature Coeffi cient l –0.00033 dB/°C

VOUTDIFF Differential Output Voltage Swing VINDIFF = ±2.3Vl

3.53.2

4 VP-P VP-P

VOUTMIN Output Voltage Swing Low Single-Ended Measurement of OUT+, OUT–. VINDIFF = ±2.3V l

0.2 0.30.35

VV

VOUTMAX Output Voltage Swing High Single-Ended Measurement of OUT+, OUT–. VINDIFF = ±2.3V l

2.051.95

2.2 VV

IOUT Output Current Drive (Note 4) Single-Ended Measurement of OUT+, OUT– l ±20 mA

VOS Differential Input Offset Voltage IN+ = IN– = 1.25V, VOS = VOUTDIFF/GDIFF l

–5–10

–0.1 510

mVmV

TCVOS Differential Input Offset Voltage Drift l 1 μV/°C

VIOCM Common Mode Offset Voltage, Input to Output

VOUTCM – VINCMl

–65–75

–40 –15–5

mVmV

IVRMIN Input Voltage Range, IN+, IN– (Minimum) (Single-Ended)


IVRMAX Input Voltage Range, IN+, IN– (Maximum) (Single-Ended)


IB Input Bias Current, IN+, IN– IN+ = IN– = 1.25V l –15 –4 15 μA

RINDIFF Differential Input Resistance VINDIFF = ±1.2V l 9 12 15 kΩ

CINDIFF Differential Input Capacitance 1 pF

RINCM Input Common Mode Resistance IN+ = IN– = 0.65V to 1.85V 6 kΩ

CMRR Common Mode Rejection Ratio IN+ = IN– = 0.65V to 1.85V = ΔVINCM,CMRR = (VOUTDIFF/GDIFF/ΔVINCM) l

63.559.6

83 dBdB

eN Input Noise Voltage Density f = 100kHz 1.8 nV/√Hz

iN Input Noise Current Density f = 100kHz 6.5 pA/√Hz

Output Common Mode Voltage Control

GCM VCM Pin Common Mode Gain VCM = 0.65V to 1.85V l 0.9 0.96 1.05 V/V

VINCMDEFAULT Default Input Common Mode Voltage VINCM. IN+, IN–, VCM Pin Floating l 1.2 1.28 1.35 V

VOS (VCM – VINCM) Offset Voltage, VCM to VINCM VCM – VINCM, VCM = 1.25V l –70 –26 70 mV

VOUTCMDEFAULT Default Output Common Mode Voltage Inputs Floating, VCM Pin Floating l 1.15 1.24 1.35 V

VOS (VCM – VOUTCM) Offset Voltage, VCM to VOUTCM VCM – VOUTCM, VCM = 1.25V l –60 14 60 mV

VOUTCMMIN Output Common Mode Voltage (Minimum)

VCM = 0.1Vl

0.34 0.50.55

VV

VOUTCMMAX Output Common Mode Voltage (Maximum)

VCM = 2.4Vl

2.052

2.16 VV

VCMDEFAULT VCM Pin Default Voltage l 1.2 1.25 1.3 V

RVCM VCM Pin Input Resistance l 2.5 3.8 5.1 kΩ

CVCM VCM Pin Input Capacitance 1 pF

IBVCM VCM Pin Bias Current VCM = 1.25V l –10 0.2 10 μA

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3.3V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defi ned as (IN+ + IN–)/2. VOUTCM is defi ned as (OUT+ + OUT–)/2. VINDIFF is defi ned as (IN+ – IN–). VOUTDIFF is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

LTC6416

56416f


Differential AC Characteristics

–3dBBW –3dB Bandwidth 200mVP-P,OUT Differential 2 GHz

0.1dBBW ±0.1dB Bandwidth 200mVP-P,OUT Differential 0.3 GHz

0.5dBBW ±0.5dB Bandwidth 200mVP-P,OUT Differential 1.4 GHz

1/f 1/f Noise Corner 25 kHz

SR Slew Rate Differential 3.4 V/ns

tS1% 1% Settling Time 2VP-P,OUT 1.8 ns

Common Mode AC Characteristics (VCM Pin)

–3dBBWVCM VCM Pin Small Signal –3dB BW VCM = 0.1VP-P, Measured Single-Ended at Output

9 MHz

SRCM Common Mode Slew Rate Measured Single-Ended at Output 40 V/μs

AC Clamping Characteristics

tOVDR Overdrive Recovery Time 1.9VP-P,OUT 5 ns

AC Linearity

70MHz Signal

HD2 Second Harmonic Distortion V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-PV+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-PV+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-PV+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P

–83.5–71

–78.5–88.5

dBcdBcdBcdBc

AC ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3.3V and 3.6V unless otherwise noted, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = VCC, CLLO = 0V unless otherwise noted. VINCM is defi ned as (IN+ + IN–)/2. VOUTCM is defi ned as (OUT+ + OUT–)/2. VINDIFF is defi ned as (IN+ – IN–). VOUTDIFF is defi ned as (OUT+ – OUT–). See DC test circuit schematic.


DC Clamping Characteristics

VCLHIDEFAULT Default Output Clamp Voltage, High l 2.1 2.23 2.4 V

VOS (CLHI – VOUTCM) Offset Voltage, CLHI to VOUTCM l –55 4 55 mV

VCLLODEFAULT Default Output Clamp Voltage, Low l 0.1 0.25 0.4 V

VOS (CLLO – VOUTCM) Offset Voltage, CLLO to VOUTCM l –120 –72 0 mV

RCLHI CLHI Pin Input Resistance VCLHI = 2.25V l 3 4.1 5 kΩ

IBCLHI CLHI Pin Bias Current VCLHI = 2.25V l –25 –1 25 μA

RCLLO CLLO Pin Input Resistance VCLLO = 0.25V l 1.5 2.3 3.2 kΩ

IBCLLO CLLO Pin Bias Current VCLLO = 0.25V l –25 3 25 μA

Power Supply

VS Supply Voltage Range l 2.7 3.9 V

IS Supply Currentl

33 42 5154

mAmA

PSRR Power Supply Rejection Ratio VS = 2.7V to 3.6V l 57.5 80 dB

The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3.3V, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = V+, CLLO = 0V unless otherwise noted. VINCM is defi ned as (IN+ + IN–)/2. VOUTCM is defi ned as (OUT+ + OUT–)/2. VINDIFF is defi ned as (IN+ – IN–). VOUTDIFF is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

3.3V ELECTRICAL CHARACTERISTICS

LTC6416

66416f

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC6416C/LTC6416I is guaranteed functional over the

operating temperature range of –40°C to 85°C.

Note 3: The LTC6416C is guaranteed to meet specifi ed performance from

0°C to 70°C. It is designed, characterized and expected to meet specifi ed

performance from –40°C and 85°C but is not tested or QA sampled


HD3 Third Harmonic Distortion V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-PV+ = 3.3V, VCM = 1.25V, VOUTDIFF = 2VP-PV+ = 3.6V, VCM = 1.05V, VOUTDIFF = 2VP-PV+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P

–73–60

–94.5–83

dBcdBcdBcdBc

IM3 Output Third Order Intermodulation Distortion

V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-PV+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P

–76.5–86

dBcdBc

OIP3 Output Third Order Intercept (Equivalent) (Note 5)


42.2547

dBmdBm

P1dB Output 1dB Compression Point (Equivalent) (Note 5)

V+ = 3.6V, VCM = 1.25V 14.1 dBm

140MHz Signal


–79.5–75.5–73–81

dBcdBcdBcdBc


–64–55–70–72

dBcdBcdBcdBc



–75–84.5

dBcdBc



41.546.25

dBmdBm


V+ = 3.6V, VCM = 1.25V 14.1 dBm

300MHz Signal


–75–65

–69.5–74

dBcdBcdBcdBc


–59–51.5–63

–67.5

dBcdBcdBcdBc



–68.5–72.5 –64

dBcdBc


V+ = 3.3V, VCM = 1.05V, VOUTDIFF = 2VP-PV+ = 3.6V, VCM = 1.25V, VOUTDIFF = 2VP-P 36

38.2540.25

dBmdBm


V+ = 3.6V, VCM = 1.25V 12.9 dBm

AC ELECTRICAL CHARACTERISTICS The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at TA = 25°C. V+ = 3.3V and 3.6V unless otherwise noted, GND = 0V, No RLOAD, CLOAD = 6pF. VCM = 1.25V, CLHI = VCC, CLLO = 0V unless otherwise noted. VINCM is defi ned as (IN+ + IN–)/2. VOUTCM is defi ned as (OUT+ + OUT–)/2. VINDIFF is defi ned as (IN+ – IN–). VOUTDIFF is defi ned as (OUT+ – OUT–). See DC test circuit schematic.

at these temperatures. The LT6416I is guaranteed to meet specifi ed

performance from –40°C to 85°C.

Note 4: This parameter is pulse tested.

Note 5: Since the LTC6416 is a voltage-output buffer, a resistive load is not

required when driving an AD converter. Therefore, typical output power is very

small. In order to compare the LTC6416 with amplifi ers that require a 50Ω

output load, the LTC6416 output voltage swing driving a given RL is converted

to OIP3 and P1dB as if it were driving a 50Ω load. Using this modifi ed

convention, 2VP-P is by defi nition equal to 10dBm, regardless of actual RL.

LTC6416

76416f

FREQUENCY (MHz)

DIF

FER

EN

TIA

L G

AIN

(dB

)

6416 G01

10 1000 10000100

V+ = 3.3V2

0

–4

–8

–12

–2

–6

–10

–14

–16

S11 (

dB

)

6416 G02

V+ = 3.3V0

–20

–25

–5

–15

–10

–30

–35

FREQUENCY (MHz)

10 1000100

DIF

FER

EN

TIA

L O

UTP

UT R

ETU

RN

LO

SS

(dB

)

6416 G03

V+ = 3.3V0

–1

–4

–8

–7

–2

–3

–6

–5

–9

–10

FREQUENCY (MHz)

10 1000100

DIF

FER

EN

TIA

L R

EV

ER

SE I

SO

LA

TIO

N (

dB

)

6416 G04

V+ = 3.3V–20

–40

–80

–70

–30

–60

–50

–90

–100

FREQUENCY (MHz)

10 1000100

TYPICAL PERFORMANCE CHARACTERISTICS

Differential Reverse Isolation (S12) vs Frequency

Differential Forward Gain (S21) vs Frequency

Differential Input Return Loss (S11) vs Frequency

Differential Output Return Loss (S22) vs Frequency

–50

–60

–70

–80

–90

–100

FREQUENCY (MHz)

HD

2, H

D3 (

dB

c)

6416 G05

10 100 500

V+ = 3.3VVCM = 1.25VRLOAD = 400ΩVOUT = 2VP-P DIFFERENTIAL

HD2

HD3–50

–60

–70

–80

–90

–100

FREQUENCY (MHz)

HD

2, H

D3 (

dB

c)

6416 G06

V+ = 3.6VVCM = 1.25VRLOAD = 400ΩVOUT = 2VP-P DIFFERENTIAL

HD2

HD3

10 100 500

Second and Third Harmonic Distortion vs Frequency

Second and Third Harmonic Distortion vs Frequency

LTC6416

86416f


Third Order Intermodulation Distortion (IM3) vs Frequency and Supply Voltage

Third Order Intermodulation Distortion (IM3) vs Output Common Mode Voltage (140MHz)

Output Third Order Intercept (OIP3EQUIV) vs Frequency and Supply Voltage

Output Third Order Intercept (OIP3EQUIV) vs Output Common Mode Voltage and Supply Voltage (140MHz)

Output 1dB Compression (Equivalent) vs Frequency, VCM and Supply Voltage

Second and Third Harmonic Distortion vs Output Common Mode Voltage (140MHz)




–50

–60

–70

–80

–90

–100

VCM (V)

HD

2, H

D3 (

dB

c)

6416 G07

V+ = 3.6VRLOAD = 400ΩVOUT = 2VP-P DIFFERENTIAL

HD2

HD3

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

–50

–60

–70

–80

–90

–100

VCM (V)

HD

2, H

D3 (

dB

c)

6416 G08


HD2

HD3

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

–50

–60

–70

–80

–90

–100

VCM (V)

HD

2, H

D3 (

dB

c)

6416 G09


HD2

HD3

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

–50

–60

–70

–80

–90

–100

VCM (V)

HD

2, H

D3 (

dB

c)

6416 G10


HD2

HD3

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

–50

–60

–70

–80

–90

–100

FREQUENCY (MHz)

IM3 (

dB

c)

6416 G11

V+ = 3.3V, 3.6V; VCM = 1.25VRLOAD = 400ΩVOUT = 2VP-P DIFFERENTIAL (COMPOSITE)

f = 1MHz

IM3 VCC = 3.3V

IM3 VCC = 3.6V

0 250 450150 350 500200 400100 30050

–50

–60

–70

–80

–90

–100

VCM (V)

IM3 (

dB

c)

6416 G12

V+ = 3.3V, 3.6VRLOAD = 400ΩVOUT = 2VP-P DIFFERENTIAL (COMPOSITE)

f = 1MHz

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

IM3 V+ = 3.3V

IM3 V+ = 3.6V

50

45

40

35

30

25

FREQUENCY (MHz)

OIP

3EQ

UIV

(dB

)

6416 G13

V+ = 3.3V, 3.6VVCM = 1.25VRLOAD = 400ΩVOUT = 2VP-P DIFFERENTIAL (COMPOSITE)

f = 1MHz

OIP3 VCC = 3.3V

OIP3 VCC = 3.6V

0 250 450150 350 500200 400100 30050

50

45

40

35

30

25

OIP

3EQ

UIV

(dB

m)

6416 G14

V+ = 3.3V, 3.6VRLOAD = 400ΩVOUT = 2VP-P DIFFERENTIAL (COMPOSITE)

f = 1MHz

OIP3EQUIV V+ = 3.3V

OIP3EQUIV V+ = 3.6V

1.05 1.15 1.251.10 1.20 1.35 1.451.30 1.40

VCM (V)

15.0

14.0

13.0

12.0

11.0

14.5

13.5

12.5

11.5

10.5

10.0

FREQUENCY (MHz)

P1dB

CO

MP

RES

SIO

N (

EQ

UIV

ALEN

T)

(dB

m)

6416 G15

V+ = 3.3V, 3.6VRLOAD = 400ΩVOUT = 2VP-P DIFFERENTIAL

VCM = 1.05V

VCM = 1.25V

0 250150 350 400200100 30050

V+ = 3.3VV+ = 3.6V

LTC6416

96416f

Supply Current vs Supply Voltage


Noise Figure and Input Referred Noise Voltage vs Frequency PSRR vs Frequency

SUPPLY VOLTAGE (V)6416 G16

0 2.51.5 3.5 4.02.01.0 3.00.5

50

45

40

35

30

25

20

15

10

5

0

SU

PP

LY C

UR

REN

T (

mA

)

FREQUENCY (Hz)

INP

UT R

EFE

RR

ED

NO

ISE V

OLT

AG

E (

nV

√H

z)N

OIS

E FIG

UR

E (d

B)

6416 G17

14

10

12

8

6

4

2

0

14

10

12

8

6

4

2

01k 10k 100k 100M 1G10M1M

eN

NF

Positive Overdrive Recovery (VCLHI Pin)

200mV/DIV

6416 G1820ns/DIV

IN+

OUT+

Negative Overdrive Recovery (VCLLO Pin)

6416 G1920ns/DIV

200mV/DIV

IN+

OUT+

6416 G30500ps/DIV

10mV/DIV

Small Signal Transient Response, Rising Edge

FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 G20

–130–120–110–100–90–80–70–60–50–40–30–20–10

10 30

3

2

20 40 50

0V+ = 3.6VHD2 = –104.9dBcHD3 = –86.1dBcSFDR = 86.05dBSNR = 76.5dBSEE FIGURE 5/TABLE 11:1 BALUN

FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 G21

–130–120–110–100–90–80–70–60–50–40–30–20–10

10 3020 40 50

0V+ = 3.6VHD2 = –101.9dBcHD3 = –96.2dBcSFDR = 96.2dBcSNR = 74.2dBSEE FIGURE 5/TABLE 11:1 BALUN

32

LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 30MHz, –1dBFS, PGA = 0


6416 G31500ps/DIV

10mV/DIV

Small Signal Transient Response, Falling Edge

0.1 1

40

60

70

80

50

1000

6416 G29

30

0

10

20

10 100

90V+ = 3.6V

FREQUENCY (MHz)

PSRR

(dB)

LTC6416

106416f


FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 G22

–130–120–110–100–90–80–70–60–50–40–30–20–10

10 3020 40 50

0V+ = 3.6VHD2 = –95dBcHD3 = –86dBcSFDR = 86dBcSNR = 74.6dBFSSEE FIGURE 5/TABLE 1 1:1 BALUN

32

FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 G23

–130–120–110–100–90–80–70–60–50–40–30–20–10

10 3020 40 50

0V+ = 3.6VHD2 = –99dBcHD3 = –91dBcSFDR = 91dBcSNR = 73dBFSSEE FIGURE 5/TABLE 1 1:1 BALUN

32

FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 G24

–130–120–110–100–90–80–70–60–50–40–30–20–10

10 3020 40 50

0V+ = 3.6V

HD2 = –85.6dBcHD3 = –95.5dBcSFDR = 85.6dBcSNR = 72.6dBFS

SEE FIGURE 5/TABLE 11:1 BALUN

3 52

FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 G25

–130–120–110–100–90–80–70–60–50–40–30–20–10

10 3020 40 50

0

32

V+ = 3.6VHD2 = –91.8dBcHD3 = –93.6dBcSFDR = 91.8dBcSNR = 70.9dBFS

SEE FIGURE 5/TABLE 11:1 BALUN

FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 G26

–130–120–110–100–90–80–70–60–50–40–30–20–10

10 3020 40 50

0V+ = 3.6VIM3 = 86dBcSEE FIGURE 5/TABLE 1 1:1 BALUN

FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 G27

–130–120–110–100–90–80–70–60–50–40–30–20–10

10 3020 40 50

0V+ = 3.6VIM3 = 81.7dBcSEE FIGURE 5/TABLE 1 1:1 BALUN

FREQUENCY (MHz)0

AMPL

ITUD

E (d

BFS)

60

6416 G28

–130–120–110–100–90–80–70–60–50–40–30–20–10

10 3020 40 50

0V+ = 3.6V

IM3 = 81.7dBcSEE FIGURE 5/TABLE 1

1:1 BALUN


LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 30MHz and 31MHz, –7dBFS/Tone, PGA = 0

LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 70MHz and 71MHz, –7dBFS/Tone, PGA = 0

LTC6416 Driving LTC2208 16-Bit ADC, 64K Point FFT, fIN = 139.5MHz and 140.5MHz, –7dBFS/Tone, PGA = 0




LTC6416

116416f

PIN FUNCTIONSVCM (Pin 1): This pin sets the output common mode voltage seen at OUT+ and OUT– by driving IN+ and IN– through an internal buffer with a high output resistance of 6k. The VCM pin has a Thevenin equivalent resistance of approximately 3.8k and can be overdriven by an external voltage. If no voltage is applied to VCM, it will fl oat to a default voltage of approximately 1.25V on a 3.3V supply or 1.36V on a 3.6V supply. The VCM pin should be bypassed with a high-quality ceramic bypass capacitor of at least 0.1μF.

CLHI (Pin 2): High Side Clamp Voltage. The voltage applied to the CLHI pin defi nes the upper voltage limit of the OUT+ and OUT– pins. This voltage should be set at least 300mV above the upper voltage range of the driven ADC. On a 3.3V supply, the CLHI pin will fl oat to a 2.23V default voltage. On a 3.6V supply, the CLHI pin will fl oat to a 2.45V default voltage. CLHI has a Thevenin equivalent of approximately 4.1kΩ and can be overdriven by an external voltage. The CLHI pin should be bypassed with a high-quality ceramic bypass capacitor of at least 0.1μF.

IN+,IN– (Pins 3, 4): Non-inverting and inverting input pins of the buffer, respectively. These pins are high impedance, approximately 6kΩ. If AC-coupled, these pins will self bias to the voltage present at the VCM pin.

CLLO (Pin 5): Low Side Clamp Voltage. The voltage ap-plied to the CLLO pin defi nes the lower voltage limit of the OUT+ and OUT– pins. This voltage should be set at least 300mV below the lower voltage range of the driven

ADC. On a 3.3V supply, the CLLO pin will fl oat to a 0.25V default voltage. On a 3.6V supply, the CLLO pin will fl oat to a 0.265V default voltage. CLLO has a Thevenin equivalent resistance of approximately 2.3k and can be overdriven by an external voltage. The CLLO pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.1μF.

GND (Pins 6, 9, 11): Negative power supply, normally tied to ground. Both pins and the exposed paddle must be tied to the same voltage. GND may be tied to a voltage other than ground as long as the voltage between V+ and GND is 2.7V to 4V. If the GND pins are not tied to ground, bypass them with 680pF and 0.1μF capacitors as close to the package as possible.

OUT–, OUT+ (Pins 7, 8): Outputs. The LTC6416 outputs are low impedance. Each output has an output impedance of approximately 9Ω at DC.

V+ (Pin 10): Positive Power Supply. Typically 3.3V to 3.6V. Split supplies are possible as long as the voltage between V+ and GND is 2.7V to 4V. Bypass capacitors of 680pF and 0.1μF as close to the part as possible should be used between the supplies.

Exposed Pad (Pin 11): Ground. The exposed pad must be soldered to the printed circuit board ground plane for good heat transfer. If GND is a voltage other than ground, the Exposed Pad must be connected to a plane with the same potential as the GND pins – Not to the system ground plane.

DC TEST CIRCUIT SCHEMATIC

81

2

3

4

5

69

11

7

CLOAD

V+

V+

10

OUT–

6416 DC

OUT+ OUT–

OUT+

RLOAD

VCMVCM

IN+IN+

CLHICLHI

CLLOCLLO

IN–IN–

LTC6416

VINDIFF = IN+ – IN–

IN+ + IN–

2VINCM =

VOUTDIFF = OUT+ – OUT–

OUT+ + OUT–

2VOUTCM =

LTC6416

126416f

BLOCK DIAGRAM

R36k

I1 I11 I13

R413k

R513.5k

x1

VCM

CLHI

IN+

IN–

CLLO

R62.5k

Q3

Q1

Q13

Q11

I2 I12

Q5

R16k

R116k

1

2

3

4

5

Q2

Q4

Q12

Q14R129Ω

7

V+

10

OUT–

GND (6, 9)

6416 BD

R29Ω

8OUT+

LTC6416 Simplifi ed Schematic

LTC6416

136416f

APPLICATIONS INFORMATIONCircuit Operation

The LTC6416 is a low noise and low distortion fully dif-ferential unity-gain ADC driver with operation from DC to 2GHz (–3dB bandwidth), a differential input impedance of 12kΩ, and a differential output impedance of 18Ω. The LTC6416 is composed of a fully differential buffer with output common mode voltage control circuitry and high speed voltage-limiting clamps at the output. Small output resistors of 9Ω improve the circuit stability over various load conditions. They also simplify possible external fi lter-ing options, which are often desirable when the load is an ADC. Lowpass or bandpass fi lters are easily implemented with just a few external components. The LTC6416 is very fl exible in terms of I/O coupling. It can be AC- or DC-coupled at the inputs, the outputs or both. When using the LTC6416 with DC-coupled inputs, best performance is obtained with an input common mode voltage between 1V and 1.5V. For AC-coupled operation, the LTC6416 will take the voltage applied to the VCM pin and use it to bias the inputs so that the output common mode voltage equals VCM, thus no external circuitry is needed. The VCM pin has been designed to directly interface with the VCM pin found on Linear Technology’s 16-, 14- and 12-bit high speed ADC families.

Input Impedance and Matching

The LTC6416 has a high differential input impedance of 12kΩ. The differential inputs may need to be terminated to a lower value impedance, e.g. 50Ω, in order to provide an impedance match for the source. Figure 1 shows input

matching using a 1:1 balun, while Figure 2 shows match-ing using a 1:4 balun. These circuits provide a wideband impedance match. The balun and matching resistors must be placed close to the input pins in order to minimize the rejection due to input mismatch. In Figure 1, the capaci-tor center-tapping the two 24.9Ω resistors improves high frequency common mode rejection. As an alternative to this wideband approach, a narrowband impedance match can be used at the inputs of the LTC6416 for frequency selection and/or noise reduction.

The noise performance of the LTC6416 also depends upon the source impedance and termination. For example, the input 1:4 balun in Figure 2 improves SNR by adding 6dB of voltage gain at the inputs. A trade-off between gain and noise is obvious when constant noise fi gure circle and constant gain circle are plotted within the same input Smith Chart. This technique can be used to determine the optimal source impedance for a given gain and noise requirement.

Output Match and Filter

The LTC6416 provides a source resistance of 9Ω at each output. For testing purposes, Figure 3 and Figure 4 show the LTC6416 driving a differential 400Ω load impedance using a 1:1 or 1:4 balun, respectively.

The LTC6416 can drive an ADC directly without external output impedance matching, but improved performance can usually be obtained with the addition of a few external components. Figure 5 shows a typical topology used for driving the LTC2208 16-bit ADC.

Figure 1. Input Termination for Differential 50Ω Input Impedance Using a 1:1 Balun

••

VIN

IN+

IN–

3

4

24.9Ω 0.1μF50Ω

24.9Ω

OUT–

6416 F01

OUT+

7

8

LTC6416

0.1μF

0.1μF

1:1

+–

LTC6416

146416f

• •165Ω

0.1μF

0.1μF 1:1

0.1μF

IN+

IN–

3

4OUT–

6416 F03

OUT+

7

8

LTC641650Ω

165Ω

••

VIN

IN+

IN–

3

4

100Ω

100Ω

50Ω

OUT–

6416 F02

OUT+

7

8

LTC6416

0.1μF

0.1μF

1:4

+–

0.1μF

APPLICATIONS INFORMATION

Figure 2. Input Termination for Differential 50Ω Input Impedance Using a 1:4 Balun

Figure 3. Output Termination for Differential 400Ω Load Impedance Using a 1:1 Balun

Figure 4. Output Termination for Differential 400Ω Load Impedance Using a 4:1 Balun

• •

90.9Ω0.1μF

0.1μF 4:1

0.1μF

IN+

IN–

3

4OUT–

6416 F04

OUT+

7

8

LTC641650Ω

90.9Ω

Figure 5. DC1257B Simplifi ed Schematic with Suggested Output Termination for Driving an LTC2208 16-Bit ADC at 140MHz

V+

VCM

OUT–

6416 F05

OUT+

3.6V

2.2μF

IN+

CLHI

CLLO

IN–

LTC6416 1pF

1.5pF

1.5pF

3.3V

CLOCK(130MHz)

DATA16

VCM

LTC2208

AIN+

AIN–

25Ω

25ΩGND

GND

R36100Ω

R15100Ω

0.1μF

C390.01μF

3

2

16

4

50Ω

680pF

T1TCM4-19+

+–

LTC6416

156416f

APPLICATIONS INFORMATIONAs seen in Table 1, suggested component values for the fi lter will change for differing IF frequencies.

Table 1.

INPUTFREQUENCY

LTC6416 OUTPUT RESISTORS

FILTERING CAPACITORS

30MHz 50Ω 5.6pF/6.8pF/5.6pF

70MHz 25Ω 5.6pF/6.8pF/5.6pF

140MHz 25Ω 1.5pF/1pF/1.5pF

250MHz 5Ω -/-/-

Output Common Mode Adjustment

The output common mode voltage is set by the VCM pin. Because the input common mode voltage is approximately the same as the output common mode voltage, both are approximately equal to VCM. The VCM pin has a Thevenin equivalent resistance of 3.8k and can be overdriven by an external voltage. The VCM pin fl oats to a default voltage of 1.25V on a 3.3V supply and 1.36V on a 3.6V supply. The output common mode voltage is capable of tracking VCM in a range from 0.34V to 2.16V on a 3.3V supply. The VCM pin can be fl oated, but it should always be bypassed close to the LTC6416 with a 0.1μF bypass capacitor to ground. When interfacing with A/D converters such as the LTC22xx families, the VCM pin can be connected to the VCM output pin of the ADC, as shown in Figure 5.

CLLO and CLHI Pins

The CLLO and CLHI pins are used to set the clamping voltage for high speed internal circuitry. This circuitry limits the single-ended minimum and maximum voltage excursion seen at each of the outputs. This feature is extremely important in applications with input signals having very large peak-to-average ratios such as cellular basestation receivers. If a very large peak signal arrives at the LTC6416, the voltages applied to the CLLO and CLHI pins will determine the minimum and maximum output swing respectively. Once the input signal returns to the normal operating range, the LTC6416 returns to linear operation within 5ns. Both CLLO and CLHI are high impedance inputs. CLLO has an input impedance of 2.3k, while CLHI has an input impedance of 4.1k. On a 3.3V supply, CLLO self-biases to 0.25V while CLHI self-biases

to 2.23V. On a 3.6V supply, CLLO self-biases to 0.265V while CLHI self-biases to 2.45V. Both CLLO and CLHI pins should be bypassed with a 0.1μF capacitor as close to the LTC6416 as possible.

Interfacing the LTC6416 to A/D Converters

The LTC6416 has been specifi cally designed to interface directly with high speed A/D converters. It is possible to drive the ADC directly from the LTC6416. In practice, however, better performance may be obtained by adding a few external components at the output of the LTC6416. Figure 5 shows the LTC6416 being driven by a 1:8 trans-former which provides 9dB of voltage gain while also performing a single-ended to differential conversion. The differential outputs of the LTC6416 are lowpass fi ltered, then drive the differential inputs of the LTC2208 ADC. In many applications, an anti-alias fi lter like this is desir-able to limit the wideband noise of the amplifi er. This is especially true in high performance 16-bit designs. The minimum recommended network between the LTC6416 and the ADC is simply two 5Ω series resistors, which are used to help eliminate resonances associated with the stray capacitance of PCB traces and the stray inductance of the internal bond wires at the ADC input, and the driver output pins.

Single-Ended Signals

The LTC6416 has not been designed to convert single-ended signals to differential signals. A single-ended input signal can be converted to a differential signal via a balun connected to the inputs of the LTC6416.

Power Supply Considerations

For best linearity, the LTC6416 should have a positive supply of V+ = 3.6V. The LTC6416 has an internal edge-trig-gered supply voltage clamp. The timing mechanism of the clamp enables the LTC6416 to withstand ESD events. This internal clamp is also activated by voltage overshoot and rapid slew rate on the positive supply V+ pin. The LTC6416 should not be hot-plugged into a powered socket. Bypass capacitors of 680pF and 0.1μF should be placed to the V+ pin, as close as possible to the LTC6416.

LTC6416

166416f

APPLICATIONS INFORMATIONTest Circuits

Due to the fully differential design of the LTC6416 and its usefulness in applications both with and without ADCs, two test circuits are used to generate the information in this data sheet. Test circuit A is Demo Board DC1287A, a two-port demonstration circuit for the LTC6416. The board layout and the schematic are shown in Figures 6 and 7. This circuit includes input and output 1:1 baluns for single-ended-to-differential conversion, allowing direct analysis using a 2-port network analyzer. In this circuit implementation, there are series resistors at the

output to present the LTC6416 with a 382Ω differential load, thereby optimizing distortion performance. Including the 1:1 input and output baluns, the –3dB bandwidth is approximately 2GHz.

Test circuit B is Demo Circuit DC1257B. It consists of an LTC6416 driving an LTC2208 ADC. It is intended for use in conjunction with demo circuit DC890B (computer interface board) and proprietary Linear Technology evaluation soft-ware to evaluate the performance of both parts together. Both the DC1257B board layout and the schematic can be seen in Figures 8 and 9.

Figure 6. Demo Board DC1287A Layout

Figure 7. Demo Board DC1287A Schematic (Test Circuit A)

J1IN+

J2IN–

J3OUT+

J4OUT–

CLLOC130.1μF

VCM

VCMV+

2.7V TO 4V

GND

CLHI

CLLO

1

5GND

GND

6416 TA04

CLHI2

IN+3

IN–4

GND9

OUT+ 8

OUT– 7

V+

6

11

10

LTC6416

GND

R40Ω

R50Ω

R1165Ω

R3165Ω

C70.1μF

T1MABA-007190-000000

T2MABA-007190-000000

C10OPT

C10.1μF

C2680pF

C30.1μF

C8OPT

C120.1μF

C50.1μF

C9OPT

C6OPT

C110.1μF

C40.1μF

R224.9Ω

R624.9Ω

C150.1μF

C140.1μF

2

5 1

4 3

• •

2

3 4

1 5

••

LTC6416

176416f


Figure 8. Demo Board DC1257B Layout

LTC6416

186416f

LTC

22

08

CU

P

SE

NS

E

GN

D

VC

M

GN

D

VD

D

VD

D

GN

D

AIN

+

AIN

−

GN

D

GN

D

EN

C+

EN

C−

GN

D

VD

D

VD

D

VC

M

DA

6

DA

5

DA

4

DA

3

DA

2

DA

1

DA

0

CL

KC

OU

TA

CL

KC

OU

TB

OFB

DB

15

DB

14

DB

13

DB

12

DB

11

DB

10

1 2 3 4 5 6 7 8 9

10

11

12

13

14

15

16

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PGA

RAND

MODE

LVDS

OFA

DA15

DA14

DA13

DA12

DA11

DA10

DA9

DA8

DA7

OGND

OVDD

17

18

19

20

21

22

23

24

25

26

27

27

29

30

31

32

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

VDD

GND

SHDN

DITH

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

DB8

DB9

OGND

OVDD

GND

C2

21

pF

R1

32

4.9

Ω

R1

52

4.9

Ω

C2

41

.5p

F

C2

01

.5p

F

C1

62

.2μ

F

C1

40

.1μ

F

C1

76

80

pF

65

R7, 100Ω

R6

OPT

R5

OPT

31

OFF

VD

DV

DD

JP2

RA

ND

R2

10

ΩR

31

0Ω

JP1

PG

A

2R

4 1k

31

LO

W

E7

EX

TR

EF

HI 2

E2

CL

HI

E3

CL

LO

VD

D

VD

D

OV

P

OV

P

C1

20

.1μ

F

C1

10

.1μ

F

6416 F

09

R2

84

.99

k

R2

54

.99

k

C3

10

.1μ

F

R2

44

.99

k

R2

9O

PT

R2

72

k

24

LC

02

5

8 7 6 5

1 2 3 4

VC

C

WP

SC

L

SD

A

A0

A1

A2

VS

S

31

ON

OFF

SH

DN

EN

JP3

SH

DN

AD

CJP

4D

ITH

2

31

2

VD

D

C1

00

.1μ

F

C9

0.1

μF

C8

0.1

μF

••

C3

00

.1μ

F

3 2 1

4 5

R1

95

1.1

Ω

R2

65

1.1

Ω

C2

80

.1μ

F

T2

MA

BA

-00

71

59

-00

00

00

R2

11

00

Ω

CL

K

J4

C2

90

.1μ

F

GN

DVS

3.6

V T

O 2

0V

3

2

1

LT1

96

3A

ES

T-3

.3

GN

DE

5E

4

E6

OP

TIN

OU

TC

32

10

μF

25

V

C3

31

0μ

F6

.3V

L1

(op

t.)

BL

M1

8P

G2

21

SN

1D

L2

BL

M1

8P

G2

21

SN

1D

L3

BL

M1

8P

G2

21

SN

1D

VS

VD

D

VC

C

OV

P

LTC

64

16

CD

DB

VC

C

VC

C

C2

60

.1μ

F

TC

M4−

19

+

T1

C2

50

.1μ

F

C2

70

.1μ

F

C1

30

.1μ

F

C2

1O

PT

J2 J3

R1

4A

10

0Ω

R1

4B

10

0Ω

V+

GN

D

OU

T+

OU

T−

GN

D

VC

M

CL

HI

IN+

IN−

CL

LO

GN

D

C1

90

.1μ

F

C2

3O

PT

R8

OP

T

R1

0O

PT

VC

C

C1

80

.1μ

F

1

1 2 3 4 5

10

9 8 7 6

11

24 5

3

R1

1O

PT

R1

2O

PT

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LTC6416

196416f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

2.00 ±0.10(2 SIDES)

NOTE:1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40 ± 0.10

BOTTOM VIEW—EXPOSED PAD

0.64 ± 0.05(2 SIDES)

0.75 ±0.05

R = 0.115TYPR = 0.05

TYP

2.39 ±0.05(2 SIDES)

3.00 ±0.10(2 SIDES)

15

106

PIN 1 BARTOP MARK

(SEE NOTE 6)

0.200 REF

0 – 0.05

(DDB10) DFN 0905 REV Ø

0.25 ± 0.05

2.39 ±0.05(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.64 ±0.05(2 SIDES)

1.15 ±0.05

0.70 ±0.05

2.55 ±0.05

PACKAGEOUTLINE

0.25 ± 0.050.50 BSC

PIN 1R = 0.20 OR0.25 × 45°CHAMFER

0.50 BSC

DDB Package10-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1722 Rev Ø)

LTC6416

206416f

Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008

LT 1108 • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

Fixed Gain IF Amplifi ers/ADC Drivers

LT1993-2/LT1993-4/LT1993-10

800MHz Differential Amplifi er/ADC Drivers –72dBc IM3 at 70MHz 2VP-P Composite, AV = 2V/V, 4V/V, 10V/V

LTC6400-8/LTC6400-14/LTC6400-20/LTC6400-26

1.8GHz Low Noise, Low Distortion Differential ADC Drivers

–71dBc IM3 at 240MHz 2VP-P Composite, IS = 90mA, AV = 8dB, 14dB, 20dB, 26dB

LTC6401-8/LTC6401-14/LTC6401-20/LTC6401-26

1.3GHz Low Noise, Low Distortion Differential ADC Drivers

–74dBc IM3 at 140MHz 2VP-P Composite, IS = 50mA, AV = 8dB, 14dB, 20dB, 26dB

LT6402-6/LT6402-12/LT6402-20

300MHz Differential Amplifi er/ADC Drivers –71dBc IM3 at 20MHz 2VP-P Composite, AV = 6dB, 12dB, 20dB

LTC6420-XX Dual 1.8GHz Low Noise, Low Distortion Differential ADC Drivers

Dual Version of the LTC6400-XX, AV = 8dB, 14dB, 20dB, 26dB

LTC6421-XX Dual 1.3GHz Low Noise, Low Distortion Differential ADC Drivers

Dual Version of the LTC6401-XX, AV = 8dB, 14dB, 20dB, 26dB

IF Amplifi ers/ADC Drivers with Digitally Controlled Gain

LT5514 Ultra-Low Distortion IF Amplifi er/ADC Driver with Digitally Controlled Gain

OIP3 = 47dBm at 100MHz, Gain Range 10.5dB to 33dB 1.5dB steps

LT5524 Low Distortion IF Amplifi er/ADC Driver with Digitally Controlled Gain

OIP3 = 40dBm at 100MHz, Gain Range 4.5dB to 37dB 1.5dB steps

LT5554 High Dynamic Range 7-bit Digitally Controlled IF VGA/ADC Driver

OIP3 = 46dBm at 200MHz, Gain Range 1.725 to 17.6dB 0.125dB steps

Baseband Differential Amplifi ers

LT1994 Low Noise, Low Distortion Differential Amplifi er/ADC Driver

16-Bit SNR and SFDR at 1MHz, Rail-to-Rail Outputs

LTC6403-1 Low Noise Rail-to-Rail Output Differential Amplifi er/ADC Driver

16-Bit SNR and SFDR at 3MHz, Rail-to-Rail Outputs, eN = 2.8nV/√Hz

LTC6404-1/LTC6404-2 Low Noise Rail-to-Rail Output Differential Amplifi er/ADC Driver

16-Bit SNR and SFDR at 10MHz, Rail-to-Rail Outputs, eN = 1.5nV/√Hz, LTC6404-1 is unity-gain stable, LTC6404-2 is Gain-of-2 Stable

LTC6406 3GHz Rail-to-Rail Input Differential Amplifi er/ADC Driver

–65dBc IM3 at 50MHz 2VP-P Composite, Rail-to-Rail Inputs, eN = 1.6nV/√Hz, 18mA

LT6411 Low Power Differential ADC Driver/Dual Selectable Gain Amplifi er

–83dBc IM3 at 70MHz 2VP-P Composite, AV = 1, –1 or 2, 16mA, Excellent for Single-Ended to Differential Conversion

DC1257B Simplifi ed Schematic with Suggested Output Termination for Driving an LTC2208 16-Bit ADC at 140MHz

V+

VCM

OUT–

6416 F05

OUT+

3.6V

2.2μF

IN+

CLHI

CLLO

IN–

LTC6416 1pF

1.5pF

1.5pF

3.3V

CLOCK(130MHz)

DATA16

VCM

LTC2208

AIN+

AIN–

25Ω

25ΩGND

GND

R36100Ω

R15100Ω

0.1μF

C390.01μF

3

2

16

4

50Ω

680pF

T1TCM4-19+

+–

ltc6416 - 2 ghz low noise differential 16-bit adc...

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