LTC1922-1

1

TYPICAL APPLICATIO

U

DESCRIPTIO

U

FEATURES

Synchronous PhaseModulated Full-Bridge Controller

LOAD CURRENT (A)0

EFFI

CIEN

CY (%

)

40

1922 • TA01b

10 20 30

100

90

80

70

60

VIN = 36VVIN = 48V

Efficiency

The LTC®1922-1 phase shift PWM controller provides allof the control and protection functions necessary to imple-ment a high performance, zero voltage switched, phaseshift, full-bridge power converter with synchronous recti-fication. The part is ideal for developing isolated, lowvoltage, high current outputs from a high voltage inputsource. The LTC1922-1 combines the benefits of the full-bridge topology with fixed frequency, zero voltage switch-ing operation (ZVS). Adaptive ZVS circuity controls theturn-on signals for each MOSFET independent of internaland external component tolerances for optimal perfor-mance.

The LTC1922-1 also provides secondary side synchro-nous rectifier control. The device uses peak current modecontrol with programmable slope comp and leading edgeblanking.

The LTC1922-1 features extremely low operating andstart-up currents to simplify off-line start-up and biascircuitry. The LTC1922-1 also includes a full range ofprotection features and is available in 20-pin through hole(N) and surface mount (G) packages.

Telecommunications, Infrastructure Power Systems Distributed Power Architectures Server Power Supplies High Density Power Modules

Adaptive DirectSenseTM Zero Voltage Switching Integrated Synchronous Rectification Control for

Highest Efficiency Output Power Levels from 50W to Kilowatts Very Low Start-Up and Quiescent Currents Compatible with Voltage Mode and Current Mode

Topologies Programmable Slope Compensation Undervoltage Lockout Circuitry with 4.2V Hysteresis

and Integrated 10.3V Shunt Regulator Fixed Frequency Operation to 1MHz 50mA Outputs for Bridge Drive and Secondary Side

Synchronous Rectifiers Soft-Start, Cycle-by-Cycle Current Limiting and

Hiccup Mode Short-Circuit Protection 5V, 15mA Low Dropout Regulator 20-Pin PDIP and SSOP Packages

, LTC and LT are registered trademarks of Linear Technology Corporation.DirectSense is a trademark of Linear Technology Corporation.

LTC1922-1

1922 TA01a

ISOLATEDFEEDBACK

VIN48V

VOUT3.3V

BIASSUPPLY

APPLICATIO SU

LTC1922-1

2

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Input Supply

UVLO Undervoltage Lockout Measured on VCC 10.25 10.7 V

UVHY UVLO Hysteresis Measured on VCC 3.8 4.2 V

ICCST Start-Up Current VCC = VUVLO – 0.3V 145 250 µA

ICCRN Operating Current 4 7 mA

VSHUNT Shunt Regulator Voltage Current Into VCC = 10mA 10.2 10.8 V

RSHUNT Shunt Resistance Current Into VCC = 7mA to 17mA –1.5 2 ΩDelay Blocks

DTHR Delay Pin Threshold SBUS = 1.5V 1.38 1.50 1.62 VADLY and PDLY SBUS = 2.25V 2.08 2.25 2.42 V

DHYS Delay Hysteresis Current SBUS = 1.5V, ADLY/PDLY = 1.6V 1.1 1.3 1.45 mAADLY and PDLY

DTMO Delay Time-Out SBUS = 1.5V 600 nsSBUS = 2.25V 900 ns

DZRT Zero Delay Threshold Measured on SBUS 3 4.15 5 V

Phase Modulator

ROS RAMP Offset Voltage Measured on COMP, RAMP = 0V 0.4 V

IRMP RAMP Discharge Current RAMP = 1V, COMP = 0V 30 50 mA

ISLP Slope Compensation Current Measured on CS, CT = 1.5V 35 55 75 µACT = 3V 70 110 150 µA

DCMX Maximum Phase Shift COMP = 4V 95 99.5 %

DCMN Minimum Phase Shift COMP = 0V 0.1 0.6 %

VCC to GNDLow Impedance Source ......................... –0.3V to 10V(Chip Self Regulates at 10.3V)

All Other Pins to GND(Low Impedance Source) ..................... –0.3V to 5.5V

VCC (Current Fed) .................................................. 25mAVREF Output Current ................................ Self RegulatedOutputs (A, B, C, D, E, F) Current ..................... ±100mAOperating Temperature Range (Note 5)

LTC1922E ........................................... –40°C to 85°CLTC1922I ............................................ –40°C to 85°C

Storage Temperature Range ................. –65°C to 125°CLead Temperature (Soldering, 10 sec).................. 300°C

ORDER PARTNUMBER

TJMAX = 125°C, θJA = 110°C/W (G)TJMAX = 125°C,θJA = 62°C/W (N)

LTC1922EG-1LTC1922IG-1LTC1922EN-1LTC1922IN-1

ABSOLUTE AXI U RATI GS

W WW U

PACKAGE/ORDER I FOR ATIOU UW

(Note 1)

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at VCC = 9.5V, CT = 180pF, TA = TMIN to TMAX unless other wise noted.

1

2

3

4

5

6

7

8

9

10

TOP VIEW

G PACKAGE20-LEAD PLASTIC SSOP

20

19

18

17

16

15

14

13

12

11

SYNC

RAMP

CS

COMP

RLEB

FB

SS

PDLY

SBUS

ADLY

CT

GND

OUTA

OUTB

OUTC

VCC

OUTD

OUTE

OUTF

VREF

N PACKAGE20-LEAD PDIP

Consult factory for parts specified with wider operating temperature ranges.

LTC1922-1

3

ELECTRICAL CHARACTERISTICS The denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at VCC = 9.5V, CT = 180pF, TA = TMIN to TMAX unless other wise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Oscillator

OSCT Total Variation VCC = 6.5V to 9.5V 236 277 319 kHz

OSCV CT RAMP Amplitude Measured on CT 3.6 3.85 4.2 V

OSYT SYNC Threshold Measured on SYNC 1.6 1.8 2.2 V

OSYW Minimum SYNC Pulse Width Measured at Outputs (Note 2) 6 ns

OSYWX Maximum SYNC Pulse Width Measured on Outputs, CT = 180pF 1.3 µs

OSOP SYNC Output Pulse Width Measured on SYNC, RSYNC = 5.1k 170 ns

Error Amplifier

VFB FB Input Voltage COMP = 2.5V (Note 3) 1.179 1.204 1.229 V

FBI FB Input Range Measured on FB (Note 4) –0.3 2.5 V

AVOL Open-Loop Gain COMP = 1V to 3V (Note 3) 70 90 dB

IIB Input Bias Current COMP = 2.5V (Note 3) 5 50 nA

VOH Output High Load on COMP = –100µA 4.7 4.92 V

VOL Output Low Load on COMP = 100µA 0.18 0.4 V

ISOURCE Output Source Current COMP = 2.5V – 400 –800 µA

ISINK Output Sink Current COMP = 2.5V 3 7 mA

Reference

VREF Initial Accuracy TA = 25°C, Measured on VREF 4.925 5 5.075 V

REFTV Total Variation Line, Load and Temperature 4.9 5 5.1 V

REFLD Load Regulation Load on VREF = 100µA to 5mA 2 15 mV

REFLN Line Regulation VCC = 6.5V to 9.5V 0.1 10 mV

REFSC Short-Circuit Current VREF Shorted to GND 18 30 45 mA

Outputs

OUTH(X) Output High Voltage IOUT(X) = –50mA 7.9 8.4 V

OUTL(X) Output Low Voltage IOUT(X) = 50mA 0.6 1 V

RHI(X) Pull-Up Resistance IOUT(X) = –50mA to –10mA 22 30 ΩRLO(X) Pull-Down Resistance IOUT(X) = –50mA to –10mA 12 20 Ωtr(X) Rise Time COUT(X) = 50pF 5 15 ns

tf(X) Fall Time COUT(X) = 50pF 5 15 ns

Current Limit and Shutdown

CLPP Pulse-by-Pulse Current Limit Threshold Measured on CS 0.34 0.415 0.48 V

CLSD Shutdown Current Limit Threshold Measured on CS 0.55 0.64 0.73 V

SSI Soft-Start Current SS = 2.5V 7 12 17 µA

SSR Soft-Start Reset Threshold Measured on SS 0.7 0.4 0.1 V

FLT FAULT Reset Threshold Measured on SS 4.4 4.1 3.8 V

Note 1: Absolute Maximum Ratings are those values beyond which the lifeof a device may be impaired.Note 2: SYNC pulse width is valid from >20ns and <0.4 • (1/fOSC),VSYNC = 0V to 5V.Note 3: FB is driven by a servo loop amplifier to control VCOMP for thesetests.

Note 4: Set FB to –0.3V, 2.5 and insure that COMP does not phase invert.Note 5: The LTC1922-1E is guaranteed to meet performance specificationsfrom 0°C to 85°C. Specification over the –40°C to 85°C operatingtemperature range are assured by design, characterization and correlationwith statistical process controls. The LTC1922-1I is guaranteed and testedover the – 40°C to 85°C operating temperature range.

LTC1922-1

4

TYPICAL PERFOR A CE CHARACTERISTICS

UW

VCC (V)0

I CC

(µA)

100

150

8

1922 • G01

50

02 4 6 10

200TA = 25°C

ISHUNT (mA)0

V CC

(V)

10.00

10.25

40

1922 • G02

9.75

9.5010 20 30 50

10.50TA = 25°C

TEMPERATURE (°C)

FREQ

UENC

Y (k

Hz)

260

270

80

1922 • G03

250

240–40–60 –20 200 40 60 100

280CT = 180pF

RLEB (kΩ)0

BLAN

K TI

ME

(ns)

350

300

250

200

150

100

50

0

1922 • G04

40 1002010 30 50 70 9060 80

TA = 25°C

IREF (mA)0

V REF

(V)

5.05

5.00

4.95

4.90

4.85

4.8015 25 40

1922 • G05

5 10 20 30 35

TJ = 25°C

TJ = 85°C

TJ = –40°C

TEMPERATURE (°C)

V REF

(V)

4.99

5.00

80

1922 • G03

4.98

4.97–40–60 –20 200 40 60 100

5.01

Start-Up ICC vs VCC VCC vs ISHUNTOscillator Frequency vsTemperature

Leading Edge Blanking Timevs RLEB VREF vs IREF

VREF vs Temperature Error Amplifier Gain/Phase

FREQUENCY (Hz)

GAIN

(dB)

PHAS

E (D

EG) –180

1M

1922 • G07

–270

–360

10 1k100 10k 100k 10M

100806040200

TA = 25°C

LTC1922-1

5

TEMPERATURE (°C)–55

I CC

(µA)

160

150

140

130

120

110

100

90

80

70

1922 • G10

–25 5 35 95 12565TEMPERATURE (°C)

–55

HYST

ERES

IS C

URRE

NT (m

A)

1922 • G11

–25 5 35 95 12565

1.278

1.276

1.274

1.272

1.270

1.268

1.266

1.264

1.262

1.260

1.258

1.256

SBUS = 1.5V

TEMPERATURE (°C)–55

CURR

ENT

(µA)

130

120

110

100

90

80

70

60

50

40

1922 • G12

–25 5 35 95 12565

CT = 1.5V

CT = 3.0V

TEMPERATURE (°C)–55

10.5

10.4

10.3

10.2

10.1

10.0

9.9

9.8

1922 • G13

–25 5 35 95 12565

SHUN

T VO

LTAG

E (V

)

ICC = 10mA

TEMPERATURE (°C)–55

THRE

SHOL

D (V

)

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1922 • G14

–25 5 35 95 12565

SBUS = 1.5V

SBUS = 2.25V

TEMPERATURE (°C)–55

FB V

OLTA

GE (V

)

1.202

1.201

1.200

1.199

1.198

1.197

1.196

1.195

1.194

1922 • G15

–25 5 35 95 12565TEMPERATURE (°C)

–55

OFFS

ET (m

V)

390

385

380

375

370

365

360

355

350

1922 • G16

–25 5 35 95 12565

TYPICAL PERFOR A CE CHARACTERISTICS

UW

Start-Up ICC vs TemperatureDelay Hysteresis Current vsTemperature Slope Current vs Temperature

VCC Shunt Voltage vs TemperatureDelay Pin Threshold vsTemperature

FB Input Voltage vs TemperatureRamp Offset Voltage vsTemperature

LTC1922-1

6

PIN FUNCTIONS

UUU

SYNC (Pin 1): Synchronization Input/Output for theOscillator. Terminate SYNC with a 5.1k resistor to GND.

RAMP (Pin 2): Input to Phase Modulator Comparator. Thevoltage on RAMP is internally level shifted by 400mV.

CS (Pin 3): Input to Current Limit Comparators, Output ofSlope Compensation Circuitry.

COMP (Pin 4): Error Amplifier Output, Input to PhaseModulator.

RLEB (Pin 5): Timing Resistor for Leading Edge Blanking.Use a 10k to 100k resistor to program from 40ns to 310nsof leading edge blanking. A ±1% tolerance resistor isrecommended. Leading edge blanking may be defeated byconnecting RLEB to VREF.

FB (Pin 6): Error Amplifier Inverting Input. This is thevoltage feedback input for the LTC1922-1.

SS (Pin 7): Soft-Start/Restart Delay Circuitry TimingCapacitor.

PDLY (Pin 8): Passive Leg Delay Circuit Input.

SBUS (Pin 9): Input (Bus) Voltage Sensing Input.

ADLY (Pin 10): Active Leg Delay Circuit Input.

VREF (Pin 11): 5V Reference Output. VREF is capable ofsupplying up to 15mA to external circuitry. Bypass VREFwith a 1µF (minimum) ceramic capacitor to GND.

OUTF (Pin 12): 50mA Driver Output for Secondary SideCurrent Doubler Synchronous Rectifier.

OUTE (Pin 13): 50mA Driver Output for Secondary SideCurrent Doubler Synchronous Rectifier.

OUTD (Pin 14): 50mA Driver Output for Active Leg LowSide.

VCC (Pin 15): Chip Power Supply Input, 10.3V ShuntRegulator. Bypass VCC with a 0.1µF or larger ceramiccapacitor to GND.

OUTC (Pin 16): 50mA Driver Output for Active Leg HighSide.

OUTB (Pin 17): 50mA Driver Output for Passive Leg LowSide.

OUTA (Pin 18): 50mA Driver Output for Passive Leg HighSide.

GND (Pin 19): All Voltages on the LTC1922-1 Are Referredto GND.

CT (Pin 20): Timing Capacitor for Oscillator. Use ±5% orbetter multilayer NPO ceramic for best results.

LTC1922-1

7

BLOCK DIAGRA

W

UVLOSHUNT REG10.25V “ON”

6V “0FF”

REF AND LDO

SLOPECOMPENSATION

CT/R

13

6

4

15 11 20 1 9

2

7

3

5

12

19

+

–

18

17

8

10

16

14

PASSIVEDELAY

SYNCRECTIFIER

DRIVELOGIC

ACTIVEDELAY

BLANK

FAULTLOGIC

+

–

+

–

+

–

+

–

12µA

VREF

BLANK

400mV

600mV

PULSE BY PULSECURRENT LIMIT

R

S

R

S

TQ

QB

QB

Q

QB

SHUTDOWNCURRENT LIMIT

0.4V

ERRORAMPLIFIER

PHASEMODULATOR

OSC

1.2V

1.2V

5V

VCC VREF CT SYNC SBUS

50k

14.9k

FB

COMP

RAMP

SS

RLEB

CS

GND

PDLY

OUTA

OUTB

OUTE

OUTF

OUTC

OUTD

ADLY

1922 • BD

OUTA

OUTB

OUTC

OUTD

RAMP

COMP

OUTE

OUTF

CURRENT DOUBLER

ACTIVE DELAYPASSIVE DELAY

1922 TDNOTE: SHADED AREAS CORRESPOND TO POWER DELIVERY PULSES

TI I G DIAGRAUW W

LTC1922-1

8

OPERATIOU

Phase Shift Full-Bridge PWM

Conventional full-bridge switching power supply topolo-gies are often employed for high power, isolated DC/DCand off-line converters. Although they require two addi-tional switching elements, substantially greater power andhigher efficiency can be attained for a given transformersize compared to the more common single-ended forwardand flyback converters. These improvements are realizedsince the full-bridge converter delivers power during bothparts of the switching cycle, reducing transformer coreloss and lowering voltage and current stresses. The full-bridge converter also provides inherent automatic trans-former flux reset and balancing due to its bidirectionaldrive configuration. As a result, the maximum duty cyclerange is extended, further improving efficiency. Soft switch-ing variations on the full-bridge topology have been pro-posed to improve and extend its performance andapplication. These zero voltage switching (ZVS) tech-niques exploit the generally undesirable parasitic ele-ments present within the power stage. The parasiticelements are utilized to drive near lossless switchingtransitions for all of the external power MOSFETs.

LTC1922-1 phase shift PWM controller provides enhancedperformance and simplifies the design task required for aZVS phase shifted full-bridge converter. The primaryattributes of the LTC1922-1 as compared to currentlyavailable solutions include:

1) Truly adaptive and accurate (DirectSense technology)ZVS switching delays.

Benefit: higher efficiency, higher duty cycle capability,eliminates external trim.

2) Internally generated drive signals for current doublersynchronous rectifiers.

Benefit: eliminates external glue logic, drivers, optimaltiming for highest efficiency.

3) Programmable (single resistor) leading edge blanking.

Benefit: prevents spurious operation, reduces externalfiltering required on CS.

4) Programmable (single resistor) slope compensation.

Benefit: eliminates external glue circuitry.

5) Optimized current mode control architecture.

Benefit: eliminates glue circuitry, less overshoot at start-up, faster recovery from system faults.

6) Proven reference circuits and design tools.

Benefit: substantially reduced learning curve, more timefor optimization.

As a result, the LTC1922-1 makes the ZVS topologyfeasible for a wider variety of applications, including thoseat lower power levels.

The LTC1922-1 controls four external power switches ina full-bridge arrangement. The load on the bridge is theprimary winding of a power transformer. The diagonalswitches in the bridge connect the primary winding be-tween the input voltage and ground every oscillator cycle.The pair of switches that conduct are alternated by aninternal flip-flop in the LTC1922-1. Thus, the voltageapplied to the primary is reversed in polarity on everyswitching cycle and each output drive signal is 1/2 thefrequency of the oscillator. The on-time of each driversignal is slightly less that 50%. The actual percentage isadaptively modulated by the LTC1922-1. The on-timeoverlap of the diagonal switch pairs is controlled by theLTC1922-1 phase modulation circuitry. (Refer to Blockand Timing Diagrams) This overlap sets the approximateduty cycle of the converter. The LTC1922-1 driver outputsignals (OUTA to OUTF) are optimized for interface with anexternal gate driver IC or buffer. External power MOSFETsA and C require high side driver circuitry, while B and D areground referenced and E and F are ground referenced buton the secondary side of the isolation barrier. Methods forproviding drive to these elements are detailed in the datasheet. The secondary voltage of the transformer is theprimary voltage divided by the transformer turns ratio.Similar to a buck converter, the secondary square wave isapplied to an output filter inductor and capacitor to pro-duce a well regulated DC output voltage.

Switching Transitions

The phase shifted full-bridge can be described by fourprimary operating states. The key to understanding howZVS occurs is revealed by examining the states in detail.

LTC1922-1

9

OPERATIOU

Each full cycle of the transformer has two distinct periodsin which power is delivered to the output, and two “free-wheeling” periods. The two sides of the external bridgehave fundamentally different operating characteristics thatbecome important when designing for ZVS over a wideload current range. The left bridge leg is referred to as the“passive” leg, while the right leg is referred to as the“active” leg. The following descriptions provide insight asto why these differences exist.

State 1 (Power Pulse 1)

Referring to Figure 1, State 1 begins with MA, MD and MF“ON” and MB, MC and ME “OFF.” During the simultaneousconduction of MA and MD, the full input voltage is appliedacross the transformer primary winding and following thedot convention, VIN/N is applied to the left side of LO1allowing current to increase in LO1. The primary currentduring this period is approximately equal to the outputinductor current (LO1) divided by the transformer turnsratio plus the transformer magnetizing current (VIN • tON/LMAG). MD turns off and ME turns on at the end of State 1.

State 2 (Active Transition and Freewheel Interval)

MD turns off when the phase modulator comparatortransitions. At this instant, the voltage on the MD/MCjunction begins to rise towards the applied input voltage(VIN). The transformer’s magnetizing current and thereflected output inductor current propels this action. Theslew rate is limited by MOSFET MC and MD’s outputcapacitance (COSS), snubbing capacitance and the trans-former interwinding capacitance. The voltage transitionon the active leg from the ground reference point to VIN willalways occur, independent of load current as long asenergy in the transformer’s magnetizing and leakage in-ductance is greater than the capacitive energy. That is,1/2 • (LM + LI) • IM2 > 1/2 • 2 • COSS • VIN

2 — the worst caseoccurs when the load current is zero. This condition isusually easy to meet. The magnetizing current is virtuallyconstant during this transition because the magnetizinginductance has positive voltage applied across it through-out the low to high transition. Since the leg is activelydriven by this “current source,” it is called the active orlinear transition. When the voltage on the active leg has

risen to VIN, MOSFET MC is switched on by the LTC1922-1 DirectSense circuitry. The primary current now flowsthrough the two high side MOSFETs (MA and MC). Thetransformer’s secondary windings are electrically shortedat this time since both ME and MF are “ON”. As long aspositive current flows in LO1 and LO2, the transformerprimary (magnetizing) inductance is also shorted throughnormal transformer action. MA and MF turn off at the endof State 2.

State 3 (Passive Transition)

MA turns off when the oscillator timing period ends, i.e.,the clock pulse toggles the internal flip-flop. At the instantMA turns off, the voltage on the MA/MB junction begins todecay towards the lower supply (GND). The energy avail-able to drive this transition is limited to the primary leakageinductance and added commutating inductance whichhave (IMAG + IOUT/2N) flowing through them initially. Themagnetizing and output inductors don’t contribute anyenergy because they are effectively shorted as mentionedpreviously, significantly reducing the available energy.This is the major difference between the active and passivetransitions. If the energy stored in the leakage and com-mutating inductance is greater than the capacitive energy,the transition will be completed successfully. During thetransition, an increasing reverse voltage is applied to theleakage and commutating inductances, helping the overallprimary current to decay. The inductive energy is thusresonantly transferred to the capacitive elements, hence,the term passive or resonant transition. Assuming there issufficient inductive energy to propel the bridge leg toGND, the time required will be approximately equal toπ • √LC/2. When the voltage on the passive leg nears GND,MOSFET MB is commanded “ON” by the LTC1922-1DirectSense circuitry. Current continues to increase in theleakage and external series inductance which is oppositein polarity to the reflected output inductor current. Whenthis current is equal in magnitude to the reflected outputcurrent, the primary current reverses direction, the oppo-site secondary winding becomes forward biased and anew power pulse is initiated. The time required for thecurrent reversal reduces the effective maximum duty cycle

LTC1922-1

10

OPERATIOU

.and must be considered when specifying the power trans-former. If ZVS is required over the entire range of loads, asmall commutating inductor is added in series with theprimary to aid with the passive leg transition, since theleakage inductance alone is usually not sufficient andpredictable enough to guarantee ZVS over the full loadrange.

Figure 1. ZVS Operation

State 4 (Power Pulse 2)

During power pulse 2, current builds up in the primarywinding in the opposite direction as power pulse 1. Theprimary current consists of reflected output inductorcurrent and current due to the primary magnetizing induc-tance. At the end of State 4, MOSFET MC turns off and anactive transition, essentially similar to State 2, but oppo-site in direction (high to low) takes place.

State 1. POWER PULSE 1VIN

MA

MBMF

MC

MDME

MF ME

MF ME

FREEWHEELINTERVAL

MA

MB

MC

MD

State 2. ACTIVETRANSITION

MA

MB

MC

MD

State 3. PASSIVE TRANSITION

MA

MB

MC

MD

State 4. POWER PULSE 2

MA

MB

MC

MD

LOAD

LOAD

LOAD

VOUT

VOUT

L1

L2N:1

PRIMARY ANDSECONDARY SHORTED

VOUT

1922 F01

IP ≈ IL01/N + (VIN • TOVL)/LMAG

+

+

LTC1922-1

11

OPERATIOU

Adaptive Mode

The LTC1922-1 is configured for adaptive delay sensingwith three pins, ADLY, PDLY and SBUS. ADLY and PDLYsense the active and passive delay legs respectively via avoltage divider network as shown in Figure 2.

Zero Voltage Switching (ZVS)

A lossless switching transition requires that the respectivefull-bridge MOSFETs be switched to the “ON” state at theexact instant their drain to source voltage is zero. Delayingthe turn-on results in lower efficiency due to circulatingcurrent flowing in the body diode of the primary sideMOSFET rather than its low resistance channel. Prematureturn-on produces hard switching of the MOSFETs, in-creasing noise and power dissipation. Previous solutionshave attempted to meet these requirements with fixed orfirst order (linear) variable open-loop time delays. Open-loop methods typically set the turn-on delay to the worstcase longest bridge transition time expected plus thetolerances of all the internal and external delay timingcircuitry. These error tolerances can be quite significant,while the optimal transition times over the load currentrange vary nonlinearly. In a volume production environ-ment, these factors can necessitate an external trim toguarantee ZVS operation, adding cost to the final product.An additional side effect of longer than required delays isa decrease in the effective maximum duty cycle. Reducedduty cycle range can mandate a lower transformer turnsratio, impacting efficiency or requiring a lower switchingfrequency, impacting size.

LTC1922-1 Adaptive Delay Circuitry

The LTC1922-1 addresses the issue of nonideal switchingdelays with novel DirectSense circuitry that intelligentlymonitors both the input supply and instantaneous bridgeleg voltages, and commands a switching transition whenthe expected zero voltage condition is reached. In effect,the LTC1922-1 “closes the loop” on the ZVS turn-on delayrequirements. DirectSense technology provides optimalturn-on delay timing, regardless of input voltage, outputload, or component tolerances and greatly simplifies thepower supply design process. The DirectSense techniquerequires only a simple voltage divider sense network toimplement. If there is not enough energy to fully commu-tate the bridge leg to a ZVS condition, the LTC1922-1automatically overrides the DirectSense circuitry and forcesa transition. The LTC1922-1 delay circuitry can also beoverridden, by tying SBUS to VREF.

SBUS ADLY

PDLY

R2

R5 R6

R1 R31k

R41k

RCS

A

B

C

D

VIN

1922 F02

Figure 2. Adaptive Mode

The threshold voltage on PDLY and ADLY for both therising and falling transitions is set by the voltage on SBUS.A buffered version of this voltage is used as the thresholdlevel for the internal DirectSense circuitry. At nominal VIN,the voltage on SBUS is set to 1.5V by an external voltagedivider between VIN and GND, making this voltage directlyproportional to VIN. The LTC1922-1 DirectSense circuitryuses this characteristic to zero voltage switch all of theexternal power MOSFETs, independent of input voltage.

ADLY and PDLY are connected through voltage dividers tothe active and passive bridge legs respectively. The lowerresistor in the divider is set to 1k. The upper resistor in thedivider is divided into one, two or three equal valueresistors to reduce its overall capacitance. In off-lineapplications, this is usually required anyway to stay withinthe maximum voltage ratings of the resistors. One or tworesistor segments will work for most nominal 48V or lowerVIN applications.

To set up the ADLY and PDLY resistors, first determine atwhat drain to source voltage to turn-on the MOSFETs.Finite delays exist between the time at which the LTC1922-1controller output transitions, to the time at which thepower MOSFET switches on due to MOSFET turn on delayand external driver circuit delay. Ideally, we want thepower MOSFET to switch at the instant there is zero voltsacross it. By setting a threshold voltage for ADLY and

LTC1922-1

12

PDLY corresponding to several volts across the MOSFET,the LTC1922-1 can “anticipate” a zero voltage VDS andsignal the external driver and switch to turn-on. Theamount of anticipation can be tailored for any applicationby modifying the upper divider resistor(s). The LTC1922-1DirectSense circuitry sources a trimmed current out ofPDLY and ADLY after a low to high level transition occurs.This provides hysteresis and noise immunity for the PDLYand ADLY circuitry, and sets the high to low threshold onADLY or PDLY to nearly the same level as the low to highthreshold, thereby making the upper and lower MOSFETVDS switch points virtually identical, independent of VIN.

Example: VIN = 48V nominal (36V to 72V)

1. Set up SBUS: 1.5V is desired on SBUS with VIN = 48V.Set divider current to 100µA.

R1 = 1.5V/100µA = 15k.

R2 = (48V – 1.5V)/100µA = 465k.

An optional small capacitor (0.001µF) can be addedacross R1 to decouple noise from this input.

2. Set up ADLY and PDLY: 7V of “anticipation” are requiredin this circuit to account for the delays of the externalMOSFET driver and gate drive components.

R3, R4 = 1k, sets a nominal 1.5mA in the dividerchain at the threshold.

R5, R6 = (48V – 7V – 1.5V)/1.5mA = 26.3k,use (2) equal 13k segments.

Zero Delay Mode

The LTC1922-1 provides the flexibility through the SBUSpin to disable the DirectSense delay circuitry. See Figure 3for details.

OPERATIOU

to VCC as well as signaling that the chip’s bias voltage issufficient to begin switching operation (under voltagelockout). With its typical 10.2V turn-on voltage and 4.2VUVLO hysteresis, the LTC1922-1 is tolerant of looselyregulated input sources such as an auxiliary transformerwinding. The VCC shunt is capable of sinking up to 25mAof externally applied current. The UVLO turn-on and turn-off thresholds are derived from an internally trimmedreference making them extremely accurate. In addition,the LTC1922-1 exhibits very low (145µA typ) start-upcurrent that allows the use of 1/8W to 1/4W trickle chargestart-up resistors.

The trickle charge resistor should be selected as follows:

RSTART(MAX) = VIN(MIN) – 10.7V/250µA

Adding a small safety margin and choosing standardvalues yields:

APPLICATION VIN RANGE RSTART

DC/DC 36V to 72V 100k

Off-Line 85V to 270VRMS 430k

PFC Preregulator 390VDC 1.4M

VCC should be bypassed with a 0.1µF to 1µF multilayerceramic capacitor to decouple the fast transient currentsdemanded by the output drivers and a bulk tantalum orelectrolytic capacitor to hold up the VCC supply before thebootstrap winding, or an auxiliary regulator circuit takesover.

CHOLDUP = (ICC + IDRIVE) • tDELAY/3.8V(minimum UVLO hysteresis)

Regulated bias supplies as low as 7V can be utilized toprovide bias to the LTC1922-1. Refer to Figure 4 forvarious bias supply configurations.

ADLY

PDLY

VREF

SBUS

1922 F03

Figure 3. Zero Delays

Figure 4. Bias Configurations

Powering the LTC1922-1

The LTC1922-1 utilizes an integrated VCC shunt regulatorto serve the dual purposes of limiting the voltage applied

1922 F04

12V ±10%

1.5k

VCC

VIN

VCC

CHOLD

1N52263V

0.1µF 0.1µF

VBIAS < VUVLO

RSTART1N914

+

LTC1922-1

13

OPERATIOU

Off-Line Bias Supply Generation

If a regulated bias supply is not available to provide VCCvoltage to the LTC1922-1 and supporting circuitry, onemust be generated. Since the power requirement is small,approximately 1W, and the regulation is not critical, asimple open-loop method is usually the easiest and lowestcost approach. One method that works well is to add awinding to the main power transformer, and post regulatethe resultant square wave with an L-C filter (see Figure 5a).The advantage of this approach is that it maintains decentregulation as the supply voltage varies, and it does notrequire full safety isolation from the input winding of thetransformer. Some manufacturers include a primary wind-ing for this purpose in their standard product offerings aswell. A different approach is to add a winding to the outputinductor and peak detect and filter the square wave signal(see Figure 5b). The polarity of this winding is designed sothat the positive voltage square wave is produced while theoutput inductor is freewheeling. An advantage of thistechnique over the previous is that it does not require aseparate filter inductor and since the voltage is derivedfrom the well-regulated output voltage, it is also wellcontrolled. One disadvantage is that this winding willrequire the same safety isolation that is required for themain transformer. Another disadvantage is that a muchlarger VCC filter capacitor is needed, since it does not

generate a voltage as the output is first starting up, orduring short-circuit conditions.

Programming the LTC1922-1 Oscillator

The high accuracy LTC1922-1 oscillator circuit providesflexibility to program the switching frequency, slope com-pensation, and synchronization with minimal externalcomponents. The LTC1922-1 oscillator circuitry producesa 3.8V peak-to-peak amplitude ramp waveform on CT anda narrow pulse on SYNC that can be used to synchronizeother PWM chips. Typical maximum duty cycles of 99%are obtained at 300kHz and 97% at 1MHz. The largeamplitude ramp provides a high degree of noise margin. Acompensating slope current is derived from the oscillatorramp waveform and sourced out of CS.

The desired amount of slope compensation is selectedwith single external resistor (or no resistor), if not re-quired. A capacitor to GND on CT programs the switchingfrequency. The CT ramp discharge current is internally setto a high value (>10mA). The dedicated SYNC I/O pin easilyachieves synchronization. The LTC1922-1 can be set up toeither synchronize other PWM chips or be synchronizedby another chip or external clock source. The 1.8V SYNCthreshold allows the LTC1922-1 to be synchronized di-rectly from all standard 3V and 5V logic families.

Design Procedure:

1. Choose CT for the desired oscillator frequency. Theswitching frequency selected must be consistent with thepower magnetics and output power level. This is detailedin the Transformer Design section. In general, increasingthe switching frequency will decrease the maximum achiev-able output power, due to limitations of maximum dutycycle imposed by transformer core reset and ZVS. Re-member that the output frequency is 1/2 that of theoscillator.

CT = 1/(20k • fOSC)

Example: Desired fOSC = 330kHz

CT = 1/(20k • 330kHz) = 152pF, choose closest standardvalue of 150pF. A 5% or better tolerance multilayer NPOor X7R ceramic capacitor is recommended for bestperformance.

1922 F05bVCC

VOUT

VIN

CHOLD

RSTART +

0.1µF

LOUT

ISO BARRIER

Figure 5a. Auxiliary Winding Bias Supply

Figure 5b. Output Inductor Bias Supply

1922 F05a

+

VCCVIN

CHOLD 0.1µF

RSTART

2k15V*

*OPTIONAL

LTC1922-1

14

3. Slope compensation is required for most peak currentmode controllers in order to prevent subharmonic oscilla-tion of the current control loop. In general, if the systemduty cycle exceeds 50% in a fixed frequency, continuouscurrent mode converter, an unstable condition existswithin the current control loop. Any perturbation in thecurrent signal is amplified by the PWM modulator result-ing in an unstable condition. Some common manifesta-tions of this include alternate pulse nonuniformity andpulse width jitter. Fortunately, this can be addressed byadding a corrective slope to the current sense signal or bysubtracting the same slope from the current commandsignal (error amplifier output). In theory, the currentdoubler output configuration does not require slope com-pensation since the output inductor duty cycles onlyapproach 50%. However, transient conditions can mo-mentarily cause higher duty cycles and therefore, thepossibility for unstable operation. The exact amount ofrequired slope compensation is easily programmed by theLTC1922-1 with the addition of a single external resistor(see Figure 7). The LTC1922-1 generates a current that isproportional to the instantaneous voltage on CT,

OPERATIOU

(33µA/V(CT)). Thus, at the peak of CT, this current isapproximately 125µA and is output from the CS pin. Aresistor connected between CS and the external currentsense resistor sums in the required amount of slopecompensation. The value of this resistor is dependent onseveral factors including minimum VIN, VOUT, switchingfrequency, current sense resistor value and output induc-tor value. An illustrative example with the design equationis provided below.

Example: VIN = 36V to 72V

VOUT = 3.3V

IOUT = 40A

L = 2.2µH

Transformer turns ratio (N) = VIN(MIN) • DMAX/VOUT = 3

RCS = 0.025Ω

fSW = 300kHz, i.e., transformer f = fSW/2 = 150kHz

RSLOPE = VO • RCS/(2 • L • fT • 125µA • N) = 3.3V • 0.025/(2 • 2.2µA • 100k • 125µA • 3)

RSLOPE = 500Ω, choose the next higher standard valueto account for tolerances in ISLOPE, RCS, N and L.

LTC1922-1

LTC1922-1

LTC1922-1CT

CT

CT

CT

CT

CT

SYNC

SYNC

SYNC

5.1k

5.1k

5.1k

1k

1k

•••

UP TO 5 SLAVES

SLAVES

MASTER

CT OF SLAVE(S) IS 1.25 CT OF MASTER.

1922 F06a

LTC1922-1CT

CT

SYNC

5.1k

1k

1922 F06b

EXTERNALFREQUENCY

SOURCE

AMPLITUDE > 1.8V12.5ns < PW < 0.4/ƒ

Figure 6a. SYNC Output (Master Mode)

Figure 6b. SYNC Input from an External Source

Figure 7. Slope Compensation Circuitry

2. The LTC1922-1 can either synchronize other PWMs, orbe synchronized to an external frequency source or PWMchip. See Figure 6 for details.

Current Sensing and Overcurrent Protection

Current sensing provides feedback for the current modecontrol loop and protection from overload conditions. TheLTC1922-1 is compatible with either resistive sensing orcurrent transformer methods. Internally connected to theLTC1922-1 CS pin are two comparators that providepulse-by-pulse and overcurrent shutdown functions re-spectively. (See Figure 8)

BRIDGECURRENT

CURRENT SENSEWAVEFORM

V(CT)33k

I = CSCT

33kADDEDSLOPE

RSLOPE

RCS

1922 F07

LTC1922-1

LTC1922-1

15

The pulse-by-pulse comparator has a 400mV nominalthreshold, which can reduce sense resistor losses by 67%compared to previous solutions. This corresponds to 3Win a 200W, 48V to 3.3V converter. If the 400mV thresholdis exceeded, the PWM cycle is terminated. The overcurrentcomparator is set approximately 50% higher than thepulse-by-pulse level. If the current signal exceeds thislevel, the PWM cycle is terminated, the soft-start capacitoris quickly discharged and a soft-start cycle is initiated. Ifthe overcurrent condition persists, the LTC1922-1 haltsPWM operation and waits for the soft-start capacitor tocharge up to approximately 4V before a retry is allowed.The soft-start capacitor is charged by an internal 12µAcurrent source. If the fault condition has not cleared whensoft-start reaches 4V, the soft-start pin is again dis-charged and a new cycle is initiated. This is referred to ashiccup mode operation. In normal operation and undermost abnormal conditions, the pulse-by-pulse compara-tor is fast enough to prevent hiccup mode operation. Insevere cases, however, with high input voltage, very lowRDS(ON) MOSFETs and a shorted output, or with saturat-ing magnetics, the overcurrent comparator provides ameans of protecting the power converter.

Leading Edge Blanking

The LTC1922-1 provides programmable leading edgeblanking to prevent nuisance tripping of the current sense

circuitry. Although the ZVS full-bridge topology is some-what more immune to leading edge noise spikes thanother types of converters, they are not totally eliminated.Leading edge blanking relieves the filtering requirementsfor the CS pin, greatly improving the response to realovercurrent conditions. It also allows the use of a groundreferenced current sense resistor or transformer(s), fur-ther simplifying the design. With a single 10k to 100kresistor from RLEB to GND, blanking times of approxi-mately 40ns to 320ns are programmed. If not required,connecting RLEB to VREF can disable leading edge blank-ing. Keep in mind that the use of leading edge blanking willset a minimum linear control range for the phase modula-tion circuitry.

Resistive Sensing

A resistor connected between input common and thesources of MB and MD is the simplest, fastest and mostaccurate method of current sensing for the full-bridgeconverter. This is the preferred method for low to moder-ate power levels. A graph of resistive sense power lossesvs output power is shown Figure 9. The sense resistorshould be chosen such that the maximum rated outputcurrent for the converter can be delivered at the lowestexpected VIN. Use the following formula to calculate theoptimal value for RCS.

+

–

+

–

OVERLOADCURRENT LIMIT

400mV

600mV

φMOD

UVLOENABLE

UVLOENABLE

R

S Q

R

S Q

Q

QS

Q PWMLOGIC

H = SHUTDOWNOUTPUTS

CS

RCS

+

–

+

–

CSS

SS

0.4V

4.1V 12µA

1922 F08

PULSE BY PULSECURRENT LIMIT

PWMLATCH

Figure 8. Current Sense/Fault Circuitry Detail

OPERATIOU

LTC1922-1

16

If RAMP and CS are connected together:

RV A R

I PEAKCS

SLOPE

P= µ0 4 125. – ( • )

( )

I PEAKI

N EFF

V D

L fV D

L f N

PO MAX IN MAX MIN

MAG CLK

O MIN

OUT CLK

( )• •

• •

•( – )

• •

( ) ( )= + +2

2

1

where: N = Transformer turns ratio

If RAMP and CS are separated

RV

I PEAKCS

P= 0 4.

( )

Current Transformer Sensing

A current sense transformer can be used in lieu of resistivesensing with the LTC1922-1. Current sense transformersare available in many styles from several manufacturers.A typical sense transformer for this application will use a1:50 turns ratio (N), so that the sense resistor value is Ntimes larger, and the secondary current N times smallerthan in the resistive sense case. Therefore, the senseresistor power loss is about N times less with the trans-former method, neglecting the transformers core andcopper losses. The disadvantages of this approach

include, higher cost and complexity, lower accuracy, corereset/max duty cycle limitations and lower speed. Never-theless, for very high power applications, this method ispreferred. The sense transformer primary is placed in thesame location as the ground referenced sense resistor, orbetween the upper MOSFET drains in the (MA, MC) andVIN. The advantage of the high side location is a greaterimmunity to leading edge noise spikes, since gate chargecurrent and reflected rectifier recovery current are largelyeliminated. Figure 10 illustrates a typical current sensetransformer based sensing scheme. RS in this case iscalculated the same as in the resistive case, only its valueis increased by the sense transformer turns ratio. At highduty cycles, it may become difficult or impossible to resetthe current transformer. This is because the requiredtransformer reset voltage increases as the available timefor reset decreases to equalize the (volt • seconds) applied.The interwinding capacitance and secondary inductanceof the current sense transformer form a resonant circuitthat limits the dV/dT on the secondary of the CS trans-former. This in turn limits the maximum achievable dutycycle for the CS transformer. Attempts to operate beyondthis limit will cause the transformer core to “walk” andeventually saturate, opening up the current feedback loop.

Common methods to address this limitation include:

1. Reducing the maximum duty cycle by lowering thepower transformer turns ratio.

2. Reducing the switching frequency of the converter.

3. Employ external active reset circuitry.

4. Using two CS transformers summed together.

5. Choose a CS transformer optimized for high frequencyapplications.

OUTPUT CURRENT (A)0

POW

ER L

OSS

(W)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

010 20 25

1922 • F09

5 15 30 35 40

RS = 0.025VIN = 48VVO = 3.3VLO = 2.2µH

Figure 9. RSENSE Power Loss vs IOUT

OPTIONALFILTERING

N:1

MBSOURCE

MDSOURCE

CURRENTTRANSFORMER

RSLOPERAMP

CS

RS

1922 F10

Figure 10. Current Transformer Sense Circuitry

OPERATIOU

LTC1922-1

17

Phase Modulator

The LTC1922-1 phase modulation control circuitry iscomprised of the phase modulation comparator and logic,the error amplifier, and the soft-start amplifier (seeFigure 11). Together, these elements develop the requiredphase overlap (duty cycle) required to keep the outputvoltage in regulation. In isolated applications, the sensedoutput voltage error signal is fed back to COMP across theinput to output isolation boundary by an optical couplerand shunt reference/error amplifier (LT®1431) combina-tion. The FB pin is connected to GND, forcing COMP high.The collector of the optoisolator is connected to COMPdirectly. The voltage COMP is internally attenuated by theLTC1922-1. The attenuated COMP voltage provides oneinput to the phase modulation comparator. This is thecurrent command. The other input to the phase modula-tion comparator is the RAMP voltage, level shifted byapproximately 400mV. This is the current loop feedback.During every switching cycle, alternate diagonal switches

(MA-MD or MB-MC) conduct and cause current in anoutput inductor to increase. This current is seen on theprimary of the power transformer divided by the turnsratio. Since the current sense resistor is connectedbetween GND and the two bottom bridge transistors, avoltage proportional to the output inductor current will beseen across RSENSE. The high side of RSENSE is alsoconnected to RAMP and CS, usually through a smallresistor (RSLOPE). When the voltage on RAMP/CS exceedseither COMP/5.2 –400mV, or 400mv, the overlap conduc-tion period will terminate. During normal operation, theattenuated COMP voltage will determine the RAMP/CS trippoint. During start-up, or slewing conditions following alarge load step, the 400mV CS threshold will terminate thecycle, as COMP will be driven high, such that the attenu-ated version exceeds the 400mV threshold. In extremeconditions, the 600mV threshold on CS will be exceeded,invoking a soft-start/restart cycle.

400mV12µA

1922 F11

R

S Q

R

SQ

+

–

+

–

+

–

+

–

Q

Q

C

B

D

ACLK

CLK

CLK

1.2V

VREF

SOFT-STARTAMPLIFIER

ERRORAMPLIFIER

TOGGLEF/F

PHASEMODULATION

LOGIC

PHASEMODULATIONCOMPARATOR

FROMCURRENTLIMITCOMPARATOR

BLANKING

FB

COMP

SS

RLEB

RAMP

14.9k

50k

Figure 11. Phase Modulation Circuitry

OPERATIOU

LTC1922-1

18

Selecting the Power Stage Components

Perhaps the most critical part of the overall design of theconverter is selecting the power MOSFETs, transformer,inductors and filter capacitors. Tremendous gains in effi-ciency, transient performance and overall operation canbe obtained as long as a few simple guidelines are followedwith the phase shifted full-bridge topology.

Power Transformer

This guide is aimed at selecting readily available standard“off the shelf” transformers. The basic requirements,however, apply to custom transformer designs as well.Switching frequency, core material characteristics, seriesresistance and input/output voltages all play an importantrole in transformer selection. Close attention also needs tobe paid to leakage and magnetizing inductances as theyplay an important role in how well the converter willachieve ZVS. Planar magnetics are very well suited tothese applications because of their excellent control ofthese parameters.

Turns Ratio

The required turns ratio for a current doubler secondary isgiven below. Depending on the magnetics selected, thisvalue may need to be reduced slightly.

Turns ratio formula:

NV D

VIN MIN MAX

OUT= 2 •

•( )

where:

VIN(MIN) = Minimum VIN for operation

DMAX = Maximum duty cycle of controller

Magnetizing, Output, and Leakage Inductors

A lower value of magnetizing and output inductance willimprove the ability of the converter to achieve ZVS over thefull range of loads and reduce the size of the externalcommutating inductor. One of the trade-offs is increasedprimary referred ripple current which has a small negative

impact on efficiency. Other factors to consider are switch-ing frequency and required maximum duty cycle. A lowervalue of magnetizing inductance will require a longer timeto reset the core, cutting into the available duty cyclerange. As switching frequencies increase, this becomesmore significant. In general, the magnetizing inductancevalue should be the lowest value required in order toachieve the necessary maximum duty cycle at the chosenswitching frequency. Output inductor value determinesthe magnitude of output ripple current and therefore theripple voltage along with the output capacitors. Generallyspeaking, the output inductance should be minimized asmuch as possible in order to improve transient response.In addition, output capacitance ESR should be minimizedas much as possible. Using the equations below, plug inthe manufacturers magnetizing inductance value and a“starting value” of commutating inductance (1% of LMAG)to verify that a sufficient max duty cycle can be achievedat the desired switching frequency. Next, use equation (2)to determine what the absolute minimum required LCOM isto guarantee ZVT over the entire load range. One or twoiterations may be required in order to arrive at the finalselections.

MAX DC vs LCOM at fSW

MAX DCf TSW R≥

22

– •;

(1)

where:

TR = transformer reset time (worst case)

=+ +

I f L V D N

f L NL L

VO MAX SW MAG IN

SW MAG

COM L

IN

( ) • • • • •

• •

2

LCOM vs ZVS vs Load

L LC L f

DCOM L

OSS MAG SW+ =4 3

2

2 2

2

/ • •

•(2)

OPERATIOU

LTC1922-1

19

where:COSS = MOSFET D-S capacitancelMAG = magnetizing inductancefSW = switching frequencyD = duty cycleLL = leakage inductance

For a 48V to 3.3V/5V, 200W converter, the followingvalues were derived:

fSW : 300kHzLMAG : 100µHLCOM : 0.9µHLOUT : 2.2µH

Turns Ratio (N) = 2.5

Output Capacitors

Output capacitor selection has a dramatic impact on ripplevoltage, dynamic response to transients and stability.Capacitor ESR along with output inductor ripple currentwill determine the peak-to-peak voltage ripple on theoutput. The current doubler configuration is advanta-geous because it has inherent ripple current reduction.The dual output inductors deliver current to the outputcapacitor 180 degrees out of phase, in effect, partiallycanceling each other’s ripple current. This reduction ismaximized at high duty cycle and decreases as the dutycycle reduces. This means that a current doubler con-verter requires less output capacitance for the sameperformance as a conventional converter. By determiningthe minimum duty cycle for the converter, worse-caseVOUT ripple can be derived by the formula given below.

V I ESRV ESR

L fD DORIPPLE RIPPLE

O

O SW= =•

•• •

( – )( – )2

1 1 2

where:

D = minimum duty cycle

fSW = oscillator frequency

LO = output inductance

ESR = output capacitor series resistance

The amount of bulk capacitance required is usually systemdependent, but has some relationship to output induc-tance value, switching frequency, load power and dynamicload characteristics. Polymer electrolytic capacitors arethe preferred choice for their combination of low ESR,small size and high reliability. For less demanding applica-tions, or those not constrained by size, aluminum electro-lytic capacitors are commonly applied. MostDC/DC converters in the 100kHz to 300kHz range use 20µFto 25µF of bulk capacitance per watt of output power.Converters switching at higher frequencies can usuallyuse less bulk capacitance. In systems where dynamicresponse is critical, additional high frequency capacitors,such as ceramics, can substantially reduce voltage tran-sients,

Power converter stability is, to a large extent, determinedby the choice of output capacitor. A zero in the converter’stransfer function is given by 1/(2π • ESR • CO). Aluminumelectrolytic ESR is highly variable with temperature, in-creasing by about 4× at cold temperatures, making theESR zero frequency highly variable. Polymer electrolyticESR is essentially flat with temperature. This characteris-tic simplifies loop compensation and allows for a muchfaster responding power supply compared to one withaluminum electrolytic capacitors. Specific details on loopcompensation are given in the Compensation section ofthe data sheet.

Power MOSFETs

The full-bridge power MOSFETs should be selected fortheir RDS(ON) and BVDSS ratings. Select the lowest BVDSSrated MOSFET available for a given input voltage rangeleaving at least a 20% voltage margin. Conduction lossesare directly proportional to RDS(ON). Since the full-bridgehas two MOSFETs in the power path most of the time,conduction losses are approximately equal to:

2 • RDS(ON) • I2, where I = IO/2N

Switching losses in the MOSFETs are dominated by thepower required to charge their gates, and turn-on andturn-off losses. At higher power levels, gate charge poweris seldom a significant contributor to efficiency loss. ZVSoperation virtually eliminates turn-on losses. Turn-offlosses are reduced by the use of an external drain to source

OPERATIOU

LTC1922-1

20

snubber capacitor and/or a very low resistance turn-offdriver. If synchronous rectifier MOSFETs are used on thesecondary, the same general guidelines apply. Keep inmind, however, that the BVDSS rating needed for these canbe greater than VIN(MAX)/N, depending on how well thesecondary is snubbed. Without snubbing, the secondaryvoltage can ring to levels far beyond what is expected dueto the resonant tank circuit formed between the secondaryleakage inductance and the COSS (output capacitance) ofthe synchronous rectifier MOSFETs.

Switching Frequency Selection

Unless constrained by other system requirements, thepower converter’s switching frequency is usually set ashigh as possible while staying within the desired efficiencytarget. The benefits of higher switching frequencies aremany including smaller size, weight and reduced bulkcapacitance. In the full-bridge phase shift converter, theseprinciples are generally the same with the added compli-cation of maintaining zero voltage transitions, and there-fore, higher efficiency. ZVS is achieved in a finite timeduring the switching cycle. During the ZVS time, power isnot delivered to the output; the act of ZVS reduces themaximum available duty cycle. This reduction is propor-tional to maximum output power since the parasitic ca-pacitive element (MOSFETs) that increase ZVS time getlarger as power levels increase. This implies an inverserelationship between output power level and switchingfrequency. Table 1 displays recommended maximumswitching frequency vs power level for a 30V/75V in to3.3V/5V out converter. Higher switching frequencies canbe used if the input voltage range is limited, the outputvoltage is lower and/or lower efficiency can be tolerated.Table 1.Switching Frequency vs Power Level

<50W 600kHz

<100W 450kHz

<200W 300kHz

<500W 200kHz

<1kW 150kHz

<2kW 100kHz

Closing the Feedback Loop

Closing the feedback loop with the full-bridge converterinvolves identifying where the power stage and othersystem poles/zeroes are located and then designing acompensation network around the converters error ampli-fier to shape the frequency response to insure adequatephase margin and transient response. Additional modifi-cations will sometimes be required in order to deal withparasitic elements within the converter that can alter thefeedback response. The compensation network will varydepending on the load current range and the type of outputcapacitors used. In isolated applications, the compensa-tion network is generally located on the secondary side ofthe power supply, around the error amplifier of theoptocoupler driver, usually an LT1431or equivalent. Innonisolated systems, the compensation network is lo-cated around the LTC1922-1’s error amplifier.

In current mode control, the dominant system pole isdetermined by the load resistance (VO/IO) and the outputcapacitor 1/(2π • RO • CO). The output capacitors ESR1/(2π • ESR • CO) introduces a zero. Excellent DC line andload regulation can be obtained if there is high loop gain atDC. This requires an integrator type of compensatoraround the error amplifier. A procedure is provided forderiving the required compensation components. Morecomplex types of compensation networks can be used toobtain higher bandwidth if necessary.

Step 1. Calculate location of minimum and maximumoutput pole:

FP1(MIN) = 1/(2π • RO(MAX) • CO)

FP1(MAX) = 1/(2π • RO(MIN) • CO)

Step 2. Calculate ESR zero location:

FZ1 = 1/(2π • RESR • CO)

Step 3. Calculate the feedback divider gain:

RB/(RB + RT) or VREF/VOUT

If Polymer electrolytic output capacitors are used, the ESRzero can be employed in the overall loop compensationand optimum bandwidth can be achieved. If aluminumelectrolytics are used, the loop will need to be rolled offprior to the ESR zero frequency, making the loop response

OPERATIOU

LTC1922-1

21

slower. A linearized SPICE macromodel of the control loopis very helpful tool to quickly evaluate the frequencyresponse of various compensation networks.

Polymer Electrolytic (see Figure 12) 1/(2πCCRI) sets alow frequency pole. 1/(2πCCRF) sets the low frequencyzero. The zero frequency should coincide with the worst-case lowest output pole frequency. The pole frequencyand mid frequency gain (RF/RI) should be set such so thatthe loop crosses over zero dB with a –1 slope at afrequency lower than (fSW/8). Use a bode plot to graphi-cally display the frequency response. An optional higherfrequency pole set by CP2 and Rf is used to attenuateswitching frequency noise.

Aluminum Electrolytic (see Figure 12) the goal of thiscompensator will be to cross over the output minimumpole frequency. Set a low frequency pole with CC and RINat a frequency that will cross over the loop at the outputpole minimum F, place the zero formed by CC and Rf at theoutput pole F.

Synchronous Rectification

The LTC1922-1 produces the precise timing signals nec-essary to control current doubler secondary side synchro-nous MOSFETs on OUTE and OUTF. Synchronous rectifi-ers are used in place of Schottky or Silicon diodes on thesecondary side of the power supply. As MOSFET RDS(ON)levels continue to drop, significant efficiency improve-ments can be realized with synchronous rectification,provided that the MOSFET switch timing is optimized. Anadditional benefit realized with synchronous rectifiers isbipolar output current capability. These characteristicsimprove transient response, particularly overshoot, andimprove ZVS ability at light loads.

Figure 12. Compensation for Polymer Electrolytic

Current Doubler

The current doubler secondary employs two output induc-tors that equally share the output load current. The trans-former secondary is not center-tapped. This configurationprovides 2× higher output current capability compared tosimilarly sized single output inductor modules, hence thename. Each output inductor is twice the inductance valueas the equivalent single inductor configuration and thetransformer turns ratio is 1/2 that of a single inductorsecondary. The drive to the inductors is 180 degrees outof phase which provides partial ripple current cancellationin the output capacitor(s). Reduced capacitor ripple cur-rent lowers output voltage ripple and enhances thecapacitors’s reliability. The amount of ripple cancellationis related to duty cycle (see Figure 13). Although thecurrent doubler requires an additional inductor, the induc-tor core volume is proportional to LI2, thus the size penaltyis small. The transformer construction is simplified with-out a center-tap winding and the turns ratio is reduced by1/2 compared to a conventional full wave rectifier configu-ration.

Figure 13. Ripple Current Cancellation vs Duty Cycle

Synchronous rectification of the current doubler second-ary requires two ground referenced N-channel MOSFETs.The timing of the LTC1922-1 drive signals is shown in theTiming Diagram. Synchronous rectifier turn-on is inter-nally delayed by the LTC1922-1 after OUT (C or D)turn-off—just after the end of a power cycle. Synchronousrectifier turn-off occurs coincident with OUT (A or B)turn-off. This gives a passive transition time margin before

+

–

2.5V

Rf

RL

RDESR

REFRI

CC

CO

CP2VOUT

COLL

COMPOPTO

VOUT

LT1431 OR EQUIVALENTPRECISION ERROR

AMP AND REFERENCE

OPTIONAL

1922 F12

1

00 0.25 0.5

DUTY CYCLE

NORMALIZED OUTPUT RIPPLE

CURRENT ATTENUATION

1922 • F13

NOTE: INDUCTOR(S) DUTY CYCLE IS LIMITED TO 50% WITH CURRENT DOUBLER PHASE SHIFT CONTROL.

OPERATIOU

LTC1922-1

22

the start of a new power cycle. A noninverting MOSFETdriver such as the LTC1693-1 (Figure 14) is used so thata single signal transformer with secondary center tap canbe employed to translate the drive signals from the pri-mary to the secondary side. In the event of overcurrentshutdown, or UVLO condition, both synchronous rectifi-cation MOSFETs are driven on in order to protect the loadcircuitry.

Full-Bridge Gate Drive

The full-bridge converter requires high current MOSFETgate driver circuitry for two ground referenced switchesand two high side referred switches. Providing drive to theground referenced switches is not too difficult as long asthe traces from the gate driver chip or buffer to the gate andsource leads are short and direct. Drive requirements are

Figure 14. Isolated Drive Circuitry

further eased since all of the switches turn on with zeroVDS, eliminating the “Miller” effect. Low turn-off resis-tance is critical, however, in order to prevent excessiveturn-off losses resulting from the same Miller effects thatwere not an issue for turn on. The LTC1922-1 does notrequire the propagation delays of the high and low sidedrive circuits to be precisely matched as the DirectSenseZVS circuitry will adapt accordingly, unlike previous solu-tions. As a result, LTC1922-1 can drive a simple NPN-PNPbuffer or a gate driver chip like the LTC1693-1 to providethe low side gate drive. Providing drive to the high sidepresents additional challenges since the MOSFET gatemust be driven above the input supply. A simple circuit(Figure 15) using a single LTC1693-1, an inexpensivesignal transformer, and a few discrete components pro-vides both high side gate drives (A and C) reliably.

Figure 15. High Side Gate Driver Circuitry

IN1 OUT1

IN2 OUT2

1:2

OUTE

OUTF

LTC1922-1

GND1

GND2

LTC1693-1

1922 F14

IN OUTOUTA

OROUTC

GND

1/2LTC1693-1

1922 F15

VCC0.1µF

2µFCER

0.1µF

SIGNALTRANSFORMER

2kBAT54

BRIDGELEG

REGULATEDBIAS

POWERMOSFET

VIN

LTC1922-1

OPERATIOU

LTC1922-1

23

PACKAGE DESCRIPTIO

U

Dimensions in inches (millimeters) unless otherwise noted.

G20 SSOP 1098

0.13 – 0.22(0.005 – 0.009)

0° – 8°

0.55 – 0.95(0.022 – 0.037)

5.20 – 5.38**(0.205 – 0.212)

7.65 – 7.90(0.301 – 0.311)

1 2 3 4 5 6 7 8 9 10

7.07 – 7.33*(0.278 – 0.289)1718 14 13 12 1115161920

1.73 – 1.99(0.068 – 0.078)

0.05 – 0.21(0.002 – 0.008)

0.65(0.0256)

BSC0.25 – 0.38

(0.010 – 0.015)NOTE: DIMENSIONS ARE IN MILLIMETERSDIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDEDIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE

*

**

N20 1098

0.020(0.508)

MIN

0.125(3.175)

MIN

0.130 ± 0.005(3.302 ± 0.127)

0.065(1.651)

TYP

0.045 – 0.065(1.143 – 1.651)

0.018 ± 0.003(0.457 ± 0.076)

0.005(0.127)

MIN

0.100(2.54)BSC

0.255 ± 0.015*(6.477 ± 0.381)

1.040*(26.416)

MAX

1 2 3 4 5 6 7 8 9 10

19 1112131416 15171820

0.009 – 0.015(0.229 – 0.381)

0.300 – 0.325(7.620 – 8.255)

0.325+0.035–0.015+0.889–0.3818.255( )

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)

N Package20-Lead PDIP (Narrow 0.300)

(LTC DWG # 05-08-1510)

G Package20-Lead Plastic SSOP (0.209)

(LTC DWG # 05-08-1640)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

LTC1922-1

24 Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 2000

1922f LT/TP 0501 2K • PRINTED IN USA

TYPICAL APPLICATIO

U

PART NUMBER DESCRIPTION COMMENTS

LT1105 Off-Line Switching Regulator Built-In Isolated Regulation without Optoisolator

LT1681/LTC1698 36V to 72V Input Isolated DC/DC Converter Chipset Synchronous Rectification; Overcurrent, Overvoltage, UVLOProtection; Power Good Output Signal;h Voltage Margining;Compact Solution

LT1683 Ultralow Noise Push-Pull DC/DC Converter Minimizes Conducted and Radiated EMI; Reduces Need for Filters,Shields and PCB Iterations

LTC1693-1 High Speed Dual MOSFET Driver 1.5A Peak Output Current; 4.5V ≤ VIN ≤ 13.2V

LT1725 General Purpose Isolated Flyback Controller 48V to 5V Conversion; No Optoisolator Required

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