lp8501 multi-purpose 9-output led driver (rev. d)

LP8501

D1

D2

D4

D7

VOUT

COUT1 PF

C20.47 PF

VDD1_6

VDD7_9

GNDTRIG

INT

CIN1 PF

VIN = 2.7V TO 5.5VVDD

C10.47 PF

C1+ C1- C2+ C2-

GPO

B

G

R

D3

D8

B

G

R

B

G

R

D6

D5

D9

MCU

SCL

SDA

EN

CLK

VOUT

LP8501

www.ti.com SNVS548D –SEPTEMBER 2008–REVISED AUGUST 2013

LP8501 Multi-Purpose 9-Output LED DriverCheck for Samples: LP8501

1FEATURES DESCRIPTIONThe LP8501 is an LED driver with 9 outputs,

2• Three Independent Program Executiondesigned to produce versatile lighting effects forEngines for User-defined Programs with Largemobile devices. The device is equipped with anSRAM Memory for Storing Lighting Programs internal program memory, which allows operation

• 9 Programmable Source (High Side) Driver without processor control. Internal program memoryOutputs with 25.5 mA Full-Scale Current, 8-bit is used by three independent program executionCurrent Setting Resolution and 12-Bit PWM engines to produce user-defined lighting effects for

the outputs.Control Resolution• Flexible Grouping Possibility for All 9 Outputs A high-efficiency charge pump enables LED driving

Including GPO into Three Groups with Group over full Li-Ion battery voltage range. The excellentPWM and Fade-In/ Fade-Out Controls efficiency over a wide operating range is achieved by

autonomously selecting the best charge pump gain• Built-in LED Testbased on LED forward voltage requirements. The• Adaptive Charge Pump with 1x and 1.5x Gain LP8501 is able to automatically enter power-save

Provides up to 95% LED Drive Efficiency, with mode when LED outputs are not active, thus loweringSoft Start and Overcurrent/Short Circuit idle current consumption down to 10 µA (typ.)Protection

• Automatic Power Save Mode; IVDD = 10 µA(typ.)

• Two Wire, I2C-Compatible, Control Interface• Small Application Circuit• Pin-configured LED Powering for LEDs 1 to 6

and for LEDs 7 to 9• Solution Area <18 mm2

APPLICATIONS• Fun Lights and Indicator Lights• LED Backlighting and Color Keypad Lighting• Programmable Current Source• Haptic Feedback Driver and GPIO Expander

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date. Copyright © 2008–2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

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RGB or KeyLEDs

Sub Display

Main Display

LP8501

D1

D2

D4

D7

VOUT

COUT1 PF

C20.47 PF

VDD1_6

VDD7_9

GND

TRIG

INT

CIN1 PF

VIN = 2.7V TO 5.5V

VDD

C10.47 PF

C1+ C1- C2+ C2-

GPO

D3

D8

D6

D5

D9

MCU

SCL

SDA

EN

CLK

VOUT

LP8501

SNVS548D –SEPTEMBER 2008–REVISED AUGUST 2013 www.ti.com

DESCRIPTION (CONTINUED)The device has a flexible General Purpose Output (GPO) (which can be used, for example, as a digital controlpin for other devices), an INT pin (interrupt function), which can be used to notify the processor, and a Triggerinput interface, which allows program execution start without I2C write.

The device requires only four small and low-cost ceramic capacitors. The LP8501 is available in a tiny 25-bump2.26 mm x 2.26 mm x 0.60 mm DSBGA package (0.4 mm pitch).

Typical Application Circuits

2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated

Product Folder Links: LP8501


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RGB LEDs, KeyLEDs, Indicators

Main Display

LP8501

D1

D2

D4

D7

VOUT

COUT1 PF

C20.47 PF

VDD1_6

VDD7_9

GND

TRIG

INT

CIN1 PF

VIN = 2.7V TO 5.5V

VDD

C10.47 PF

C1+ C1- C2+ C2-

GPO

D3

D8

D6

D5

D9

MCU

SCL

SDA

EN

CLK

VOUT

RGB or KeyLEDs

Main Display

LP8501

D1

D2

D4

D7

VOUT

COUT1 PF

C20.47 PF

VDD1_6

VDD7_9

GND

TRIG

INT

CIN1 PF

VIN = 2.7V TO 5.5V

VDD

C10.47 PF

C1+ C1- C2+ C2-

GPO

D3

D8

D6

D5

D9

MCU

SCL

SDA

EN

CLK

VOUT

LP8501


Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 3



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1

2

3

4

5

E D C B A

5

4

3

1

E D B

2

C A

Main Display LP8501

D1

D2

D4

D7

VOUT

COUT1 PF

C20.47 PF

VDD1_6

VDD7_9

GND

TRIG

INT

CIN1 PF

VIN = 2.7V TO 5.5V

VDD

C10.47 PF

C1+ C1- C2+ C2-

GPO

D3

D8

D6

D5

D9

MCU

SCL

SDA

EN

CLK

VOUT

LP8501


Connection DiagramsThin DSBGA 25-bump package, 2.26 x 2.26 x 0.60 mm body size, 0.4 mm pitch, Package Number YFQ0025

Figure 1. Top View Figure 2. Bottom View




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LP8501


PIN DESCRIPTIONS (1)

Pin Name Type DescriptionA1 D1 A Current source output 1A2 D2 A Current source output 2A3 VOUT A Charge pump outputA4 C2- A Flying capacitor 2 negative terminalA5 C2+ A Flying capacitor 2 positive terminalB1 D3 A Current source output 3B2 D4 A Current source output 4B3 VDD1_6 P Power for D1 to D6 driversB4 C1- A Flying capacitor 1 negative terminalB5 C1+ A Flying capacitor 1 positive terminalC1 D5 A Current source output 5C2 D6 A Current source output 6C3 VDD7_9 P Power for D7 to D9 driversC4 EN I EnableC5 VDD P Input power supplyD1 D7 A Current source output 7.D2 D8 A Current source output 8.D3 INT OD/O Interrupt for microcontroller unit. Leave unconnected if not usedD4 CLK I 32 kHz clock input; connect to ground if not used.D5 GND G GroundE1 D9 A Current source output 9.E2 GPO O General purpose output. Leave unconnected if not used.E3 TRIG I/OD Trigger; connect to ground if not used.E4 SDA I/OD Serial interface dataE5 SCL I Serial interface clock

(1) A: Analog Pin, G: Ground Pin, P: Power Pin, I: Input Pin, I/O Input/Output Pin, O: Output Pin, OD: Open Drain Pin

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.




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LP8501


ABSOLUTE MAXIMUM RATINGS (1) (2) (3)

VDD −0.3V to +6.0VVoltage on D1 to D9, C1−, C1+, C2−, C2+, −0.3V to + 6.0VVOUTVoltage on Logic Pins (Input or Output Pins) −0.3V to VDD +0.3V

with 6.0V maxContinuous Power Dissipation (4) Internally LimitedJunction Temperature (TJ-MAX) 125°CStorage Temperature Range −65°C to +150°CMaximum Lead Temperature (Soldering) See (5)

ESD Rating Human Body Model: D1 to D9 4 kV (6)

Human Body Model: All Other Pins 2.5 kV (6)

Machine Model: All Pins 250V (7)

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation ofdevice reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings orother conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended OperatingConditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(2) All voltages are with respect to the potential at the GND pins.(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.(4) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) and

disengages at TJ = 130°C (typ.).(5) For detailed soldering specifications and information, please refer to Texas Instruments Application Note AN1112 : DSBGA Wafer Level

Chip Scale Package.(6) Human Body Model, applicable standard JESD22-A114C(7) Machine Model, applicable standard JESD22-A115-A

OPERATING RATINGS (1) (2)

VDD Input Voltage Range 2.7V to 5.5VVoltage on Logic Pins (Input or Output Pins) 0 to VDD

Recommended Charge Pump Load Current 0 mA to 100 mAJunction Temperature (TJ) Range −30°C to +125°CAmbient Temperature (TA) Range (3) −30°C to +85°C

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation ofdevice reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings orother conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended OperatingConditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.

(2) All voltages are with respect to the potential at the GND pins.(3) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP =125°C), the maximum power dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of thepart/package in the application (θJA), as given by the following equation: TA-MAX = TJ-MAX-OP – (θJA × PD-MAX).

THERMAL PROPERTIESJunction-to-Ambient Thermal Resistance (θJA) (1), Thermal Package 87°C/WYFQ0025 Package (2)

(1) Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 150°C (typ.) anddisengages at TJ = 130°C (typ.).

(2) Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum powerdissipation exists, special care must be paid to thermal dissipation issues in board design.




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LP8501


ELECTRICAL CHARACTERISTICS (1) (2) (3)

Limits in standard typeface are for TA = 25°C. Limits in boldface type apply over the operating ambient temperature range(−30°C < TA < +85°C). Unless otherwise noted, specifications apply to the LP8501 Block Diagram with: VDD = 3.6V, VEN =1.65V, COUT = 1 µF, CIN = 1 µF, C1–2 = 0.47 µF. (4)

Symbol Parameter Condition Min Typ Max UnitsVEN = 0V, CHIP_EN=0 (bit),external 32 kHz clock running or 0.2 1 µAnot running

Standby supply current CHIP_EN=0 (bit), external 32 kHz 0.7 µAclock not runningCHIP_EN=0 (bit), external 32 kHz 1.4 µAclock runningExternal 32 kHz clock running,charge pump and current source 0.6 mA

IVDD outputs disabledCharge pump in 1x mode, no

Normal Mode Supply Current load, current source outputs 0.8 mAdisabledCharge pump in 1.5x mode, noload, current source outputs 1.8 mAdisabledExternal 32 kHz clock running 11 µAPower Save Mode Supply

Current Internal oscillator running 0.6 mAInternal Oscillator Frequency −4 +4fOSC %Accuracy −7 +7

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Conditions except as otherwise modifiedor specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not ensured.

(2) All voltages are with respect to the potential at the GND pins.(3) Min and Max limits are specified by design, test, or statistical analysis. Typical numbers are not ensured, but do represent the most

likely norm.(4) Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.

CHARGE PUMP ELECTRICAL CHARACTERISTICSSymbol Parameter Condition Min Typ Max Units

Gain = 1.5x 3.5ROUT Charge Pump Output Resistance ΩGain = 1x 1fSW Switching Frequency 1.25 MHz

Gain = 1.5x 1.2IGND Ground Current mAGain = 1x 0.3tON VOUT Turn-On Time (1) VDD = 3.6V, IOUT = 60 mA 100 µs

(1) Turn-on time is measured from the moment the charge pump is activated until the VOUT crosses 90% of its target value.

LED DRIVER ELECTRICAL CHARACTERISTICSSymbol Parameter Condition Min Typ Max Units

ILEAKAGE Leakage Current (outputs D1 to D9) 0.1 1 µAIMAX Maximum Source Current Outputs D1 to D9 25.5 mA

−4 +4IOUT Output Current Accuracy (1) Output current set to 17.5 mA %−5 +5IMATCH Matching (1) Output current set to 17.5 mA 1 %fLED LED Switching Frequency 312 HzVSAT Saturation Voltage (2) Output current set to 17.5 mA 60 100 mV

(1) Output Current Accuracy is the difference between the actual value of the output current and programmed value of this current.Matching is the maximum difference from the average. For the constant current outputs on the part (D1 to D9), the following aredetermined: the maximum output current (MAX), the minimum output current (MIN), and the average output current of all outputs (AVG).Two matching numbers are calculated: (MAX-AVG)/AVG and (AVG-MIN)/AVG. The largest number of the two (worst case) isconsidered the matching figure. The typical specification provided is the most likely norm of the matching figure for all parts. Note thatsome manufacturers have different definitions in use.

(2) Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at VOUT – 1V.




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LP8501


LED TEST ELECTRICAL CHARACTERISTICSSymbol Parameter Condition Min Typ Max Units

LSB Least Significant Bit 30 mVEABS Total Unadjusted Error (1) VIN_TEST = 0V to VDD <±3 ±4 LSBtCONV Conversion Time 2.7 msVIN_TEST DC Voltage Range 0 5 V

(1) Total unadjusted error includes offset, full-scale and linearity errors.

LOGIC INTERFACE CHARACTERISTICSVEN = 1.65 to VDD unless otherwise noted.

Symbol Parameter Condition Min Typ Max UnitsLogic input ENVIL Input Low Level 0.5 VVIH Input High Level 1.2 VII Input Current –1.0 1.0 µAtDELAY Input Delay (1) 2 µsLogic input SCL, SDA, TRIG, CLKVIL Input Low Level 0.2xVEN VVIH Input High Level 0.8xVEN VII Input Current -1.0 1.0 µALogic output SDA, TRIG, INTVOL Output Low Level IOUT = 3 mA (pullup current) 0.3 0.5 VIL Output Leakage Current VOUT = 2.8V 1.0 µALogic output GPOVOL Output Low Level IOUT = 3 mA 0.3 0.5 VVOH Output High Level IOUT = -2 mA VDD −0.5 VDD −0.3IL Output Leakage Current VOUT = 2.8V 1.0 µA

(1) The I2C host should allow at least 500 µs before sending data to the LP8501 after the rising edge of the EN pin.




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LP8501


RECOMMENDED EXTERNAL CLOCK SOURCE CONDITIONS (1) (2)

Symbol Parameter Condition Min Typ Max UnitsLogic input CLK

ƒCLK Clock Frequency 32.7 kHztCLKH High Time 6 µstCLKL Low Time 6 µs

tr Clock Rise Time 10% to 90% 2 µstƒ Clock Fall Time 90% to 10 % 2 µs

(1) Specified by design. VEN = 1.65V to VDD.(2) The ideal external clock signal for the LP8501 is a 0V to VEN, 25% to 75% duty-cycle square wave. At frequencies above 32.7 kHz,

program execution will be faster and at frequencies below 32.7 kHz program execution will be slower.

SERIAL BUS TIMING PARAMETERS (SDA, SCL) (1)

LimitSymbol Parameter Units

Min MaxƒSCL Clock Frequency 400 kHz

1 Hold Time (repeated) START Condition 0.6 µs2 Clock Low Time 1.3 µs3 Clock High Time 600 ns4 Setup Time for a Repeated START Condition 600 ns5 Data Hold Time 50 ns6 Data Setup Time 100 ns7 Rise Time of SDA and SCL 20+0.1 Cb 300 ns8 Fall Time of SDA and SCL 15+0.1 Cb 300 ns9 Set-up Time for STOP condition 600 ns10 Bus Free Time between a STOP and a START Condition 1.3 µs

Capacitive Load Parameter for Each Bus LineCb 10 200 nsLoad of One Picofarad Corresponds to One Nanosecond

(1) Specified by design. VEN = 1.65V to VDD.




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VDD = 3.6V

VDD = 3.3V

VDD = 3.0V

VDD = 2.7V

OU

TP

UT

VO

LTA

GE

(V

OU

T)

LOAD CURRENT (A)

0.12

3.98

4.50

4.24

3.72

3.46

3.200.150.090.070.040.01

IOUT = 10 mA

EF

FIC

IEN

CY

(%

)

100

3.0

VDD (V)

80

60

IOUT = 60 mA

IOUT = 30 mA

2.5 3.5 4.0 4.5 5.0

VLED = 3.3V

VLED = 3.6V

VLED = 3V

IOUT = 45 mA

LED

DR

IVE

EF

FIC

IEN

CY

(%

)

VDD

2.6

30

3.1 3.6 4.0 4.5 5.0

40

50

60

70

80

90

100

VDD = 2.7V

VDD = 3.0V

VDD = 3.3V

VDD = 3.6V

0.89

0.92

0.86

0.83

0.81

0.78

0.75

EF

FIC

IEN

CY

(%

)

LOAD CURRENT (A)

0.090.07 0.12 0.150.040.01

0 51 102 153 204 255

CURRENT CODE (DEC)

I DR

IVE

R (

mA

)26.0

20.8

15.6

10.4

5.2

0.0

VDD

2.5

17.0

3.1 3.7 4.3 4.9 5.5

CU

RR

EN

T (

mA

)

17.1

17.1

17.2

17.3

17.3

17.4

17.5

17.5

17.6

17.7

17.7

17.8

17.9

17.9

18.0

LP8501


TYPICAL PERFORMANCE CHARACTERISTICSLED Current vs. Current Register Code LED Current vs. Supply Voltage

Figure 3. Figure 4.

LED Drive Efficiency vs. Input Voltage Automatic GainChange Charge Pump Efficiency vs. Load Current 1.5x Mode

Figure 5. Figure 6.

Charge Pump Efficiency vs. Input Voltage 1.5x Mode Charge Pump Output Voltage 1.5x Mode vs. Load Current

Figure 7. Figure 8.




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VDD

VOUT

VO

LTA

GE

TIME (10 ms/DIV)

2.7

3.1

3.5

3.8

4.2

4.6

VDD

VOUT

3.6V

4.2V

2.8V

3.6V

TIME (2 ms/DIV)

VO

LTA

GE

VLED = 3.6V

VLED = 3.3V

VLED = 3V

IOUT = 45 mA

(9*5 mA)

VO

UT

VDD

2.7

3.4

3.0 3.3 3.6 3.9 4.2

3.6

3.8

4.1

4.3

4.5

VDD decreasing

VDD increasing

VO

UT

VDD

2.7

2.8

3.0 3.3 3.6 3.9 4.2

3.1

3.5

3.8

4.2

4.5

100 mV

200 mV

300 mV

400 mV

VO

UT

VDD

2.7

2.9

3.0 3.3 3.6 3.9 4.2

3.2

3.5

3.9

4.2

4.5

Startup to 1x mode

Startup to 1.5x mode

VO

UT

TIME (200 Ps/DIV)

0.9

1.8

2.8

3.7

4.6

0.0

LP8501


TYPICAL PERFORMANCE CHARACTERISTICS (continued)Charge Pump Automatic Gain Change with Different

Charge Pump Startup in 1x and 1.5x Modes Hysteresis

Figure 9. Figure 10.

Charge Pump Automatic Gain Change with Different LED Charge Pump Automatic Gain Change Hysteresis with 400Forward Voltages mV Setting


Line Transient and Charge Pump Automatic Gain Change Line Transient and Charge Pump Automatic Gain Change(1.5x to 1x) (1x to 1.5x)

with 9 LED Outputs at 1mA 100% PWM with 9 LED Outputs at 1mA 100% PWM





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CU

RR

EN

T C

ON

SU

MP

TIO

N (

mA

)

VDD

1.2

1.0

0.8

0.7

0.5

0.3

-40oC

85oC

25oC

2.7 3.3 3.8 4.4 4.9

External clock, right scale

Internal clock, left scale

CU

RR

EN

T C

ON

SU

MP

TIO

N (

mA

)

VDD

0.5

3.0

CU

RR

EN

T C

ON

SU

MP

TIO

N (P

A)

3.5 4.0 4.5 5.0 5.5

0.6

0.7

0.8

0.9

1.0

8

12

16

21

25

29

Chargepump off

Chargepump 1x mode

Chargepump 1.5x mode

CU

RR

EN

T C

ON

SU

MP

TIO

N (

mA

)

VDD

0.30

2.70 3.26 3.82 4.38 4.94

0.64

0.98

1.32

1.66

2.00

LP8501


TYPICAL PERFORMANCE CHARACTERISTICS (continued)Current Consumption in Power Save Mode with Different

ClocksCurrent Consumption with Different Charge Pump Modes(LED Outputs Off) (Charge Pump in 1x Mode, LED Outputs Off)


Current Consumption with Different Temperatures(Charge Pump in 1x Mode, LED Outputs Off)

Figure 17.




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LP8501


FUNCTIONAL OVERVIEW

The LP8501 is a fully integrated lighting management unit (LMU) designed for producing lighting effects formobile devices. The LP8501 includes all necessary power management, high-side current sources, two-wirecontrol interface and programmable execution engines. The overall maximum current for each driver is set by an8-bit register.

The LP8501 controls LED luminance with a pulse width modulation (PWM) scheme with a resolution of 12 bits.

ProgrammingThe LP8501 provides flexibility and programmability for dimming and sequencing control. Each LED can becontrolled directly and independently through the serial bus. LED drivers can also be freely grouped together.The LED drivers may be grouped into a maximum of three groups. Each of the three groups' PWM can becontrolled through the serial bus.

The LP8501 has three independent program execution engines, so it is possible to form three independentlyprogrammable LED banks. LED drivers can be grouped based on their function so that, for example, the firstbank of drivers can be assigned to the keypad illumination, the second bank to the “fun lights” and the thirdgroup to the indicator LED(s). Each bank can contain 1 to 9 LED driver outputs. Instructions for programexecution engines are stored in the program memory. The total amount of the program memory is 96instructions, and the user can allocate the memory as required by the engines.

LED Error DetectionThe LP8501 has built-in LED error detection. Error detection both detects open and short circuits, and providesan opportunity to measure the forward voltages of the LEDs. The test is activated by serial interface write, andthe result can be read through the serial interface during the next cycle. This can be used for general purposemeasurements such as checking the supply voltages and charge pump output voltage.

Energy EfficiencyWhen charge pump automatic mode selection is enabled, the LP8501 monitors the voltage over the driverswhich are powered from the charge pump (VOUT) so that the device can select the best charge pump gain andmaintain good efficiency over the whole operating voltage range. In RGB LED applications the red LED elementtypically has a forward voltage of about 2V. For that reason, the outputs D7, D8 and D9 can be powered by VDDsince battery voltage is high enough to drive red LEDs over the whole operating range. This allows driving ofthree RGB LEDs with good efficiency because the red LEDs don't load the charge pump.

The LP8501 is able to automatically enter power-save mode, when LED outputs are not active, thus lowering idlecurrent consumption down to 10 µA (typ.). Also, during the "down time" of the PWM cycle (constant currentoutput status is low), additional power savings can be achieved under certain conditions.




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CHARGE PUMP1X/1.5X

C2

0.47 PF

C1

0.47 PF

COUT

1 PF

VOUT

C1+ C1- C2+ C2-

D/A

D1

D2

D6

D7

D8

D9

PROGRAM MEMORY

50H TO 6FH;96 INSTRUCTIONS

PWM PATTERNGENERATOR



12 BIT PWM PATTERN CONTROL

8 BITMAXIMUM

CURRENTCONTROL

IDAC AND HIGH SIDE

LED DRIVERS

SCL

SDA

EN

CLK

INT

VDD7_9

VDD1_6

TRIG

GPO

SERIAL DATA

CTRLREG

POR

THERMALSHUTDOWN

1.25 MHzOSC

BIAS

VREF

CONTROL

GND

CIN

1 PF

VDD

VDD7_9 LED

TE

ST

VDD1_6

LP8501


LP8501 Block Diagram




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STANDBY

RESET

INTERNALSTARTUP

SEQUENCE

Write FFh to Reset Register 3Dh

orPOR=H

TSD = H

NORMAL MODE

EN=H (pin) and CHIP_EN=H (bit) EN=L (pin) or

CHIP_EN=L (bit)

POR

TSD = L

POWER SAVE

Enter power save Exit power save

LP8501


Modes of OperationRESET In the RESET mode all the internal registers are reset to the default values. Reset is entered always if

FFh is written to Reset Register (3Dh) or internal Power-On Reset (POR) is active. POR will activateduring the chip startup or when the supply voltage VDD fall below 1.5V (typ.). Once VDD rises above 1.5V(typ.), POR will deactivate, and the chip will continue to the STANDBY mode. The CHIP_EN control bit islow after POR by default.

STANDBY: The STANDBY mode is entered if the register bit CHIP_EN or the EN pin is LOW, and Reset is notactive. This is the low-power consumption mode, when all circuit functions are disabled. Registers can bewritten in this mode if the EN pin is raised to high state so that control bits will be effective right after thestart up.

STARTUP: When CHIP_EN bit is written high and the EN pin is high, the INTERNAL STARTUP SEQUENCEpowers up all the needed internal blocks (VREF, Bias, Oscillator etc.). Startup delay is 500 μs. If the chiptemperature rises too high, the Thermal Shutdown (TSD) disables the chip operation, and chip waits inSTARTUP mode until no thermal shutdown event is present.

NORMAL: During NORMAL mode the user controls the chip using the Control Registers.

POWER SAVE: In POWER SAVE mode analog blocks are disabled to minimize power consumption. See PowerSaving for further information.




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REG 1.5XV, 1.5 x V

, ROUTVIN VOUT

LP8501


Charge Pump Operational Description

OverviewThe LP8501 includes a pre-regulated switched-capacitor charge pump with a programmable voltagemultiplications of 1 and 1.5x. The 1.5x mode combines the principles of a switched-capacitor charge pump and alinear regulator, generating a regulated 4.5V output from Li-Ion input voltage range. A two-phase non-overlappingclock generated internally controls the operation of the charge pump. During the charge phase, both flyingcapacitors (C1 and C2) are charged from input voltage. In the pump phase that follows, the flying capacitors aredischarged to output. A traditional switched capacitor charge pump operating in this manner will use switcheswith very low on-resistance, ideally 0Ω, to generate an output voltage that is 1.5x the input voltage. The LP8501regulates the output voltage by controlling the resistance of the input-connected pass-transistor switches in thecharge pump.

Output ResistanceAt lower input voltages, the charge pump output voltage may degrade due to effective output resistance (ROUT) ofthe charge pump. The expected voltage drop can be calculated by using a simple model for the charge pumpillustrated in Figure 18 below.

Figure 18. Charge Pump Output Resistance Model

The model shows a linear pre-regulation block (REG), a voltage multiplier (1.5x), and an output resistance(ROUT). Output resistance models the output voltage drop that is inherent to switched capacitor converters. Theoutput resistance is 3.5Ω (typ.), and it is a function of switching frequency, input voltage, flying capacitors’capacitance value, internal resistances of the switches and ESR of the flying capacitors. When the output voltageis in regulation, the regulator in the model controls the voltage V’ to keep the output voltage equal to 4.5V (typ).

With increased output current, the voltage drop across ROUT increases. To prevent a drop in output voltage, thevoltage drop across the regulator is reduced, V’ increases, and VOUT remains at 4.5V. When the output currentincreases to the point that there is zero voltage drop across the regulator, V’ equals the input voltage, and theoutput voltage is “on the edge” of regulation. Additional output current causes the output voltage to fall out ofregulation, so that the operation is similar to a basic open-loop 1.5x charge pump. In this mode, output currentresults in output voltage drop proportional to the output resistance of the charge pump. The out-of-regulationoutput voltage can be approximated by: VOUT = 1.5 x VIN – IOUT x ROUT.

Controlling the Charge PumpThe c harge pump is controlled with two CP_MODE bits in CONFIG register (address 36h). When both of the bitsare low, charge pump is disabled and output voltage is pulled down with an internal 300 kΩ (typ.) resistor. Thecharge pump can be forced to bypass mode, so that the battery voltage is connected directly to the currentsources; in 1.5x mode output voltage is boosted to 4.5V. In automatic mode, charge pump operation mode isdefined by current source outputs saturation as described in the next section.

LED Forward Voltage MonitoringWhen the charge-pump automatic mode selection is enabled, voltages over LED drivers connected to chargepump are monitored. If the drivers do not have enough headroom, the charge pump gain is set to 1.5x. Driversaturation monitor does not have a fixed voltage limit, since saturation voltage is a function of temperature andcurrent. Charge pump gain is set to 1x when battery voltage is high enough to supply all LEDs. Note that in orderto get the automatic gain change work correctly, power config bits in register 05H must be set according to wherethe VDD1_6 and VDD7_9 are connected.

In automatic gain change mode, the charge pump is switched to bypass mode (1x) when LEDs are inactive forover 50 ms.




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0,0 64,0 128,0 192,0 256,0

DIMMING CONTROL (DEC)

PW

M O

UT

PU

T %

100

80

60

40

20

00 64 128 192 256

8-BIT CURRENT SETTING

0 mA TO 25.5 mA

12-BIT PWM PATTERN CONTROL

0% TO 100 %

TIME

LED

OU

TP

UT

CU

RR

EN

T

PWM FREQUENCY = 312Hz

LP8501


Gain Change HysteresisCharge pump gain control utilizes digital filtering to prevent supply voltage disturbances (for example, thetransient voltage on the power supply during the GSM burst) from triggering unnecessary gain changes.Hysteresis is provided to prevent periodic gain changes, which would occur due to LED driver and charge pumpvoltage drops in 1x mode. The hysteresis of the gain change can be configured by the user; default setting isfactory programmable. Flexible configuration ensures that hysteresis can be minimized or set to desired level ineach application.

LED Driver Operational Description

OverviewThe LP8501 LED drivers are constant current sources. Output current can be programmed with an I2C registerup to 25.5 mA. The overall maximum current is set by 8-bit output current control registers with 100 μA step size.Each of the 9 LED drivers has a separate output current control register. See table below for current control.

CURRENT bits Output Current00000000 0.0 mA00000001 0.1 mA00000010 0.2 mA

... ...10101111 17.5 mA default setting

.... ....11111110 25.4 mA11111111 25.5 mA

The LED luminance pattern (dimming) is controlled with PWM (pulse width modulation) technique, which hasinternal resolution of 12 bits (8-bit control can be seen by user). PWM frequency is 312 Hz. See Figure 19.

Figure 19. LED Pattern and Current Control Principle

For LED dimming a logarithmic or linear scale can be applied — see the figure below (Figure 20). Logarithmic orlinear scheme can be set for both the program execution engine control and direct PWM control. By using alogarithmic PWM scale, the visual effect looks linear to the human eye.

Figure 20. Logarithmic vs Linear Dimming




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LP8501


Powering LEDsThe power for the LEDs is supplied via VDD1_6 (outputs D1 to D6) and VDD7_9 pins (outputs D7 and D9).Powering LEDs this way allows flexibility since the pins can be connected to the VDD or to the VOUT (or to anotherapplication power source, for example, an external DC/DC converter may be used), depending on theapplication.

In the case of LEDs which have forward voltages around 2 volts, LEDs can be powered directly from VDD. If allthe LEDs are powered from VDD or an external power source and VOUT is not used the charge pump can be leftunconnected and charge pump capacitors can be left uninstalled. When the forward voltage of the LEDs isaround 3.6V, VDD may not be high enough. In this case the LEDs should be powered from the VOUT.

Note that the power supply must be correctly defined in the LP8501 register settings (register 05h 'PowerConfig').

Controlling the PWM of High-Side LED Drivers1. Direct PWM Control

– All LP8501 LED drivers, D1 to D9, can be controlled independently through the two-wire serial I2Ccompatible interface. For each high-side driver there is a PWM control register. Direct PWM control isactive by default.

2. Controlling by Program Execution Engines– Engine control is used when the user wants to create programmed sequences. Th program execution

engine has higher priority than direct control registers. Therefore, if the user has set a certain value to thePWM register, it will be automatically overridden when the program execution engine controls the driver.LED control and program execution engine operation is described later on in this document.

3. Group Fader Control– In addition to LED-by-LED PWM register control, the LP8501 is equipped with group fader control, which

allows the user to fade in or fade out multiple LEDs by writing to only one register. This is a usefulfunction to minimize serial bus traffic between the MCU and the LP8501. The LP8501 has three groupfader registers, so it is possible to form three fader groups.

– With the LP8501 it is also possible to set fade-in and fade-out times. These times control the time whenramping up or down the group PWM value. Time can be set with 4-bits according to the following table.

FADE IN/FADE OUT Time (s)0000 0.00001 0.050010 0.10011 0.20100 0.30101 0.40110 0.50111 0.61000 0.71001 0.81010 0.91011 1.01100 1.51101 2.01110 3.01111 4.0




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LP8501


– When the LP8501 is shut down (through chip_en), the fading off can be achieved. When “fade-to-off” bit(in register 36h) is set to 1, the group fade times have effect, and the LEDs fade off according to the timeset in the register.

Examples of Controlling LED Drivers1. Direct PWM Control Example —Start up the device:

– Supply, e.g., 3.6V to VDD.– Supply, e.g., 1.8V to EN.– Write 40h (0100 0000b) to address 00h (enable LP8501).– Wait 500 µs (startup delay).Check LED powering– Suppose LED outputs from 1 to 6 are connected to VDD and LED outputs 7 to 9 are connected to VOUT.– Write 01h (0000 0001b) to address 05h (VDD1_6 powered from VDD and VDD7_9 powered from VOUT.Enable charge pump to AUTO mode and use internal clock– Write 19h (0001 1001b) to address 36h.Write PWM values:– Write 80h (1000 0000b) to address 16h (LED output 1 PWM duty cycle to 50%).– Write C0h (1100 0000b) to address 1Ah (LED output 5 PWM duty cycle to 75%).– Write FFh (1111 1111b) to address 1Eh (LED output 9 PWM duty cycle to 100%).LED outputs are turned on after PWM values are written. Changes to the PWM value registers are reflectedimmediately to the LED brightness. Default LED output current (17.5 mA) is used for LED outputs, if no othervalues are written.

2. Controlling by Program Execution Engines Example —Start up device and configure device to SRAMwrite mode:– Supply e.g. 3.6V to VDD.– Supply e.g. 1.8V to EN.– Generate 32 kHz clock signal to CLK pin.– Write 40h (0100 0000b) to address 00h.– Wait 500 µs (startup delay).– Write 14h (0001 0100b) to address 01h (configure engines 1 and 2 to Load mode).Check LED powering– Suppose LED outputs from 1 to 6 are connected to VOUT and LED outputs 7 to 9 are connected to VDD.– Write 02h (0000 0010b) to address 05h (VDD1_6 powered from VOUT and VDD7_9 powered from VDD.Program load to SRAM– Write 00h (0000 0000b) to register 4Fh (select memory page 0).– Write 9Dh (1001 1101b) to register 50h (select LED output 1 for engine 1 MSB, instruction part).– Write 01h (0000 0001b) to register 51h (select LED output 1 for engine 1 LSB, output selection part).– Write 40h (0100 0000b) to register 52h (set PWM value to full FFh MSB, instruction part).– Write FFh (1111 1111b) to register 53h (set PWM value to full FFh LSB, PWM value part).– Write 7Eh (0111 1110b) to register 54h (wait for 0.48s (maximum) MSB, instruction part).– Write 00h (0000 0000b) to register 55h (wait for 0.48s LSB).– Write 40h (0100 0000b) to register 56h (set PWM value to zero MSB, instruction part).– Write 00h (0000 0000b) to register 57h (set PWM value to zero LSB, PWM value part).– Write 7Eh (0111 1110b) to register 58h (wait for 0.48s MSB, instruction part).– Write 00h (0000 0000b) to register 59h (wait for 0.48s LSB).– Write A2h (1010 0010b) to register 5Ah (branch instruction with loop count 4 MSB, instruction part).– Write 01h (0000 0001b) to register 5Bh (branch instruction with loop count 4 LSB sets program counter

value to '1', i.e., program continues execution in this case from setting PWM value).– Write C0h (1100 0000b) to register 5Ch (end instruction MSB, instruction part).– Write 00h (0000 0000b) to register 5Dh (end instruction LSB).– Write 9Dh (1001 1101b) to register 5Eh (select LED output 3 for engine 2MSB, instruction part).




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LP8501


– Write 03h (0000 0011b) to register 5Fh (select LED output 3for engine 2LSB, output selection part).– Write 40h (0100 0000b) to register 60h (set PWM value to full FFh MSB, instruction part).– Write FFh (1111 1111b) to register 61h (set PWM value to full FFh LSB, PWM value part).– Write 7Eh (0111 1110b) to register 62h (wait for 0.48s (maximum) MSB, instruction part).– Write 00h (0000 0000b) to register 63h (wait for 0.48s LSB).– Write 40h (0100 0000b) to register 64h (set PWM value to zero MSB, instruction part).– Write 00h (0000 0000b) to register 65h (set PWM value to zero LSB, PWM value part).– Write 7Eh (0111 1110b) to register 66h (wait for 0.48s MSB, instruction part).– Write 00h (0000 0000b) to register 67h (wait for 0.48s LSB).– Write A2h (1010 0010b) to register 68h (branch instruction with loop count 4 MSB, instruction part).– Write 01h (0000 0001b) to register 69h (branch instruction with loop count 4 LSB sets program counter

value to '1', i.e., program continues execution in this case from setting PWM value).– Write C0h (1100 0000b) to register 6Ah (end instruction MSB, instruction part).– Write 00h (0000 0000b) to register 6Bh (end instruction LSB).Set start address– Write 00h (0000 0000b) to register 4Ch (set engine 1 start address to 0).– Write 07h (0000 0111b) to register 4Dh (set engine 2 start address to 7, 7th 16–bit write, 15th I2C write).– Optional: Write 00h (0000 0000b) to register 37h (set program counter of engine 1 to 0).– Optional: Write 00h (0000 0000b) to register 38h (set program counter of engine 2 to 0).Enable powersave, set charge pump to auto mode and select external clock:– Write 38h (0011 1000b) to register 36h.Run program:– Write 28h (0010 1000b) to register 01h (set engines 1 and 2 to Run mode).– Write 68h (0110 1000b) to register 00h (set program execution from Hold to Run and keep device

enabled).LP8501 will now generate five 0.48 second long blinks to LED outputs 1 and 3.

3. Group Fader ControlStart up the device:– Supply, e.g., 3.6V to VDD.– Supply, e.g., 1.8V to EN.– Write 40h (0100 0000b) to address 00h (enable the device).– Wait 500 µs (startup delay).Check LED powering– Suppose LED outputs from 1 to 9 are connected to VOUT.– Write 03h (0000 0011b) to address 05h (VDD1_6 and VDD7_9 powered from VOUT.Enable charge pump 1.5x mode and use internal clock:– Write 11h (0001 0001b) to register 36h.Select LED outputs 1, 3 and 7 to Fader Group 1:– Write 40h (0100 0000b) to address 06h (LED output 1 to group 1).– Write 40h (0100 0000b) to address 08h (LED output 3 to group 1).– Write 40h (0100 0000b) to address 0Ch (LED output 7 to group 1).Set group 1 fader times:– Write CFh (1100 1111b) to register 02h (group 1 Fade IN time to 1.5 s and Fade OUT time to 4s).Set group PWM value:– Write FFh (1111 1111b) to register 48h (group 1 PWM duty cycle to 100%, all three LED outputs fades

on in 1.5s)




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LP8501


LP8501 Engine ProgrammingThe LP8501 has three independent programmable lighting engines. All the lighting engines have their ownprogram memory block allocated by the user. Note that in order to access program memory the operation modeneeds to be LOAD Program, at least for one of the three lighting engines. Also note that one should not changefrom RUN —mode directly to LOAD program. Correct sequence would be RUN (10) –> DISABLED (00) –>LOAD (01).

Program execution is clocked with 32 768Hz clock. This clock can be generated internally, or an external 32 kHzclock can be connected to CLK pin. Using external clock enables synchronization of LED timing to this clockrather than to the internal clock.

The engines have different priorities; thus when more than one engine is controlling the same LED output: theLED engine 1 has the highest priority, LED engine 2 second highest and LED engine 3 third highest.

Supported instruction set is listed in the tables below:

Table 1. LP8501 LED Driver InstructionsInst. Bit [15] Bit Bit Bit Bit Bit Bit [9] Bit [8] Bit [7] Bit [6] Bit Bit [4] Bit [3] Bit Bit Bit

[14] [13] [12] [11] [10] [5] [2] [1] [0]pres

Ramp 0 cale Step time Sign # of incrementsSet PWM 0 1 0 0 0 0 0 0 PWM value

presWait 0 cale Time 0 0 0 0 0 0 0 0 0

Table 2. LP8501 LED Mapping InstructionsInst. Bit Bit Bit Bit Bit Bit Bit [9] Bit [8] Bit [7] Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1] Bit [0]

[15 [14] [13] [12] [11] [10]]

mux_ld 1 0 0 1 1 1 0 0 0 SRAM address 0–95_startmux_ld 1 0 0 1 1 1 0 0 1 SRAM address 0–95_endmux_se 1 0 0 1 1 1 0 1 0 LED selectlmux_clr 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0mux_in 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 0cmux_de 1 0 0 1 1 1 0 1 1 1 0 0 0 0 0 0cmux_se 1 0 0 1 1 1 1 1 1 SRAM address 0–95t

Table 3. LP8501 Branch InstructionsInst. Bit [15] Bi t Bit Bit [12] Bit Bit Bit [9] Bit [8] Bit [7] Bit [6] Bit Bit Bit [3] Bit Bit Bit

[14] [13] [11] [10] [5] [4] [2] [1] [0]Go to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0StartBranch 1 0 1 Loop count Step numberInt 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0End 1 1 0 Int Reset X X X X X X X X X X XTrigger 1 1 1 Wait for a trigger Send a trigger X

Ext. trig X X ENGI ENGI ENGI Ext. X X ENGI ENG ENG XNE3 NE2 NE1 trig NE3 INE2 INE1




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DIMMINGCONTROL

STEP COUNT1 2 43 5 6 7 80

STEP TIME SPAN = 187.5 ms

TIME ELAPSED (ms)375 750 1125 1500140

141

142

143

144

145

146

147

148

0

RAMP INSTRUCTION

LP8501


RAMPThis is the instruction useful for smoothly changing from one PWM value into another PWM value on the D1 toD9 outputs; in other words, generating ramps (with a negative or positive slope). The LP8501 allowsprogramming of very fast and very slow ramps.

Ramp instruction generates a PWM ramp, using the effective PWM value as a starting value. At each ramp stepthe output is incremented/decremented by one unit, unless the step time span is 0 or number of increments is 0.Time span for one ramp step is defined with prescale (bit [14]) and step time (bits [13:9]). Prescale = 0 sets 0.49ms cycle time and prescale = 1 sets 15.6 ms cycle time; so the minimum time span for one step is 0.49 ms(prescale * step time span = 0.49ms x 1) and the maximum time span is 15.6 ms x 31 = 484ms/step. Note: if allthe step time bits [13:9] are set to zero, instruction is treated as Set PWM instruction.

The number of increment define how many steps will be taken during one ramp instruction; maximum incrementvalue is 255d, which corresponds to incrementing from zero to the maximum value. If PWM reachesminimum/maximum value (0/255) during the ramp instruction, ramp instruction will be executed to the endregardless of saturation. This enables ramp instruction to be used as a combined ramp & wait instruction. Note:Ramp instruction is the wait instruction when the increment bits [7:0] are set to zero.

Setting bit LOG_EN high/low sets logarithmic (1) or linear ramp (0) (bit 5 in registers 06h — 0Eh and in register15h for GPO). By using the logarithmic ramp setting the visual effect appears like a linear ramp, because thehuman eye behaves in a logarithmic way.

Name Value (d) Descriptionprescale 0 Divides master clock (32 768 Hz) by 16 = 2048 Hz → 0.488 ms cycle time

1 Divides master clock (32 768 Hz) by 512 = 64 Hz → 15.625 ms cycle timesign 0 Increase PWM output

1 Decrease PWM outputstep time 1 - 31 One ramp increment done in (step time) x (prescale). Note: 0 means Set PWM instruction# of increments 0 - 255 The number of increment/decrement cycles Note: Value 0 takes the same time as increment by 1, but

it is the wait instruction.

RAMP INSTRUCTION APPLICATION EXAMPLELet's say that the LED dimming is controlled according to the linear scale and effective PWM value at themoment t=0 is 140d (~55%,), as shown in Figure 21 below, and we want to reach a PWM value of 148d (~58%)at the moment t = 1.5s. The parameters for the RAMP instruction will be:• Prescale = 1 → 15.625 ms cycle time• Step time = 12 → step time span will be 12*15.625 ms = 187.5 ms• Sign = 0 → increase PWM output• # of increments = 8 → take 8 steps

Figure 21. Example of Ramp Instruction




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LP8501


SET_PWMThis instruction is used for setting the PWM value on the outputs D1 to D9 without any ramps. Set PWM outputvalue from 0 to 255 with PWM value bits [7:0]. Instruction execution takes sixteen 32 kHz clock cycles (=488 µs).

Name Value (d) DescriptionPWM value 0 to 255 PWM output duty cycle 0 to 100%

WAITWhen a wait instruction is executed, the engine is set in a wait status, and the PWM values on the outputs arefrozen.

Name Value (d) Descriptionprescale 0 Divide master clock (32 768 Hz) by 16 which

means 0.488 ms cycle time1 Divide master clock (32 768 Hz) by 512

which means 15.625 ms cycle timetime 1 — 31 Total wait time will be = (time) x (prescale).

Maximum 484 ms, minimum 0.488 ms

LED MAPPING INSTRUCTIONSThese commands define the engine-to-LED mapping. The mapping information is stored in a table, which isstored in the SRAM (program memory of the LP8501). Mapping information can be located anywhere in SRAMmemory. LP8501 has three lighting engines (Engines) which can be mapped to 9 LED drivers or to one GPO pin.One engine can control one or multiple LED drivers. There are totally seven commands for the engine-to-LEDdriver control: mux_ld_start, mux_ld_end, mux_sel, mux_clr, mux_inc, mux_dec, mux_set. Note: the LEDmapping instructions do not update PWM values to LED outputs. PWM values are updated after ramp orset_pwm instructions.

MUX_LD_START; MUX_LD_ENDMux_ld_start and mux_ld_ end define the mapping table location in the memory. With mux_ld_start instructionthe mapped row can be activated at the same time by setting map = 1.

Name Value (d) Descriptionmap 0 Mapped row inactive

1 Set the mapped row active. MUX_LD_START onlySRAM address 0 - 95 Mapping table start/end address

MUX_SELWith mux_sel instruction one, and only one, LED driver (or the GPO pin) can be connected to a lighting engine.Connecting multiple LEDs to one engine is done with the mapping table. After the mapping has been releasedfrom an LED, the PWM register value will still control the LED brightness. If the mapping is released from theGPO pin, serial bus control takes over the GPO state.

Name Value (d) DescriptionLED select 0 - 16 0 = no drivers selected

1 = LED1 selected2 = LED2 selected...9 = LED9 selected16 = GPO

MUX _CLRMux_clr clears engine-to-driver mapping. After the mapping has been released from an LED, the PWM registervalue will still control the LED brightness. If the mapping is released from the GPO pin, serial bus control takesover the GPO state.




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LP8501


MUX_INCA mux_inc instruction sets the next row active in the mapping table each time it is called. For example, if the 2nd

row is active after a mux_inc instruction is called, the 3rd row will be active. If the mapping table end is reached,activation will roll to the mapping table start address next time when the mux_inc instruction is called. The enginewill not push a new PWM value to the LED driver output before a SET_PWM or RAMP instruction is executed. Ifthe mapping has been released from an LED, the value in the PWM register will still control the LED brightness.If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

MUX_DECA mux_dec instruction sets the previous row active in the mapping table each time it is called. For example, if the3rd row is active, after mux_dec instruction is called, the 2nd row will be active. If the mapping table start addressis reached, activation will roll to the mapping table end address the next time the mux_dec instruction is called.The engine will not push a new PWM value to the LED driver output before a SET_PWM or RAMP instruction isexecuted. If the mapping has been released from an LED, the value in the PWM register will still control the LEDbrightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

MUX_SETMux_set sets the index pointer to point the mapping table row defined by bits [6:0] and sets the row active. Theengine will not push a new PWM value to the LED driver output before a SET_PWM or RAMP instruction isexecuted. If the mapping has been released from an LED, the value in the PWM register will still control the LEDbrightness. If the mapping is released from the GPO pin, serial bus control takes over the GPO state.

Name Value (d) DescriptionSRAM address 0 to 95 Any SRAM address containing mapping data

GO-TO-STARTA go-to-start command resets the Program Counter register (address 37h 38h or 39h) and continues executingthe program from the I2C register program start address defined in 4Ch-4Eh. Command takes sixteen 32 kHzclock cycles. Note that default value for all program memory registers is 00h, which is “Go-to-Start” command.

BRANCHBranch instruction is mainly indented for repeating a portion of the program code several times. Step numberparameter defines how many steps loop start point is relative to the engine Start Address. The loop countparameter defines how many times the instructions inside the loop are repeated. The LP8501 supports nestedlooping, i.e., loop inside loop. The number of nested loops is not limited. Instruction takes sixteen 32 kHz clockcycles.

Name Value (d) Descriptionloop count 0 to 63 The number of loops to be done. 0 means an infinite loop.step number 0- to 95 How many steps loop start point is from engine Start Address.

INTSends interrupt to processor by pulling the INT pin down and setting the corresponding status bit high. Interruptcan be cleared by reading interrupt bits in STATUS/INTERRUPT register at address 3Ah. With this instructionprogram execution continues.




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LP8501


ENDEnds program execution and resets the PC. Instruction takes sixteen 32 kHz clock cycles. An end instruction canhave two parameters, INT and RESET. These parameters are described in tables below. Execution engine bits(Register 00h bits [5:0]) are set to zero, i.e., hold mode.

Name Value Descriptionint 0 No interrupt will be sent. PWM registers values will remain intact. Program

counter value is set to 0.1 Reset program counter value to 0 and send interrupt to processor by pulling

the INT pin down and setting corresponding status bit high to notify thatprogram has ended. PWM register values will remain intact. Interrupt canbe cleared by reading interrupt bits in STATUS/INTERRUPT register ataddress 3Ah

Name Value Descriptionreset 0 Reset program counter value to 0 and hold. PWM register values remain

intact.1 Reset program counter value to 0 and hold. PWM register values of the

non-mapped drivers will remain. PWM register values of the mapped driverswill be set to '0000 0000'.

TRIGGERWait or send triggers can be used to synchronize operation between the program execution engines. A sendtrigger instruction takes sixteen 32 kHz clock cycles and a wait-for trigger takes at least sixteen 32 kHz clockcycles. The receiving engine stores the triggers which have been sent. Received triggers are cleared by wait fortrigger instruction. Wait for trigger instruction is executed until all the defined triggers have been received (note:several triggers can be defined in the same instruction).

An external trigger input signal must stay low for at least two 32 kHz clock cycles to be executed. A trigger outputsignal is three 32 kHz clock cycles long. An external trigger signal is active low, i.e. when trigger is send/receivedthe pin is pulled to GND. Sent external trigger is masked, i.e,. the device which has sent the trigger will notrecognize it. If send and wait external triggers are used on the same instruction, the send external trigger isexecuted first, then the wait external trigger.

Name Value (d) Descriptionwait for a trigger 0 to 31 Wait for a trigger from the engine(s). Several triggers can be defined in the

same instruction. Bit [7] engages engine 1, bit [8] engages engine 2, bit [9]engages engine 3 and bit [6] is for external trigger I/O. Bits [4] and [5] arenot in use.

send a trigger 0 to 31 Send a trigger to the engine(s). Several triggers can be defined in the sameinstruction. Bit [1] engages engine 1, bit [2] engages engine 2, bit [3]engages engine 3 and bit [6] is for external trigger I/O. Bits [4] and [5] arenot in use.

Power Saving

Automatic Power Save ModeAutomatic power save mode is enabled when the POWERSAVE_EN bit in register address 36h is ‘1’. Almost allanalog blocks are powered down in power save if an external clock signal is used. Only the charge pumpprotection circuits remain active. However, if the internal clock has been selected, only the charge pump andLED drivers are disabled during the power save; the digital part of the LED controller needs to stay active. Inboth cases the charge pump enters the weak 1x mode. In this mode the charge pump utilizes a passive currentlimited keep-alive switch, which keeps the output voltage at the battery level. During the program executionLP8501 can enter power save if there is no PWM activity in any of the LED driver outputs. To prevent shortpower save sequences during program execution, LP8501 has an instruction look-ahead filter. During programexecution engine 1, engine 2 and engine 3 instructions are constantly analyzed, and if there are time slots withno PWM activity on LED driver outputs for 50 ms, the device will enter power save. In power save mode programexecution continues uninterruptedly. When an instruction that requires PWM activity is executed, a fast internalstartup sequence will be started automatically.




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LED brightness(adjusted with PWM

duty cycle)

Time

Powersave mode if brightness = 0

longer than 50 ms

POWERSAVE POWERSAVE

Time

Additional power savings from PWM powersave mode

Chip current consumption(LED current not included)

LED brightness (adjusted with PWM

duty cycle)

Time

Time

Powersave mode if brightness = 0

longer than 50 ms

Chip current consumption(LED current not included)

POWERSAVE POWERSAVE

LP8501


PWM Cycle Power Save ModePWM cycle power save mode is enabled when the PWM_POWERSAVE bit in register 36h is set to '1'. In PWMpower save mode analog blocks are powered down during the down time of the PWM cycle. Blocks are powereddown depending upon whether an external or an internal clock is used. While the Automatic Power-Save Modesaves energy when there is no PWM activity, the PWM Power-Save mode saves energy during PWM cycles.Like the Automatic Power-Save Mode, PWM Power-Save Mode works also during program execution.

Figure 22. The Effect of Power-Save mode during a Lighting Sequence

Figure 23. The effect of Powersave and PWM Powersave modes during a lighting sequence

Logic Interface Operational DescriptionThe LP8501 features a flexible logic interface for connecting to processor and peripheral devices.Communication is done with and I2C-compatible interface; different logic input/output pins makes it possible to,for example, trigger program execution or enable power saving for the device.




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InputBuffer

LevelShifter

LevelShifter

SDA

SCL

VDD

EN

LP8501


IO LEVELSI2C interface, CLK and TRIG pin input levels are defined by the EN pin. Using the EN pin as voltage reference forlogic inputs simplifies PWR routing and eliminates the need for a dedicated VIO pin. In the following blockdiagram EN pin connections are illustrated.

Figure 24. Using EN Pin As Digital IO Voltage Reference

GPO/INT PinsThe LP8501 has one General Purpose Output pin (GPO); the INT pin also can be configured as a GPO pin. TheGPO pin level is defined by VDD voltage. It also has its own PWM control register. GPO can be configured intofader groups, and it can be used in LED engine programming. When INT is configured as GPO, its level isdefined by the VDD. State of the pins can be controlled with GPO register (3Bh). GPO pins are digital CMOSoutputs, and no pull-up/down resistors are needed.

When the INT pin GPO function is disabled, it operates as an open drain pin. The INT signal is active low, i.e.,when interrupt signal is sent, the pin is pulled to GND. External pull-up resistor is needed for proper functionality.

Table 4. GPO register (3Bh)Name Bit DescriptionINT_CONF 2 Enable INT pin GPO function

0 = INT pin functions as a INT pin1 = INT pin functions as a GPO pin

GPO 1 0 = GPO pin state is low1 = GPO pin state is high

GPO_INT 0 0 = INT pin state is low (INT_CONF=1)1 = INT pin state is high (INT_CONF=0)

TRIG PinThe TRIG pin can function as an external trigger input or output. The external trigger signal is active low if, whentrigger is sent/received, the pin is pulled to GND. TRIG is an open drain pin, and an external pull-up resistor isneeded for trigger line. The external trigger input signal must be at least two 32 kHz clock cycles long to berecognized. Trigger output signal is three 32 kHz clock cycles long. If TRIG pin is not used on application, itshould be connected to GND to prevent floating of this pin and extra current consumption.

CLK PinThe CLK pin is used for connecting an external 32 kHz clock to the LP8501. Using an external clock can improveautomatic power-save mode efficiency because the internal clock can be switched off automatically when thedevice has entered powersave mode with an external clock present. The device can be used without the externalclock. If an external clock is not used on the application, the CLK pin should be connected to GND to preventfloating of this pin and extra current consumption.




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SCL

SDA

data change allowed

data valid

data change allowed

data valid

data change allowed

LP8501


I2C-Compatible Control InterfaceThe I2C compatible synchronous serial interface provides access to the programmable functions and registers onthe device. This protocol uses a two-wire interface for bidirectional communications between the IC's connectedto the bus. The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). Every deviceon the bus is assigned a unique address and acts as either a Master or a Slave depending on whether itgenerates or receives the serial clock SCL. The SCL and SDA lines should each have a pull-up resistor placedsomewhere on the line and remain HIGH even when the bus is idle. Note: CLK pin is not used for serial bus datatransfer.

Data ValidityThe data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state ofthe data line can only be changed when clock signal is LOW.

Figure 25. Data Validity Diagram

Start and Stop ConditionsSTART and STOP conditions classify the beginning and the end of the data transfer session. A START conditionis defined as the SDA signal transitions from HIGH to LOW while SCL line is HIGH. A STOP condition is definedas the SDA transitions from LOW to HIGH while SCL is HIGH. The bus master always generates START andSTOP conditions. The bus is considered to be busy after a START condition and free after a STOP condition.During data transmission, the bus master can generate repeated START conditions. First START and repeatedSTART conditions are equivalent, function-wise.

Transferring DataEvery byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first.Each byte of data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generatedby the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The LP8501 pullsdown the SDA line during the 9th clock pulse, signifying an acknowledge. The LP8501 generates anacknowledge after each byte has been received.

There is one exception to the “acknowledge after every byte” rule. When the master is the receiver, it mustindicate to the transmitter an end of data by not-acknowledging (“negative acknowledge”) the last byte clockedout of the slave. This “negative acknowledge” still includes the acknowledge clock pulse (generated by themaster), but the SDA line is not pulled down.

After the START condition, the bus master sends a chip address. This address is seven bits long followed by aneighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a “0” indicates a WRITE and a “1”indicates a READ. The second byte selects the register to which the data will be written. The third byte containsdata to write to the selected register.

I2C-Compatible Chip AddressLP8501 serial bus address is 32h.




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ack from slave

start MSB Chip Addr LSB

SCL

ack from slave

w MSB Register Addr LSB rs r MSB Data LSB stop

ack from slave nack from masterrepeated start data from slave

SDA

start id =32h w ack address = 3Fh ack rs r ack address 3Fh data nack stop

MSB Chip Address LSB

id = 32h

start MSB Chip Addr LSB w ack MSB Register Addr LSB ack MSB Data LSB ack stop

ack from slave ack from slave ack from slave

SCL

SDA

start id = 32h w ack addr = 40h ack ackaddress 40h data stop

ADR6bit7

ADR5bit6

ADR4bit5

ADR3bit4

ADR2bit3

ADR1bit2

ADR0bit1

R/Wbit0

MSB LSB

0 0 01 1 0 1

I2C Slave Address (chip address)

LP8501


Figure 26. LP8501 Chip Address

Figure 27. Write cycle (w = write; SDA = “0”) id = chip address = 32h for LP8501

When a READ function is to be accomplished, a WRITE function must precede the READ function, as show above.

Figure 28. Read cycle (r = read; SDA = "1"), id = chip address = 32h for LP8501

Control Register Write Cycle• Master device generates start condition.• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).• Slave device sends acknowledge signal if the slave address is correct• Master sends control register address (8 bits).• Slave sends acknowledge signal.• Master sends data byte to be written to the addressed register.• Slave sends acknowledge signal.• If master will send further data bytes, the slave’s control register address will be incremented by one after

acknowledge signal. In order to reduce program load time LP8501 supports address auto increment. Registeraddress is incremented after each 8 data bits. For example, the whole program memory page can be writtenin one serial bus write sequence. Note: serial bus address auto increment is not supported for registeraddresses from 16H to 1EH.

• Write cycle ends when the master creates stop condition.

Control Register Read Cycle• Master device generates a start condition.




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LP8501


• Master device sends slave address (7 bits) and the data direction bit (r/w = 0).• Slave device sends acknowledge signal if the slave address is correct• Master sends control register address (8 bits).• Slave sends acknowledge signal.• Master device generates repeated start condition.• Master sends the slave address (7 bits) and the data direction bit (r/w = 1).• Slave sends acknowledge signal if the slave address is correct.• Slave sends data byte from addressed register.• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition

Auto Increment FeatureThe auto increment feature allows writing several consecutive registers within one transmission. Every time an 8-bit word is sent to the LP8501, the internal address index counter will be incremented by one and the nextregister will be written. The table below shows writing sequence to two consecutive registers. The auto incrementfeature is enabled by writing the EN_AUTO_INCR bit high in the MISC register (address 36h). Note that theserial bus address auto increment is not supported for register addresses from 16h to 1Eh (PWM registers).

MASTER START CHIP WRITE REG DATA DATA STOPADDR = ADDR32H

LP8501 ACK ACK ACK ACK




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LP8501


LP8501 RegistersThe LP8501 is controlled by a set of registers through the two-wire serial interface port. Some register bits arereserved for future use. The table below lists device registers, their addresses, and their abbreviations. A moredetailed description is given in section.

Table 5. Control Register MapHex Register Name Bit(s) Read/Wr Default Value Bit Mnemonic and Description

Address ite After Reset00 ENABLE / ENGINE [6] R/W x0xxxxxx CHIP_EN

CNTRL1 0 = LP8501 not enabled1 = LP8501 enabled

[5:4] R/W xx00xxxx ENGINE1_EXECEngine 1 program execution control

[3:2] R/W xxxx00xx ENGINE2_EXECEngine 2 program execution control

[1:0] R/W xxxxxx00 ENGINE3_EXECEngine 3 program execution control

01 ENGINE CNTRL2 [5:4] R/W xx00xxxx ENGINE1_MODEENGINE 1 mode control

[3:2] R/W xxxx00xx ENGINE2_MODEENGINE 2 mode control

[1:0] R/W xxxxxx00 ENGINE3_MODEENGINE 3 mode control

02 GROUP 1 FADING [7:4] R/W 0000xxxx FADE_INFade-in time for group 1 fader

[3:0] R/W xxxx0000 FADE_OUTFade-in time for group 1 fader

03 GROUP 2 FADING [7:4 R/W 0000xxxx FADE_INFade-in time for group 2 fader


04 GROUP 3 FADING [7:4 R/W 0000xxxx FADE_INFade-in time for group 3 fader


05 POWER CONFIG [1] R/W xxxxxx0x CHP_CON_1_6D1 to D6 power selection

[0] R/W xxxxxxx0 CHP_CON_7_9D7 to D9 power selection

06 D1 CONTROL [7:6] R/W 00xxxxxx GROUP_SELECTFader group selection for D1 output

[5] R/W xx0xxxxx LOG_ENLogarithmic dimming control for D1

07 D2 CONTROL [7:6] R/W 00xxxxxx GROUP_SELECTFader group selection for D2 output

[5] R/W xx0xxxxx Logarithmic dimming control for D2 output08 D3 CONTROL [7:6] R/W 00xxxxxx GROUP_SELECT

Fader group selection for D3 output[5] R/W xx0xxxxx LOG_EN

Logarithmic dimming control for D3 output09 D4 CONTROL [7:6] R/W 00xxxxxx GROUP_SELECT


Logarithmic dimming control for D4 output0A D5 CONTROL [7:6] R/W 00xxxxxx GROUP_SELECT


Logarithmic dimming control for D5 output




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LP8501


Table 5. Control Register Map (continued)Hex Register Name Bit(s) Read/Wr Default Value Bit Mnemonic and Description

Address ite After Reset0B D6 CONTROL [7:6] R/W 00xxxxxx GROUP_SELECT


Logarithmic dimming control for D6 output0C D7 CONTROL [7:6] R/W 00xxxxxx GROUP_SELECT


Logarithmic dimming control for D7 output0D D8 CONTROL [7:6] R/W 00xxxxxx GROUP_SELECT


Logarithmic dimming control for D8 output0E D9 CONTROL [7:6] R/W 00xxxxxx GROUP_SELECT


Logarithmic dimming control for D9 output0F TO 14 RESERVED [7:0] RESERVED FOR FUTURE USE

15 GPO CONTROL [7:6] R/W 00xxxxxx GROUP_SELECTFader group selection for GPO

[5] R/W xx0xxxxx LOG_ENLogarithmic dimming control for GPO

16 D1 PWM [7:0] R/W 00000000 PWMPWM duty cycle control for D1




1A D5 PWM [7:0] R/W 00000000 PWMPWM duty cycle control for D5

1B D6 PWM [7:0] R/W 00000000 PWMPWM duty cycle control for D6

1C D7 PWM [7:0] R/W 00000000 PWMPWM duty cycle control for D7

1D D8 PWM [7:0] R/W 00000000 PWMPWM duty cycle control for D8

1E D9 PWM [7:0] R/W 00000000 PWMPWM duty cycle control for D9

1F TO 24 RESERVED [7:0] RESERVED FOR FUTURE USE25 GPO PWM [7:0] R/W 00000000 PWM

PWM duty cycle control for GPO26 D1 CURRENT CONTROL [7:0] R/W 10101111 CURRENT

D1 output current control register. Default 17.5 mA(typ.)

27 D2 CURRENT CONTROL [7:0] R/W 10101111 CURRENTD2 output current control register. Default 17.5 mA(typ.)

28 D3 CURRENT CONTROL [7:0] R/W 10101111 CURRENTD3 output current control register. Default 17.5 mA(typ.)

29 D4 CURRENT CONTROL [7:0] R/W 10101111 CURRENTD4 output current control register. Default current is17.5 mA (typ.)




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LP8501



Address ite After Reset2A D5 CURRENT CONTROL [7:0] R/W 10101111 CURRENT

D5 output current control register. Default current is17.5 mA (typ.)

2B D6 CURRENT CONTROL [7:0] R/W 10101111 CURRENTD6 output current control register. Default current is17.5 mA (typ.)

2C D7 CURRENT CONTROL [7:0] R/W 10101111 CURRENTD7 output current control register. Default current is17.5 mA (typ.)

2D D8 CURRENT CONTROL [7:0] R/W 10101111 CURRENTD8 output current control register. Default current is17.5 mA (typ.)

2E D9 CURRENT CONTROL [7:0] R/W 10101111 CURRENTD9 output current control register. Default current is17.5 mA (typ.)

2F TO 35 RESERVED FOR FUTURE [7:0] RESERVED FOR FUTURE USEUSE

36 CONFIG [7] R/W 0xxxxx0x PWM_POWERSAVEEnables PWM powersave option

[6] R/W x1xxxx0x EN_AUTO_INCRSerial bus address auto increment enable

[5] R/W xx0xxx0x POWERSAVE_ENPowersave mode enable

[4:3] R/W xxx00x0x CP_MODECharge pump gain selection

[2] R/W xxxxx00x FADE_TO_OFFAutomatic fade out enable

[1] R/W xxxxxx0x RESERVED Note that this bit should always be setto zero when writing register.

[0] R/W xxxxxx00 INT_CLK_ENLED Clock source selection

37 ENGINE1 PC [6:0] R/W x0000000 PCProgram counter for engine 1



3A STATUS/INTERRUPT [7] R 0xxxxxxx LED_TEST_MEASUREMENT_DONEIndicates when the LED test measurement is done.

[6] R x1xxxxxx MASK_BUSYMask bit for interrupt generated by START_UPBUSY or ENGINE_BUSY

[5] R xx0xxxxx START_UP BUSYThis bit indicates that the start-up sequence isrunning

[4] R xxx0xxxx ENGINE_BUSYThis bit indicates that a program execution engine isclearing internal registers

[3] R xxxx0xxx EXT_CLK_USEDIndicates when external clock signal bit is set

[2] R xxxxx0xx ENG1_INTInterrupt bit for program execution engine 1

[1] R xxxxxx0x ENG2_INTInterrupt bit for program execution engine 2

[0] R xxxxxxx0 ENG3_INTInterrupt bit for program execution engine 3




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LP8501



Address ite After Reset3B GPO [2] R/W xxxxx0xx INT_CONF

INT pin can be configured to function as a GPO withthis bit.

[1] R/W xxxxxx0x GPOGPO pin control

[0] R/W xxxxxxx0 INT_GPOGPO pin control for INT pin (when INT_CONF is setto '1')

3D RESET [7:0] R/W 00000000 RESETWriting 11111111 into this register resets the LP8501

41 LED TEST CONTROL [7] R/W 0xxxxxxx EN_LED_TEST_ADC[6] R/W x0xxxxxx EN_LED_TEST_INT[5] R/W xx0xxxxx LED_TEST_CONTINUOUS_CONV

Continuous LED test measurement selection[4:0] R/W xxx00000 LED_TEST_CTRL

Control bits for LED test42 LED TEST ADC [7:0] R N/A LED_TEST_ADC

LED test result48 GROUP FADER1 [7:0] R/W 00000000 GROUP FADER49 GROUP FADER2 [7:0] R/W 00000000 GROUP FADER4A GROUP FADER3 [7:0] R/W 00000000 GROUP FADER4C ENG1 PROG START [6:0] R/W x0000000 ADDR

ADDR4D ENG2 PROG START [6:0] R/W x0001000 ADDR

ADDR4E ENG3 PROG START [6:0] R/W x0010000 ADDR

ADDR4F PROG MEM PAGE SEL [2:0] R/W xxxxx000 PAGE_SEL




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LP8501



Address ite After Reset50 PROGRAM MEMORY [15:8] R/W 00000000

00h/10h/20h/30h/40h/50h51 [7:0] R/W 0000000052 PROGRAM MEMORY [15:8] R/W 00000000




04h/14h/24h/34h/44h/54h59 [7:0] R/W 000000005A PROGRAM MEMORY [15:8] R/W 00000000

05h/15h/25h/35h/45h/55h5B [7:0] R/W 000000005C PROGRAM MEMORY [15:8] R/W 00000000

CMD06h/16h/26h/36h/46h/56h5D [7:0] R/W 00000000 Every Instruction is 16-bit wide.The LP8501 can store 96 instructions. Each5E PROGRAM MEMORY [15:8] R/W 00000000instruction consists of 16 bits. Because one register07H/17H/27H/37H/47H/57H5F [7:0] R/W 00000000 has only 8 bits, one instruction requires two register

60 PROGRAM MEMORY [15:8] R/W 00000000 addresses. In order to reduce program load time the08h/18h/28h/38h/48h/58h LP8501 supports address auto-incrementation.61 [7:0] R/W 00000000 Register address is incremented after each 8 data

62 PROGRAM MEMORY [15:8] R/W 00000000 bits. Thus the whole program memory page can be09h/19h/29h/39h/49h/59h written in one serial bus write sequence.63 [7:0] R/W 00000000

64 PROGRAM MEMORY [15:8] R/W 000000000Ah/1Ah/2Ah/3Ah/4Ah/5Ah65 [7:0] R/W 00000000

66 PROGRAM MEMORY [15:8] R/W 000000000Bh/1Bh/2Bh/3Bh/4Bh/5Bh67 [7:0] R/W 00000000

68 PROGRAM MEMORY [15:8] R/W 000000000Ch/1Ch/2Ch/3Ch/4Ch/5Ch69 [7:0] R/W 00000000

6A PROGRAM MEMORY [15:8] R/W 000000000Dh/1Dh/2Dh/3Dh/4Dh/5Dh6B [7:0] R/W 00000000

6C PROGRAM MEMORY [15:8] R/W 000000000Eh/1Eh/2Eh/3Eh/4Eh/5Eh6D [7:0] R/W 00000000

6E PROGRAM MEMORY [15:8] R/W 000000000FH/1FH/2FH/3FH/4FH/5F6F [7:0] R/W 00000000H

76 GAIN CHANGE CONTROL [7:6] R/W 000xxxxx THRESHOLDThreshold voltage (typ.)00 — 400 mV01 — 300 mV10 — 200 mV11 — 100 mV

[5] R/W xx0xxxxx RESERVED BITWhen writing to register, write always '0'

[4:3] R/W xx000xxx TIMER00 — 5 ms01 — 10 ms10 — 50 ms11 — infinite

[2] R/W xx0xx0xx FORCE_1xActivates 1.5x to 1x timer




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LP8501


LP8501 Control Register Details00 ENABLE/ ENGINE CONTROL1• 00 - Bit [6] CHIP_EN

– 1 = internal startup sequence powers up all the needed internal blocks and the device enters normal mode– 0 = standby mode is entered. Control registers can be written or read (writing into PWM and Channel1–3

PC registers and to register 00h ENGINE1–3_EXEC bits is not possible).• 00 — Bits [5:4] ENGINE1_EXEC

– Engine 1 program execution control. Execution register bits define how the program is executed. Programstart address can be programmed to Program Counter (PC) register 37h.

– 00 = Hold: Hold causes the execution engine to finish the current instruction and then stop. Programcounter (PC) can be read or written only in this mode.

– 01 = Step: Execute the instruction at the location pointed by the PC, increment the PC by one and thenreset ENG1_EXEC bits to 00 (i.e. enter hold).

– 10 = Free Run: Start program execution from the instruction pointed by the PC.– 11 = Execute Once: Execute the instruction pointed by the current PC value and reset ENG1_EXEC to 00

(i.e. enter hold). The difference between step and executeonce is that executeonce does not incrementthe PC.

• 00 — Bits [3:2] ENGINE2_EXEC– Engine 2 program execution control. Equivalent to above definition of control bits. Program start address

can be programmed to Program Counter (PC) register 38h.• 00 — Bits [1:0] ENGINE3_EXEC

– Engine 3 program execution control. Equivalent to engine 1 control bits. Program start address can beprogrammed to Program Counter (PC) register 39h.

01 ENGINE CONTROL2• Operation modes are defined in this register.

– Disabled: Engines can be configured to disabled mode separately.– Load Program: Writing to program memory is allowed only when the engine is in load program operation

mode and engine busy bit (3Ah) is not set. Serial bus master should check the busy bit before writing toprogram memory. All the three engines are in hold while one or more engines are in load program mode.PWM values are frozen, also. Program execution continues when all the engines are out of load programmode. Load program mode resets the program counter of the respective engine. Loadprogram mode canbe entered from the disabledmode only. Entering loadprogram mode from the runprogram mode is notallowed.

– Run Program: Run program mode executes the instructions stored in the program memory. Executionregister (ENG1_EXEC etc.) bits define how the program is executed (hold, step, freerun or executeonce).Program start address can be programmed to Program Counter (PC) register. The Program Counter isreset to zero when the PC’s upper limit value is reached.

– Halt: Instruction execution aborts immediately and engine operation halts.• 01 — Bit [5:4] ENGINE1_MODE

– 00 = disabled– 01 = load program to SRAM, reset engine 1 PC– 10 = run program as defined by ENGINE1_EXEC bits– 11 = halt, halts program execution. Current command execution stopped

• 01 — Bits [3:2] ENGINE2_MODE– 00 = disabled– 01 = load program to SRAM, reset engine 2 PC– 10 = run program as defined by ENGINE2_EXEC bits– 11 = halt, halts program execution. Current command execution stopped

• 01 — Bits [1:0] ENGINE3_MODE– 00 = disabled– 01 = load program to SRAM, reset engine 3 PC




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LP8501


– 10 = run program as defined by ENGINE3_EXEC bits– 11 = halt, halts program execution. Current command execution stopped

• Note that changing mode from Run to Load is not allowed. Preferred sequence is 10 –> 00 –> 01.

02 GROUP 1 FADING• This is the register used to assign fade-in and fade-out times for group 1. Time can be set with 4 bits.• 02 — Bits [7:4] FADE_IN• 02 — Bits [3:0] FADE_OUT

FADE_IN/FADE_OUT Time, s0000 0.00001 0.050010 0.10011 0.20100 0.30101 0.40110 0.50111 0.61000 0.71001 0.81010 0.91011 1.01100 1.51101 2.01110 3.01111 4.0

03 GROUP 2 FADING• See GROUP 1 FADING

04 GROUP 3 FADING• See GROUP 1 FADING

05 POWER CONFIG• 05 — Bit [0] CHP_CON_7_9

– 1 = VDD7_9 should be connected to VOUT– 0 = VDD7_9 should be connected to VDD

• 05 — Bit [1] CHP_CON_1_6– 1 = VDD1_6 should be connected to VOUT– 0 = VDD1_6 should be connected to VDD

06 D1 CONTROL• This is the register used to assign the D1 output to the GROUP FADER group 1, 2, or 3, or none of them.

This register selects between linear and logarithmic PWM brightness adjustment. By using logarithmic PWMscale the visual effect looks like linear. Logarithmic adjustment converts internally an 8-bit PWM value to alogarithmic 12-bit value.

• 06 — Bit [7:6] GROUP_SELECT– 00 = No group fader set, clears group fader set for D1. Default setting.– 01 = Fader group 1 controls the D1 driver. The user can set the overall output of the group by the GROUP

1 FADER register at the address 48h and the fade-in/fade-out time by the GROUP 1 FADING register atthe address 02h.

– 10 = Fader group 2 controls the D1 driver. The user can set the overall output of the group by the GROUP2 FADER register at the address 49h and the fade-in/fade-out time by the GROUP 2 FADING register atthe address 03h.




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100

PW

M %

75

50

25

0

PWM Bits

00000000 10000000 11111111

LP8501


– 11 = Fader group 3 controls the D1 driver. The user can set the overall output of the group by the GROUP3 FADER register at the address 4Ah and the fade-in/fade-out time by the GROUP 3 FADING register atthe address 04h.

• 06 — Bit [5] LOG_EN– 0 = linear adjustment.– 1 = logarithmic adjustment.– This bit is effective for both the program execution engine control and direct PWM control.

07 D2 CONTROL to 0E D9 CONTROL• The control registers and control bits for D2 output to D9 output are similar to that given to D1.

15 GPO CONTROL• The control register and control bits for GPO output are similar to that given to D1.

16 D1 PWM• This is the PWM duty cycle control for D1 output. D1 PWM register is effective during direct control operation

- direct PWM control is active after power up by default. Note: serial bus address auto increment is notsupported for register addresses from 16 to 1E.

• 16 — Bits [7:0] PWM– 16 - Bits [7:0] PWM These bits set the D1 output PWM as shown in Figure 29 below.

Figure 29.

17 D2 PWM to 1E D9 PWM• PWM duty cycle control for outputs D2 to D9. The control registers and control bits for D2 output to D9 output

are similar to that given to D1.

25 GPO PWM• PWM duty cycle control for GPO. The control register and control bits for GPO are similar to that given to D1.

26 D1 OUTPUT CURRENT CONTROL• D1 LED driver current control register. The resolution is 8-bits and step size is 100 μA. .

CURRENT bits Output Current00000000 0.0 mA00000001 0.1 mA00000010 0.2 mA

... ...10101111 17.5 mA default setting

.... ....11111110 25.4 mA11111111 25.5 mA




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LP8501


27 D2 CURRENT CONTROL to 2E D9 CURRENT CONTROL• The control registers and control bits for D2 output up to D9 output are similar to that given to D1 output.

36 CONFIG• This register contains miscellaneous control bits.• 36 — Bit [7] PWM_POWERSAVE

– 1 = PWM powersave ON– 0 = PWM powersave OFF– See the Power Saving section for further details.

• 36 — Bit [6] EN_AUTO_INCR– The automatic increment feature of the serial bus address enables a quick memory write of successive

registers within one transmission.– 1 = serial bus address automatic increment is enabled.– 0 = serial bus address automatic increment is disabled.

• 36 — Bit [5] POWERSAVE_EN– 1 = power save mode is enabled.– 0 = power save mode is disabled. See the Power Saving section for further details.

• 36 — Bits [4:3] CP_MODE– Charge pump operation mode– 00 = OFF– 01 = forced to bypass mode (1x)– 10 = forced to 1.5x mode; output voltage is boosted to 4.5V.– 11 = automatic mode selection

• 36 — Bit [2] FADE_TO_OFF– Enables group fading when device is shut down through CHIP_EN.– 1 = Group fading ON.– 0 = Group fading OFF.

• 36 — Bit [1] RESERVED– This bit is reserved and should be written to zero.

• 36 — Bits [0] Clock selection bit– Program execution is clocked with internal 32 kHz clock or with external clock. Clocking is controlled with

bits [1:0] n the following way:– 0 = external clock source (CLK pin)– 1 = internal clock– External clock can be used if a clock signal is present on CLK-pin. External clock frequency must be 32

kHz for correct operation. If a higher or a lower frequency is used, it will affect on the program engineoperation speed.

– If external clock is not used in the application, CLK pin should be connected to GND to avoid oscillation onthis pin and extra current consumption.

37 ENGINE1 PC• 37 — Bits [6:0] PC

– Program counter starting value for program execution engine 1; A value from 0000000 to 1100000. Themaximum value depends on program memory allocation between the three program execution engines.


– Program counter starting value for program execution engine 2; A value from 0000000 to 1100000.


– Program counter starting value for program execution engine 3; A value from 0000000 to 1100000.

3A STATUS/INTERRUPTCopyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 39



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LP8501


• 3A — Bit [7] LED_TEST_MEASUREMENT_DONE– This bit indicates when the LED test is done, and the result is written to the LED TEST ADC register.

Typically the conversion takes 2.7 milliseconds to complete.– 1 = LED test done– 0 = LED test not done– This bit is a read-only bit, and it is cleared (to “0”) automatically after a read operation.

• 3A — Bit [6] MASK_BUSY– Mask bit for interrupts generated by STARTUP_BUSY or ENGINE_BUSY.– 1 = Interrupt events will be masked i.e. no external interrupt will be generated from STARTUP_BUSY or

ENGINE_BUSY event (default).– 0 = External interrupt will be generated when STARTUP_BUSY or ENGINE_BUSY condition is no longer

true. Reading the register 3Ah clears the status bits [5:4] and releases INT pin to high state.• 3A — Bit [5] STARTUP_BUSY

– A status bit which indicates that the device is running the internal start-up sequence. See Modes ofOperation for details.

– 1 = internal start-up sequence running. Note: STARTUP_BUSY = 1 always when CHIP_EN bit is '0'– 0 = internal start-up sequence completed

• 3A — Bit[4] ENGINE_BUSY– A status bit which indicates that a program execution engine is clearing internal registers. Serial bus

master should not write or read program memory or registers 00h, 01h, 37h to 39h or 4Ch to 4Eh, whenthis bit is set to '1'.

– 1 = at least one of the engines is clearing internal registers– 0 = engine ready

• 3A — Bit [3] EXT_CLK_USED– 1 = external clock bit is set– 0 = external clock bit is not set– This bit is high when external clock signal on CLK pin is set from register. Does not detect automatically

the external clock, only the bit selection from register 36h.• 3A — Bits [2:0] ENG1_INT, ENG2_INT, ENG3_INT

– 1 = interrupt set– 0 = interrupt not set/clear– Interrupt bits for program execution engine 1, 2 and 3, respectively. These bits are set by END instruction.

Reading the interrupt bit clears the interrupt.

3B GPO• LP8501 has one General Purpose Output pin (GPO). Status of the pin can be controlled with this register.

Also, INT pin can be configured to function as a GPO by setting the bit INT_CONF. When INT is configuredto function as a GPO, output level is defined by the VDD voltage.

• 3B — Bit [2] INT_CONF– 1 = INT pin is set to function as an interrupt pin (default).– 0 = INT pin is configured to function as a GPO.

• 3B — Bit [1] GPO– 0 =GPO pin state is low.– 1 = GPO pin state is high.– GPO pins are digital CMOS outputs, and no pull-up/down resistors are needed.

• 3B — Bit [0] GPO_INT– 0 = INT pin state is low (if INT_CONF = 1).– 1 = INT pin state is high (if INT_CONF = 1).– When INT pin’s GPO function is disabled, it operates as an open drain pin. INT signal is active low, i.e.

when interrupt signal is send, the pin is pulled to GND. External pull-up resistor is needed for properfunctionality.

3D RESET40 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated



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LP8501


• 3D — Bits [7:0] RESET– Writing 11111111 into this register resets the LP8501. Internal registers are reset to the default values.

Reading RESET register returns 00000000.

41 LED TEST CONTROL• LED test control register• 41 — Bit [7] EN_LEDTEST_ADC

– Writing this bit high (1) starts single LED test conversation. LED test measurement cycle is 2.7milliseconds.

• 41 — Bit [6] EN_LEDTEST_INT– 1 = interrupt signal will be send to the INT pin when the LED test is accomplished.– 0 = no interrupt signal will be send to the INT pin when the LED test is accomplished.– Interrupt can be cleared by reading STATUS/INTERRUPT register 3Ah.

• 41 — Bit [5] CONTINUOUS_CONV– 1 = Continuous LED test measurement. Not active in powersave mode.– 0 = Continuous conversion is disabled.

• 41 — Bits [4:0] LED__TEST_CTRL– These bits are used for choosing the LED driver output to be measured. VDD, INT-pin and charge-pump

output voltage can also be measured.

LED_TEST_CTRL bits Measurement00000 D100001 D200010 D300011 D400100 D500101 D600110 D7

000111 D801000 D9

01001 to 01110 Reserved01111 VOUT

10000 VDD

10001 INT-pin voltage10010 VDD1_610011 VDD7_9

10010 to 11111 N/A

42 LED TEST ADC• 42 — Bits [7:0 LED_TEST_ADC

– This is used to store the LED test result. Read-only register. LED test ADC least significant bitcorresponds to 30 mV. The measured voltage V (typ.) is calculated as follows: V = (RESULT(DEC) x 0.03-1.478 V. For example, if the result is 10100110 = 166(DEC), the measured voltage is 3.50V (typ.). SeeFigure 30 below.




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40 90 140 190

RESULT (DEC)

VO

LTA

GE

(V

)

5

4

3

2

1

0

LP8501


Figure 30.

48 GROUP FADER1• 48 — Bits [7:0] GROUP_FADER

– An 8-bit register to control all the LED-drivers mapped to GROUP FADER1. Group fader allows the userto control dimming of multiple LEDs with a single serial bus write. This is a faster method to control thedimming of multiple LEDs compared to the dimming done with the PWM registers (address 16h to 1Eh),which would need multiple writes.

49 GROUP FADER2• 49 — Bits [7:0] GROUP_FADER

– See GROUP FADER1 description.

4A GROUP FADER3• 4A — Bits [7:0]GROUP_FADER

– See GROUP FADER1 description.

4C ENGINE1 PROG START ADDR• Program memory allocation for program execution engines is defined with PROG START ADDR registers.• 4C — Bits [6:0] — ADDR

– Engine 1 program start address.

4D ENG2 PROG START ADDR• 4D — Bits [6:0] — ADDR


4E ENG3 PROG START ADDR• 4E — Bits [6:0] — ADDR


4F PROG MEM PAGE SELECT• 4F — Bits [2:0] — PAGE_SEL

– These bits select the program memory page. The program memory is divided into six pages of 16instructions; thus the total amount of the program memory is 96 instructions.

76 — GAIN CHANGE CONTROLNote that these controls have effect only in automatic mode.• 76 — Bits [7:6] — THRESHOLD

– Threshold voltage (typ.) pre-setting. Bits set the threshold voltage at which the charge pump gain changesfrom 1.5x to 1x. The threshold voltage is defined as the voltage difference between highest voltage output(D1 to D6) and input voltage VDD : VTHRESHOLD = VDD — MAX (voltage on D1 to D6).

– If VTHRESHOLD is larger than the set value (100 mV to 400 mV), the charge pump is in 1x mode.– 00 = 400 mV




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LP8501


– 01 = 300 mV– 10 = 200 mV– 11 = 100 mV– Note: Values above are typical and should not be used as product specification.– Note: Writing to THRESHOLD [7:6] bits by the user overrides factory settings. Factory settings are not

user accessible.– 76 — Bit [5] — RESERVED

– This bit is reserved for future use. When writing to register 76h, this bit should be written '0'.– 76 — Bits [4:3] — TIMER

– Automatic mode change from 1.5x to 1x is attempted at the interval specified with these bits. After thespecified interval time mode change to 1x is allowed if there is enough voltage over the LED drivers toensure proper operation. If FORCE_1x is set to '1' after the specified interval time 1x mode is alwaystested.

– 00 = 5 ms– 01 = 10 ms– 10 = 50 ms– 11 = infinite. The charge pump switches gain from 1x mode to 1.5x mode only. The gain reset back to

1x is enabled under certain conditions, for example in the powersave mode.– 76 — Bit [2] — FORCE_1x

– Activates forced mode change. In forced mode charge pump mode change from 1.5x to 1x isattempted at the interval specified with the TIMER bits.

– 1 = forced mode changes enabled– 0 = forced mode changes disabled




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LP8501


APPLICATIONS INFORMATION

Recommended External ComponentsThe LP8501 requires 4 external capacitors for proper operation. Surface-mount multi-layer ceramic capacitorsare recommended. Tantalum and aluminium capacitors are not recommended because of their high ESR. Forthe flying capacitors (C1 and C2) multi-layer ceramic capacitors should always be used. These capacitors aresmall, inexpensive and have very low equivalent series resistance (ESR <20 mΩ typ.). Ceramic capacitors withX7R or X5R temperature characteristic are preferred for use with the LP8501. These capacitors have tightcapacitance tolerance (as good as ±10%) and hold their value over temperature (X7R: ±15% over −55°C to125°C; X5R: ±15% over −55°C to 85°C). Capacitors with Y5V or Z5U temperature characteristic are generallynot recommended for use with the LP8501. Capacitors with these temperature characteristics typically have widecapacitance tolerance (+80%, −20%) and vary significantly over temperature (Y5V: +22%, -82% over −30°C to+85°C range; Z5U: +22%, −56% over +10°C to +85°C range). Under some conditions, a nominal 1 μF Y5V orZ5U capacitor could have a capacitance of only 0.1μF. Such detrimental deviation is likely to cause Y5V andZ5U capacitors to fail to meet the minimum capacitance requirements of the LP8501.

For proper operation it is necessary to have at least 0.24 µF of effective capacitance for each of the flyingcapacitors under all operating conditions. The output capacitor COUT directly affects the magnitude of the outputripple voltage. In general, the higher the value of COUT, the lower the output ripples magnitude. For properoperation it is necessary to have at least 0.50 µF of effective capacitance for CIN and COUT under all operatingconditions. The voltage rating of all four capacitors should be 6.3V; 10V is recommended.

The table below lists recommended external components from some leading ceramic capacitor manufacturers. Itis strongly recommended that the LP8501 circuit be thoroughly evaluated early in the design-in process with themass-production capacitors of choice. This will help ensure that any variability in capacitance does not negativelyimpact circuit performance.

Model Type Vendor Voltage Rating Package Size1 µF for COUT and CINC1005X5R1A105K Ceramic X5R TDK 10V 0402LMK105BJ105KV-F Ceramic X5R Taiyo Yuden 10V 0402ECJ0EB1A105M Ceramic X5R Panasonic 10V 0402ECJUVBPA105M Ceramic X5R, array Panasonic 10V 0504

of two470 nF for C1 and C2C1005X5R1A474K Ceramic X5R TDK 10V 0402LMK105BJ474KV-F Ceramic X5R Taiyo Yuden 10V 0402ECJ0EB0J474K Ceramic X5R Panasonic 6.3V 0402LEDs User defined.




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LP8501


REVISION HISTORY

Changes from Revision C (May 2013) to Revision D Page

• Changed layout of National Data Sheet to TI format; publish full data sheet to replace product brief .............................. 44




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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

LP8501TME/NOPB ACTIVE DSBGA YFQ 25 250 Green (RoHS& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -30 to 85 8501

LP8501TMX/NOPB ACTIVE DSBGA YFQ 25 3000 Green (RoHS& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -30 to 85 8501

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

http://www.ti.com/product/LP8501?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/LP8501?CMP=conv-poasamples#samplebuy

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PACKAGE OPTION ADDENDUM


Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

LP8501TME/NOPB DSBGA YFQ 25 250 178.0 8.4 2.43 2.48 0.75 4.0 8.0 Q1

LP8501TMX/NOPB DSBGA YFQ 25 3000 178.0 8.4 2.43 2.48 0.75 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LP8501TME/NOPB DSBGA YFQ 25 250 210.0 185.0 35.0

LP8501TMX/NOPB DSBGA YFQ 25 3000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 2

MECHANICAL DATA

YFQ0025xxx

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TMD25XXX (Rev C)

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.B. This drawing is subject to change without notice.

NOTES:

4215084/A 12/12

D0.600±0.075

E

D: Max =

E: Max =

2.29 mm, Min =

2.29 mm, Min =

2.23 mm

2.23 mm

IMPORTANT NOTICE

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lp8501 multi-purpose 9-output led driver (rev. d)

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