low power front end for the optical module of a neutrino underwater telescope

RD07 Florence-June 27-29, 200RD07 Florence-June 27-29, 20077

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[email protected]@ct.infn.it

Low Power Front End for the Optical Module Low Power Front End for the Optical Module of a Neutrino Underwater Telescopeof a Neutrino Underwater Telescope

D. Lo PrestiD. Lo Presti

University of Catania -Microelectronics GroupUniversity of Catania -Microelectronics Group

University of Bologna - Electronics GroupUniversity of Bologna - Electronics Group


2


SummarySummary

• Front end electronics for a KmFront end electronics for a Km3 3 submarine submarine neutrino detector:neutrino detector:– LIRA chipLIRA chip

• Test of the first prototype of the Front-end using Test of the first prototype of the Front-end using LIRA chip ( CT-BO ) LIRA chip ( CT-BO ) see F. Giorgi talksee F. Giorgi talk

– Study and design of the new front-endStudy and design of the new front-end– SpecificationsSpecifications– ArchitectureArchitecture– Status of workStatus of work


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AMS 0,35 AMS 0,35 m CMOS Technologym CMOS Technology

Europractice MPWEuropractice MPW

LIRA01 and LIRA02LIRA01 and LIRA02

Not Submitted to foundryNot Submitted to foundryLIRA03LIRA03

LIRA04LIRA04

LIRA05LIRA05

LIRA ChipLIRA Chip


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2 AM 200 MHz Write 10 MHz Read

PLL Stand Alone 400 MHz Slave Clock Generator

LIRA’s PLL Shielded

Trigger and Single Photon Classifier TSPC

LIRA05 CHIP CMOS 0,35 m AMS technology


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LIRA ChipLIRA Chip

• 2 SCA 3 ch.x256 cells working alternatively in 2 SCA 3 ch.x256 cells working alternatively in read and write mode to reduce dead timeread and write mode to reduce dead time– 200 MHz sampling 10 MHz transfer200 MHz sampling 10 MHz transfer– 9 bit resolution9 bit resolution– Anode and last dynode sampled (double linear Anode and last dynode sampled (double linear

dynamic)dynamic)– 20 MHz master clock sampled for time stamp20 MHz master clock sampled for time stamp

• Trigger and Single Photon ClassifierTrigger and Single Photon Classifier– 3 5-bit DAC with slow control interface3 5-bit DAC with slow control interface

• PLL to produce 200 MHz on chip PLL to produce 200 MHz on chip • 120 mW total power dissipation!!120 mW total power dissipation!!


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FPGAFPGASpartan 3ESpartan 3E

Socket chip Socket chip LIRALIRA

Front end Front end usingusing LIRA chip LIRA chip

ANALOGANALOG

DIGITALDIGITAL

Mezzanine di Mezzanine di debugdebug

See F. Giorgi talk


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SimulationsSimulations

• High energy neutrino events in NEMO High energy neutrino events in NEMO detectordetector

• 4040K spe background K spe background • Seawater Optical propertiesSeawater Optical properties• Optical module spacing, orientation and Optical module spacing, orientation and

positionposition• Hits in each pmt of the detector in Hits in each pmt of the detector in

presence of an eventpresence of an event


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Charge DynamicsCharge Dynamics

Maximum signals length spectra of three typical high energy events

Specialized Samplers

Time DynamicsTime Dynamics

p.e. spectra of three typical high energy neutrino events

Need for several input dynamics

0 20 40 60 80 100 1200

5

25Event n° 015. Intervals between first and last pulse

time (ns)

22 PMT10

15

20

1 1.5 2 2.5 3 3.5 40

5

10

15

20Event n° 015. Photoelectrons from photocatodes

22 PMT

p.e.

0 500 1000 1500 20000

20

40

60

80


time (ns)

216 PMT

0 500 1000 1500 2000 25000

50

100

150


216 PMT

p.e.

-1000 0 1000 2000 3000 4000 50000

10

20

30

40


time (ns)

440 PMT

0 5000 10000 150000

50

100

150

200

250

300


440 PMT

p.e.


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Study and Design of the Front-End Study and Design of the Front-End ElectronicsElectronics

• Simulation of neutrino events in a realistic detector (NEMO Simulation of neutrino events in a realistic detector (NEMO like)like)

• Simulation of the real Optical Module responseSimulation of the real Optical Module response

• Optimal Signal FilteringOptimal Signal Filtering

• Simulation of the Front-End chain with realistic Simulation of the Front-End chain with realistic performancesperformances

• Evaluation of the detector performances as regards to Evaluation of the detector performances as regards to acquisition parametersacquisition parameters

• Considerations on Power Dissipation and data flowConsiderations on Power Dissipation and data flow

• ASIC design ASIC design


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Filtered PMT Signal

Typical filtered signals (1, 9.3 and 94 p.e.).

A ¼ p.e. threshold gives a fluctuation of about 7 ns. We foresee to sample 2-3 leading

edge zeros and 2-3 trailing edge zeros. Signals must be delayed respect to trigger with

a delay line.

The filter is necessary to avoid aliasing at 200Msample/sec.Signals measured with PMTgain = 5.107. PMT works not linearly for high photons levels.

It is useful to reduce the PMT gain to achieve a greater linear dynamics.

Lower ageing of PMT!


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[email protected]@ct.infn.it4040K Rate vs Readout frequencyK Rate vs Readout frequency

Dead time vs. ADC freq.

10-1

100

101

102

10-1

100

101

102

even

ts lo

st (

%)

Sample frequency (MHz)

Rate 40K 500 = kHz. 10 cells/block

one block

two blocks

three blocks

four blocks

five blocks

six blocks

seven blocks

100 ps50 ps

2 ns

Four 10-cell block are able to limit dead time at reasonable dead time

We must use a buffer solution to limit dead time. A p.e. signal is long less than 40 ns. At 200Msample/sec we will use 10 cell blocks. We have simulated dead time vs block number for different

40K rates.


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10 p.e.10 p.e.

OutA OutB

OutC


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Gpmt=8.10610

610

710

8102

103

104

Gpm t

10 p

hoto

elec

tron

s T

ipic

al a

mpl

itude

(m

V) ZLoad, 300

106

107

10810

0

101

102

103

Gpmt

Cha

nnel

dyn

amic

s

ZLoad, 300

direct

2nd

3rd

0 10 20 30 40 50 6090

100

110

120

130

140

150

160

Gpmt (x10 6)

t, ps r m

s

Ck, 5ns; jt, 100psrms ; ZL oad, 300 ; Span, 1V; Ped, 1.5mVrm s ; ADC, 10 bit

0 10 20 30 40 50 60

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

Gpmt (x10 6)

q, %

Ck, 5ns; jt , 100psrms; ZLoad , 300; Spa n, 1V; Pe d, 1.5mVrms; ADC, 10 bit

0 10 20 30 40 50 60-0.55

-0.545

-0.54

-0.535

-0.53

-0.525

-0.52

-0.515

-0.51

Gpmt (x10 6)

syst

emat

ic e

rror

, p.e

.

Ck, 5ns; jt, 100psrms ; ZL oad, 300 ; Span, 1V; Ped, 1.5mVrm s ; ADC, 10 bit

10 p.e.10 p.e.


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General General RequirementsRequirements

Front End SpecificationsFront End Specifications

Low Power DissipationLow Power Dissipation < 500 mW in each Optical Module (MO) -> < 500 mW in each Optical Module (MO) -> Full-custom VLSI ASICFull-custom VLSI ASIC

FlexibilityFlexibility Acquisition param. by Slow ControlAcquisition param. by Slow Control

High Dynamic RangeHigh Dynamic RangeLinear Dynamic Range : Linear Dynamic Range : > 512 PE / 60 ns> 512 PE / 60 ns3 ranges: 8 PE / 60 ns; 64 PE / 60 ns; 512 PE/ 60 ns3 ranges: 8 PE / 60 ns; 64 PE / 60 ns; 512 PE/ 60 ns

Signal reconstruction up to 640nsSignal reconstruction up to 640ns

Time and chargeTime and charge 12000 PE / 10 12000 PE / 10 ss

Minimum Dead TimeMinimum Dead TimeDead Time < 1 nsDead Time < 1 nsBackground 30 KHz (Background 30 KHz (4040K in 10’’ PMT)K in 10’’ PMT)

Optimal ResolutionOptimal Resolution Time resolution 200 Time resolution 200 ÷300 ÷300 ps ps

Charge resolution 2 Charge resolution 2 ÷ 3 %÷ 3 %

Low CostLow Cost


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Optical Module Low Power Front-end Optical Module Low Power Front-end ArchitectureArchitecture

Anode

G1G1

G2G2

G3G3

Integrator

PMT

Interface

HV Control

Monitor

Serial Ctrl

SAS chipControl Unit

IN

MUX OUT

X10 PLL

FIFO

FADC

20 MHz

10 bit

FADC

20 MHz

10 bit

FPGAControl Unit

Slow Control Ext.

InterfaceOM

Connector

T&SPC

Class. Code

60ns

60ns

60ns

Serial Ctrl

Class.

Class.

MasterClock

CTRL+Data

CTRL+Data

Cust. EL.FPGAASIC

Data Pack & Transfer Unit


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PMT Interface Block DiagramPMT Interface Block Diagram PMT Interface

30 ns Delay lines

TSPC

Protection

Protection

Protection

-1

-1

-1

x1

/8

/64

R1

R2

R3

Filter

Filter

Filter

Delay

Delay

Delay

OUT AOUT A

OUT BOUT B

OUT BOUT B

Ra

Rb

Protection -1 Filter

IntegratorIntegrator

Rtot =

300

30MHz@ -3dB

100MHz@ -60dB

3MHz @ -3dB

10MHz @ -60dB

IC Delay Line 30 ns

x4

x4

x4

Pd 80 mWPd 80 mW


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PMT interface - PMT interface - measurements measurements

Integrator< 8 pe 8 pe ÷ 64 pe

64 pe ÷ 512 pe > 512 pe


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PMT interface - linearity

Limitazionex1

x1/8

x1/64

-0,50,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 4,0 4,5 5,0 5,5 6,0 6,5 7,0 7,5 8,0 8,5 9,0

0,0

0,2

0,4

0,6

0,8

1,0

1,2

1,4

1,6

OutAOutBOutC

Vo

ut

Vin

Test with 100mV ÷ 8,56 V equivalent to anode current pulse 333uA ÷ 28mA -> @ range 3pe ÷ 280 pe (5*106, 300)

PMT saturation @ 1nC = about 1250 pe (5*106, 300)


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PMT dynamic range VS GainPMT dynamic range VS Gain

1,00

10,00

100,00

1000,00

1,00E+00 1,00E+01 1,00E+02 1,00E+03 1,00E+04

numero fotoelettroni

nV/snVolts/s gain 5*10exp7

nVolts/s gain 10exp7

nVolts/s gain 5*10exp6

Number of photoelectrons

The effect of saturation seems to be determined by the anodic pulsed current and independent from the gain.

Limit Value of about 1 nC

120-150 p.e. @ gain 5·107

nVs

nVs @ gain 5·107

nVs @ gain 1·107

nVs @ gain 5·106

Fit of first 5 pts


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Trigger & Single Photon ClassifierTrigger & Single Photon Classifierblock diagramblock diagram

Out A

Out B

Out C

Th1

Th0

B2

B1

B0

SOT

• B0, B1, B2 = PMT signal classification codeB0, B1, B2 = PMT signal classification code

• SOT, Signal Over Threshold, twofold use:SOT, Signal Over Threshold, twofold use:

• Rising edge Trigger;Rising edge Trigger;

• SOT width determines sampling mode SOT width determines sampling mode (Short, Long, Integ.)(Short, Long, Integ.)

• Th0 e Th1 generated by 2 6-bit Th0 e Th1 generated by 2 6-bit DACDAC serial serial code (Slow Control).code (Slow Control).

• Th0 trigger threshold;Th0 trigger threshold;

• Th1 Out of range threshold.Th1 Out of range threshold.

• Asynchronous and always active.Asynchronous and always active.

Fast comparator with hysteresis


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An example…An example…

Th1

Th1

• @ t0 event trigger;

• t= t1 –t0 compared to Short

length (60 ns);

• If bigger after a Short also a Long sampling of the signal.

• The classification code is:

• B0=1; B1=0; B2=0.

• OutB samples will be converted!!

Th1

Th0

From PMT

From PMT Interface

Out A

Out B

Out C

t0 t1


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CHIP SAS - block diagramCHIP SAS - block diagram (Smart Autotriggering Sampler) (Smart Autotriggering Sampler)

Out AOut A

Out BOut B

Out COut C

b0,b1,b2,SOb0,b1,b2,SOTT

from TSPCfrom TSPC

3x163x16

3x16

3x16

3x16

3x128


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SamplingSampling• 3 sampling modes:3 sampling modes:

– SAS_SHORTSAS_SHORTo 4 independent memory banks: sampling @ START 4 independent memory banks: sampling @ START

(T&SPC)(T&SPC)– 3 channels 16 cells3 channels 16 cells– 200 MHz sampling 20 MHz transfer200 MHz sampling 20 MHz transfer– Serial transfer towards ADCSerial transfer towards ADC

– SAS_LONGSAS_LONGo T&SPC enabled: signal over Threshold more than 60 nsT&SPC enabled: signal over Threshold more than 60 ns

– 3 channels 128 cells3 channels 128 cells– 200 MHz sampling 20 MHz transfer200 MHz sampling 20 MHz transfer– Serial transfer towards ADCSerial transfer towards ADC

– FADC (external 10b 20 MHz ADC)FADC (external 10b 20 MHz ADC)o T&SPC enabled: signal over Threshold more than 640nsT&SPC enabled: signal over Threshold more than 640ns

– Integrated signalIntegrated signal– 10 bit 20 MHz Flash ADC10 bit 20 MHz Flash ADC– 1 Ksample record length1 Ksample record length


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Time Stamp MechanismTime Stamp Mechanism

InterpolationInterpolationsamplessamples

Time (ns)

Anode Anode signalsignal [V][V]

Time Time stampstamp

16 bit16 bitcountecounterr

4 bit4 bitcountecounterr

Time Stamp = 20 bit sent to data Time Stamp = 20 bit sent to data acquisitionacquisition

•One time stamp for samplerOne time stamp for sampler•Dedicated FIFODedicated FIFO

tt0 0 reconstructed offlinereconstructed offline

ThresholThresholdd T&SPC T&SPC

to


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Gpmt=8.106

ZL=300

0 500 10000

2

4

6

8

10

12

Ch1span

= 12 p.e.

Time [ns]

p.e

.

0 500 10000

10

20

30

40

50

60

70

Ch1span

= 70 p.e.

Time [ns]

p.e

.

0 500 10000

100

200

300

400

Ch1span

= 400 p.e.

Time [ns]

p.e

.

0 500 1000

0

100

200

300

400

500

600

700total 1602 p.e.

Time [ns]

p.e

.

p.e. meas. 1389

0 500 1000 15000

50

100

150

200

250

Time [ns]

Event 362. PMT 364. SCA 1

Max 677 p.e.

0 0.2 0.4 0.6

200

400

600

800

1000

1200

1400

1600 FWHM = 167.5 ns

p.e meas. 1610

20 M

Hz

AD

C in

put

Q/Q = 0.5 %

Time [ ]s


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Very rare event -> 5 successive pulses @ more than 50 ns

4 events fully sampled– 1 lost

Gpmt=8.106; ZL=300

0 200 400 600 8000

2

4

6

8

10

12

Ch1span

= 12 p.e.

time, ns

p.e.

0 200 400 600 8000

10

20

30

40

50

60

70

Ch1span

= 70 p.e.

time, ns

p.e.

0 200 400 600 8000

100

200

300

400

Ch1span

= 400 p.e.

time, ns

p.e.

0 200 400 600 800

0

0.5

1

1.5

2

2.5

3

3.5

total 54 p.e.

time, ns

p.e.

Photoelectrons measured 50

0 200 400 600 8001

1.2

1.4

1.6

1.8

2

time, ns


0 200 400 600 8000

2

4

6

8

10

12

Ch1span

= 12 p.e.

time, nsp.

e.

0 200 400 600 8000

10

20

30

40

50

60

70

Ch1span

= 70 p.e.

time, ns

p.e.

0 200 400 600 8000

100

200

300

400

Ch1span

= 400 p.e.

time, ns

p.e.

0 200 400 600 800

0

0.5

1

1.5

2

2.5

3

3.5

total 54 p.e.

time, ns

p.e.

Photoelectrons measured 50

0 200 400 600 8001

1.2

1.4

1.6

1.8

2

time, ns


Structured signal ->

well reconstructed with 128 cells


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0 500 1000 1500 20000

20

40

60

80


time, (ns)

0 500 1000 1500 2000 25000

50

100

150


0 50 100 150 200 25010

-1

100

101

102

103

104Event n° 290. SAS measures 4262 photoelectrons, ADC 8850. Sum 13112 of 13146. (%) -0.26

SCA Long consist of 3 channels of 128 cells.

The external ADC uses 20 samples.

Photoelectrons vs. PMT

BLU

E do

ts (f

rom

cat

odes

); R

ED c

ircle

s (S

CA

); R

ED

sta

rs (e

xter

nal A

DC

)

ADC

SCA

Gpmt=8.106; ZL=300

690 ns

In this event we have 13097 p.e.In this event we have 13097 p.e.

We are able to measure its charge using a We are able to measure its charge using a 128 SCA (640ns) with an error 128 SCA (640ns) with an error < 0.26%< 0.26%


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ConclusionsConclusions

• The front end electronics architecture has The front end electronics architecture has been defined and under design;been defined and under design;

• PMT interface and TSPC ready;PMT interface and TSPC ready;

• Master Control Unit (FPGA) ready;Master Control Unit (FPGA) ready;– See F. Giorgi talkSee F. Giorgi talk

• ASIC ready soon (beginning of 2008);ASIC ready soon (beginning of 2008);

• Test in NEMO phaseTest in NEMO phase 2 2


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Thank You

low power front end for the optical module of a neutrino underwater telescope

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