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EECS 427Lecture 3: CMOS review

EECS 427 F09 Lecture 3 1

Reading: 5.4, 6.2

Logistics

• CAD1 due today at 7pm• CAD2 assigned yesterday, due next Monday (9/21) at g y y, y ( )

7pm

• HW1 due next Wednesday (9/23) at the beginning of lecture

• HW1 readings: 3.5, 12.2, 5.4, 6.2.3

• HW2 due in 1.5 weeks– Email zhengya at eecs.umich.edu, subject line [EECS427

P j t G ] 1 il i l d b k d f hProject Group]: 1 email per group, include background of each person: grad/undergrad, area of interest/specialty: circuits, architecture, …

– Good to mix EE and CE, grad and undergrad, foreign and domestic, male and female


2

Outline

• Last time: layouts and design rules

• Register design for CAD2• CMOS inverter• DC and dynamic operations• Propagation delay• Static CMOS gates


• Fast gates design techniques

Register Design

Tri-state bufferTri state buffer

Transmission gate


3

Register Design

• How it worksWhen C is equal to 0, the master latch is transparent, and the salve latch is closed.

Master latch

Slave latch


Register Design

• How it worksWhen C is equal to 1, the master latch is closed, and the salve latch is

transparent When C switches from 0->1 (rising edge of the clock) the register captures the data .

Master latch

Slave latch


4

The CMOS InverterVDD

Vin Vout


CMOS Inverter VTCVout NMOS off

PMOS res

1.5

22.

5

NMOS satPMOS sat

NMOS satPMOS res

EECS 427 F09 Lecture 3 8Vin0.5 1 1.5 2 2.5

0.5

1

NMOS resPMOS off

NMOS resPMOS sat

5

Impact of Sizing

2.5

1

1.5

2V

ou

t(V)

Wider PMOS

Wider NMOS

Symmetrical


0 0.5 1 1.5 2 2.50

0.5

Vin

(V)

Impact of Process Variation2.5

1

1.5

2

Vo

ut(V

)

Fast PMOSSlow NMOS

Fast NMOSSlow PMOS

Nominal


0 0.5 1 1.5 2 2.50

0.5

Vin

(V)

6

MOS Transistor as a Switch

Discharging a capacitorDischarging a capacitor

C


MOS Transistor as a SwitchTraversed path

ID VGS = VDD

VGS ≥ VTRon D

VDS

VDDVDD /2

GS DD

Rmid

R0

S Don

Lecture 3 12

VDDVDD /2

2

112

2

112

21 )(

)(1)(

1))((

t

t D

DSt

ton

tttoneq dt

tItV

ttdttR

tttRavgR

)()(21

21 tRtRR ononeq

7

MOS Transistor as a Switch

VGS ≥ VTRon

ID VGS = VDD

S D

VDS

VDDVDD /2

Rmid

R0

mideq RRR 02

1

Lecture 3 13

21

212

1

DDDSAT

DD

DDDSAT

DDeq VI

VVI

VR

DD

DSAT

DDeq V

IV

R65

143

Gate-Channel CapacitanceG

CGC

G

CGC

G

CGC

S D S D S D

Cut-off Resistive Saturation

CGCB CGCS CGCD


Off/Lin Cgate = Cox·W·Leff

Textbook: page 109

Sat Cgate = (2/3)·Cox·W·Leff ox

oxox t

C

8

Gate Overlap CapacitancePolysilicon gatePolysilicon gate

xd xd

L d

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W

xd xd

L d

Top view

Gate-bulkoverlap

Source

n+

Drain

n+W

tox

n+ n+

Cross section

L

Gate oxidetox

n+ n+

Cross section

L

Gate oxide


doxO xCC

Top viewTop view

Off/Lin/Sat CGSO = CGDO = CO·W

Diffusion Capacitance

Side wall

NA+

Bottom

Side wallChannel

Source

Substrate

W

LS

ND

xj


NA

Cdiff = Cbottom + Csw

= Cj · AREA + Cjsw · PERIMETER

Off/Lin/Sat Cdiff = Cj·LS·W + Cjsw·(2LS+W)

9

Computing the Capacitances

VDD

VDD

13

Miller effect

M3

M4

M1

M2

Cw Cg3Cdb1

Cg4

Vout2

Cdb2

VinVout

Cgd12

2

3

Reverse

Off Sat (M4)

Lin (M3)

4

No Miller


FanoutVoutVin

CL

SimplifiedModel

biased junction

No Miller effect

Propagation Delay(Approach 1)

VDD

Vout

CLI

tpHL = CL Vswing/2

Iav

CL

kn VDD

~


Vin = VDD

CLIav kn VDD

10

Propagation Delay(Approach 2)

VDD

Vout

R

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

Vout

VDD1

ln(0.5)


Vin = VDD

Ron

t

DD

RonCL

0.5

0.36

Transient Response

3 ?

1

1.5

2

2.5

Vo

ut(V

)

tpHL = 0.69 CL Reqn

tpLH = 0.69 CL Reqp

?

tpLHtpHL


0 0.5 1 1.5 2 2.5

x 10-10

-0.5

0

0.5

t (sec)

11

Delay as a Function of VDD

5.5

2 5

3

3.5

4

4.5

5

t p(n

orm

aliz

ed

)


0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

VDD

(V)

Device Sizing

3.6

3.8x 10

-11

(for fixed load)

2.6

2.8

3

3.2

3.4

3.6

t p(s

ec)

( )

Self-loading effect:Intrinsic capacitancesdominate


2 4 6 8 10 12 142

2.2

2.4

S

dominate

12

PMOS/NMOS Ratio

5x 10

-11

4

4.5

t p(s

ec)

tpLH tpHL

tp = Wp/Wn


1 1.5 2 2.5 3 3.5 4 4.5 53

3.5

Input Rise Time0.35

t pH

L(n

sec

)

0.3

0.25

0.2


0.15

trise (nsec)10.80.60.40.20

tp = tstep(i) + tstep(i-1)

13

Static CMOS Circuits

At every point in time (except during the switching transients) each gate output is connected to eithertransients) each gate output is connected to eitherVDD or Vssvia a low-resistive path.

The outputs of the gates assume at all times the value of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods).

This is in contrast to the dynamic circuit style which


This is in contrast to the dynamic circuit style, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes.

Static CMOSVDD

I

F(In1,In2,…InN)

In1

In2

InN

In1

In2

InN

PUN

PDN

PMOS only

NMOS only


PUN and PDN are dual logic networksPUN and PDN functions are complementary

14

Threshold DropsVDD

PUNVDD

VS D

VDD 0PDN

0 VDD

CL

0 VDD - VTn

CL

VDD

VDD |VTp|

D SVGS

V


CLVDDCL

S

SD

D

VGS

NAND Gate


PDN: G = AB Conduction to GND

PUN: F = A + B = AB Conduction to VDD

G(In1,In2,In3,…) ≡ F(In1,In2,In3,…)

15

NOR Gate


Complex CMOS Gate

B

OUT = D + A • (B + C)

A

D

AC


D

B C

16

CMOS Properties

• Full rail-to-rail swing; high noise margins• Logic levels not dependent upon the relativeLogic levels not dependent upon the relative

device sizes; ratioless• Always a path to Vdd or Gnd in steady state;

low output impedance• Extremely high input resistance; nearly zero

steady-state input current


• No direct path steady state between power and ground; no static power dissipation

• Propagation delay function of load capacitance and resistance of transistors

Input Pattern Affects Delay

• Delay is dependent on th tt f i tthe pattern of inputs

• Low to high transition– both inputs go low

• delay is 0.69 Rp/2 CL

– one input goes low• delay is 0.69 Rp CL

CL

B

Rn

A

Rp

B

Rp

R


• High to low transition– both inputs go high

• delay is 0.69 2Rn CL

A

Rn Cint

17

Delay Dependence on Input Patterns

3Input Data Delay

0.5

1

1.5

2

2.5 A=B=10

A=1, B=10

A=1 0, B=1

Vol

tage

[V

]

Input Data

Pattern

Delay

(psec)

A=B=01 67

A=1, B=01 64

A= 01, B=1 61

A=B=10 45


-0.5

00 100 200 300 400

time [ps]

A=1, B=10 80

A= 10, B=1 81

NMOS = 0.5m/0.25 mPMOS = 0.75m/0.25 mCL = 100 fF

Transistor Sizing

R R R

CL

B

Rn

A

Rp

B

Rp

R

B

Rp

A

Rp

R R C

Cint

2

2 2 4

4


A

Rn Cint

A

Rn

B

Rn CL21

1

18

Transistor Sizing

OUT = D + A • (B + C)

D

A

B

C

4

4

8

8


D

A

B C

1

2

2 2

Transistor Sizing

OUT = D + A • (B + C)

D

A

B

C

6

3

6

6


D

A

B C

1

2

2 2

19

Fan-In Considerations

DCBA

C

B

A CL

C3

C2

Distributed RC model(Elmore delay)

tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)


D C1

pHL eqn( 1 2 3 L)

Propagation delay deteriorates rapidly as a function of fan-in – quadraticallyin the worst case.

Fast Gates Design Technique

• Transistor sizing– as long as fan-out capacitance dominates

• Progressive sizing

InN CLMNDistributed RC line

M1 > M2 > M3 > … > MN(the FET closest to the

EECS 427 F09 38

C3

C2

C1In1

In2

In3

M1

M2

M3

(the FET closest to theoutput is the smallest)

Can reduce delay by more than 20%; Be careful: input loading, junction caps, decreasing gains as technology shrinks

20


• Transistor ordering

C2In2

In3

M2

M3 CL

C2In2

In1

M2

M3 CL

critical path critical path

charged1

charged1

1

01 charged

discharged


C1In1 M1 C1

In3 M101

charged

delay determined by time to discharge CL, C1 and C2

delay determined by time to discharge CL

1 discharged


• Alternate logic structures

F = ABCDEFGH


21


• Isolating fan-in from fan-out using buffer insertion

CLCL



• Reducing the voltage swing

– linear reduction in delay– also reduces power consumption

B t th f ll i t i h l !

tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )

= 0.69 (3/4 (CL Vswing)/ IDSATn )


• But the following gate is much slower!• Or requires use of “sense amplifiers” on the

receiving end to restore the signal level (memory design)

22

Summary

• CMOS is the dominant circuit family due to:N i i– No static power consumption

– Ease of design

– Robust to variations and noise

• CAD2 due next Monday at 7 pm

• HW1 due next Wednesday at 1:30 pm


• Form a group. Email zhengya at eecs.umich.edu

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