logic functions and gates - cc.ntut.edu.tljkau/course/982/dd/chapter02.pdfdesignation. •...

45
1 Chapter 2 Logic Functions and Gates 2 Basic Logic Functions The three basic logic functions are: – AND – OR – NOT

Upload: truongnhi

Post on 13-May-2018

218 views

Category:

Documents


3 download

TRANSCRIPT

  • 1

    Chapter 2

    Logic Functions and Gates

    2

    Basic Logic Functions

    The three basic logic functions are: AND OR NOT

  • 2

    3

    Logic Function Representation

    Logic functions can be represented:algebraicallyusing truth tablesusing electronic circuits.

    4

    Algebraic Representation

    Uses Boolean algebra. Boolean variables have two states

    (binary). Boolean operatorsinclude

    AND, OR, and NOT.

  • 3

    5

    Truth Table Representation

    Defines the output of a function for every possible combination of inputs.

    A system with n inputs has 2n possible combinations.

    6

    Electronic Circuit Representation

    Uses logic gates to perform Boolean algebraic functions.

    Gates can be represented by schematic symbols.

    Symbols can be either distinctive-shapeor rectangular-outline.

  • 4

    7

    Distinctive Shape Schematic Symbols

    Uses different graphic representations for different logic functionsAND, OR, NOT.

    Uses a bubble (a small circle) to indicate a logical inversion.

    8

    Rectangular-Outline Schematic Symbols

    All functions are shown in rectangular form with the logic function indicated by standard notation inside the rectangle.

    The notation specifying the logic function is called the qualifying symbol.

    Inversion is indicated by a 1/2 arrowhead.

  • 5

    9

    NOT Function

    One input and one output. The output is the opposite logic level of

    the input. The output is the complement of the

    input.

    10

    NOT Function Boolean Representation

    Inversion is indicated by a bar over the signal to be inverted.

    AY =

  • 6

    11

    NOT Function Electronic Circuit

    Called a NOT gate or, more usually, an INVERTER.

    Distinctive-shape symbol is a triangle with inversion bubble.

    Rectangular-shape symbol uses 1 and the inversion 1/2 arrowhead.

    12

    NOT Function Electronic Circuit

  • 7

    13

    AND Function

    Two or more inputs, one output. Output is HIGH only when all of the

    inputs are HIGH. Output is LOW whenever any input is

    LOW.

    14

    111001010000YBA

    AND Function

  • 8

    15

    AND Boolean Representation

    AND symbol is or nothing at all.

    ABYB AY

    ==

    16

    AND Function Electronic Circuit

    Called an AND gate. Distinctive-shape symbol uses AND

    designation. Rectangular-shape symbol use & as

    designator.

  • 9

    17

    AND Function Electronic Circuit

    18

    AND Function Electronic Circuit

  • 10

    19

    0110000101010011

    1

    000A

    111

    001010000YCB

    AND Function Electronic Circuit

    20

    OR Function

    Two or more inputs, one output. Output is HIGH whenever one or more

    input is HIGH. Output is LOW only when all of the

    inputs are LOW.

  • 11

    21

    OR Function

    111

    101

    110

    000

    YBA

    22

    OR Boolean Representation

    OR symbol is +. Y = A + B

  • 12

    23

    OR Function Electronic Circuit

    Called an OR gate. Distinctive-shape symbol uses OR

    designation. Rectangular-shape symbol uses as

    designator.

    24

    OR Function Electronic Circuit

  • 13

    25

    Active Level

    The logic level defined as ON for a circuit.

    When a logic HIGH is ON, the signal is active-HIGH.

    When a logic LOW is ON, the signal is active-LOW.

    26

    NAND Function

    Generated by inverting the output of the AND function.

    Output is HIGH whenever any input is LOW.

    Output is LOW only when all inputs are HIGH.

  • 14

    27

    NAND Function

    011

    101

    110

    100

    YBA

    28

    NAND Boolean Representation

    Uses AND with an inversion overbar.

    BAY =

  • 15

    29

    NAND Function Electronic Circuit

    Called a NAND gate. Uses the AND symbol with inversion on.

    30

    NAND Function Electronic Circuit

  • 16

    31

    NOR Function

    Generated by inverting the output of the OR function.

    Output is HIGH only when all inputs are LOW.

    Outputs is LOW whenever any input is HIGH.

    32

    011

    001

    010

    100YBA

    NOR Function

  • 17

    33

    NOR Boolean Representation

    Uses OR with an inversion overbar.

    BA Y +=

    34

    NOR Function Electronic Circuit

    Called a NOR gate. Uses OR symbol with inversion on the

    output.

  • 18

    35

    NOR Function Electronic Circuit

    36

    3 Input NOR and NAND FunctionTruth Tables

    3 Input NAND:

    3 Input NOR:

    CBA Y =

    C B A Y ++=

  • 19

    37

    01111111

    0110000101010011

    1

    000A

    011

    001010100

    CB C B A ++CBA

    3 Input NOR and NAND FunctionTruth Tables

    38

    Exclusive OR Gate

    Two inputs, one output. Output is HIGH when one, and only one,

    input is HIGH. Output is LOW when both inputs are

    equal both HIGH or both LOW.

  • 20

    39

    Exclusive OR Gate

    40

    011

    101

    110

    000

    YBA

    Exclusive OR Gate

  • 21

    41

    Exclusive NOR Gate

    Two inputs, one output. Output is HIGH when both inputs are

    equal both HIGH or both LOW. Output is LOW when one, and only one,

    input is HIGH, i.e., the two inputs are different.

    42

    Exclusive NOR Gate

  • 22

    43

    111

    001

    010

    100YBA

    Exclusive NOR Gate

    44

    Gate Equivalence NAND

    A NAND gate can be represented by an AND gate with inverted output.

    A NAND gate can be represented by an OR gate with inverted inputs.

  • 23

    45

    Gate Equivalence NAND

    A

    B

    C

    D

    U1A

    14011

    1

    23

    U2A

    14011

    1

    23

    U3A

    14011

    1

    23

    Y

    B

    A

    C

    D

    U4A

    14071

    1

    23

    U6A

    14081

    1

    23

    U7A

    14081

    1

    23

    Y

    46

    Gate Equivalence NOR

    A NOR gate can be represented by an OR gate with inverted output.

    A NOR gate can be represented by an AND gate with inverted inputs.

  • 24

    47

    C

    D

    A

    B U8A

    14001

    1

    23

    U9A

    14001

    1

    23

    U10A

    14001

    1

    23

    Y

    C

    D

    B

    A

    U11A

    14071

    1

    23

    U12A

    14071

    1

    23

    U13A

    14081

    1

    23 Y

    Gate Equivalence NOR

    48

    Gate Equivalence DeMorgan Forms

    Change an AND function to an OR function and an OR function to an AND function.

    Invert the inputs. Invert the outputs.

    B

    A

    /B

    /A

    B

    /A

    A

    /B

    U14A

    14011

    1

    23

    U15A

    14071

    1

    23

    U18A

    14001

    1

    23

    U19A

    14081

    1

    23

    Y

    Y

    Y

    Y

  • 25

    49

    DeMorgans Theorem - 1

    Break the line and change the sign

    B A BA +=B A BA =+

    50

    DeMorgans Theorem - 2

    The following are two common errors associated with DeMorgans Theorem:

    B A BA ++

    B A BA

  • 26

    51

    Active Logic Levels

    Any INPUT or OUTPUT that has a BUBBLE is considered as active LOW.

    Any INPUT or OUTPUT that has no BUBBLE is considered as active HIGH.

    52

    Active Logic Levels - NOR

    At least one input HIGH makes the

    output LOW. All inputs LOW make the output HIGH.

    BA Y +=

    BA Y =

  • 27

    53

    Active Logic Levels - NOR

    54

    Logic Switches

    Provides a logic HIGH or LOW depending on switch position.

    Commonly used types include normally-open pushbutton, normally-closed pushbutton, single-pole single-throw, and single-pole double-throw.

  • 28

    55

    Logic Switches

    Open=>1Close=>0

    56

    Logic Switches

  • 29

    57

    Two-Pole Push Button

    Two-pole push button allows for normally HIGH and normally LOW levels from the same switch.

    58

    Two-Pole Push Button

  • 30

    59

    Light Emitting Diodes (LEDs)

    Used to indicate the status of a digital output.

    Has two terminals the anode and the cathode.

    If the anode is approximately 1.5 V greater than the cathode, current flows and the LED illuminates.

    60

    Light Emitting Diodes (LEDs)

    A C/K

  • 31

    61

    Light Emitting Diodes (LEDs)

    62

    Light Emitting Diodes

    Used to provide a visual indication of a logic state.

    Can be wired to display active-HIGH or active-LOW.

    Whats the common rated current flow through the diode? About 10mA

  • 32

    63

    Light Emitting Diodes

    64

    Light Emitting Diodes

  • 33

    65

    Logic Gate Enable

    The input to a gate that allows the output to respond to other inputs.

    A logic LOW for an OR or NOR gate, a logic HIGH for an AND or NAND gate.

    Somewhat like a controlled switch.

    66

    VCC

    VCCJump

    CarrierDout Q11384

    CB

    E

    D1

    JP4HEADER 2

    12

    C3102/100V

    R25

    470

    R224.7

    U5B

    4011

    5

    64

    U5A

    4011

    1

    23

    R24SVR10K

    13

    2

    R2610K

    R212K

    R231M

    Control Input

    DIP14 DIP14May be replaced by 3904.E B C1 2 3

    Logic Gate Enable

  • 34

    67

    Logic Gate Inhibit

    The input to a gate that forces the output to ignore any other input.

    A logic HIGH for an OR or NOR gate, a logic LOW for an AND or NAND gate.

    68

    Logic Gate Inhibit

  • 35

    69

    Logic Gate Inhibit

    70

    Logic Gate Inhibit

  • 36

    71

    Logic Gate InhibitNote: P.51 Textbook Error; Forgot to add a inverter in the output terminal

    72

    Logic Gate Inhibit

  • 37

    73

    Logic Gate Inhibit

    74

    Y = 1

    Y = B

    OR

    Y = 1

    NAND

    Y = 0

    NOR

    Y = B

    XOR

    A = 1

    A = 0

    Control

    Y = BY = B

    Y = 0

    XNORAND

    BY =

    BY =BY =

    B Y =

    Logic Gate Inhibit

    NAND, NOR, XNORAND, OR, NOR

  • 38

    75

    Tristate Buffer

    Three output states, HIGH, LOW and high-impedance.

    Requires a separate input to control which output state is selected.

    76

    Tristate Buffer

  • 39

    77

    Tristate Buffer

    Active Low!

    78

    Tristate Buffer Utilization

    Used to connect multiple outputs togetherAn action that requires highly attention!.

    Used in controlling the operation of buses.

  • 40

    79

    Tristate Buffer Utilization

    80

    The 74LS244 Octal Tri-State Buffer

    Contains two groups of four non-inverting tri-state buffers.

    Each group is controlled by a separate enable input, i.e., .G

  • 41

    81

    The 74LS244 Octal Tri-State Buffer

    82

    Integrated Circuit Package

    Integrated Circuits (ICs) contain many components in a single package.

    Several packaging options are available. One common package is called dual-in-

    line (DIP).

  • 42

    83

    Integrated Circuit Package

    84

    Integrated Circuit Technology

    One common form is transistor-transistor logic, called TTL.

    The other common form is Complementary Metal-Oxide Semiconductor, called CMOS.

  • 43

    85

    Low-voltage CMOS74LVX00

    Advanced low-power Schottky TTL74ALS00FAST TTL74F00

    Advanced BiCMOS (TTL/CMOS hybrid)74ABT00

    High-speed CMOS (TTL-compatible inputs)74CT00High-speed CMOS74HC00

    Low-power Schottky TTL74LS00Logic FamilyPart Number

    Integrated Circuit Technology

    86

    Integrated Circuit Designation

    Standard form is 74XXFF, where 74 is the logic family identifier, XX is the logic family member and FF identifies the specific logic function.

    SN74ALS00N

  • 44

    87

    IC Package Options

    PLCC - plastic lead chip carrier SOIC - small outline integrated circuit TSSOP thin shrink small outline

    package QFP quad flat pack DIP dual inline package BGA ball grid array

    88

    IC Package Options

    SOICTSSOP

    PLCC

    DIP BGA

  • 45

    89

    PLCC 84 Pin Packages Can be mounted on the surface of a

    circuit board or mounted in a socket. Pins are equally distributed on four sides. Pin 1 placed on the center of one of the

    rows, as indicated by a dot. Pins number counterclockwise from this

    point.

    90

    PLCC 84 Pin Packages

    /ColorImageDict > /JPEG2000ColorACSImageDict > /JPEG2000ColorImageDict > /AntiAliasGrayImages false /CropGrayImages true /GrayImageMinResolution 300 /GrayImageMinResolutionPolicy /OK /DownsampleGrayImages true /GrayImageDownsampleType /Bicubic /GrayImageResolution 300 /GrayImageDepth -1 /GrayImageMinDownsampleDepth 2 /GrayImageDownsampleThreshold 1.50000 /EncodeGrayImages true /GrayImageFilter /DCTEncode /AutoFilterGrayImages true /GrayImageAutoFilterStrategy /JPEG /GrayACSImageDict > /GrayImageDict > /JPEG2000GrayACSImageDict > /JPEG2000GrayImageDict > /AntiAliasMonoImages false /CropMonoImages true /MonoImageMinResolution 1200 /MonoImageMinResolutionPolicy /OK /DownsampleMonoImages true /MonoImageDownsampleType /Bicubic /MonoImageResolution 1200 /MonoImageDepth -1 /MonoImageDownsampleThreshold 1.50000 /EncodeMonoImages true /MonoImageFilter /CCITTFaxEncode /MonoImageDict > /AllowPSXObjects false /CheckCompliance [ /None ] /PDFX1aCheck false /PDFX3Check false /PDFXCompliantPDFOnly false /PDFXNoTrimBoxError true /PDFXTrimBoxToMediaBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXSetBleedBoxToMediaBox true /PDFXBleedBoxToTrimBoxOffset [ 0.00000 0.00000 0.00000 0.00000 ] /PDFXOutputIntentProfile () /PDFXOutputConditionIdentifier () /PDFXOutputCondition () /PDFXRegistryName () /PDFXTrapped /False

    /Description > /Namespace [ (Adobe) (Common) (1.0) ] /OtherNamespaces [ > /FormElements false /GenerateStructure true /IncludeBookmarks false /IncludeHyperlinks false /IncludeInteractive false /IncludeLayers false /IncludeProfiles true /MultimediaHandling /UseObjectSettings /Namespace [ (Adobe) (CreativeSuite) (2.0) ] /PDFXOutputIntentProfileSelector /NA /PreserveEditing true /UntaggedCMYKHandling /LeaveUntagged /UntaggedRGBHandling /LeaveUntagged /UseDocumentBleed false >> ]>> setdistillerparams> setpagedevice