DIGITAL LOGIC DESIGN IC TESTER

1. SYNOPSIS

The chip tester verifies the functionality and timing of a variety of 7400 series integrated circuits. Students taking Digital Logic Design Lab, Use these chips often in their laboratory. The IC to be tested should be placed on the ZIF socket and the Microcontroller prompts the user to enter the IC number of the chip to be tested. After entering it the microcontroller will check the IC as per the truth table of the IC which is stored in its ROM. It will check each and every pin of the IC and produce the Output detail. Like Gate is bad, Counter 1 is good etc,

2. BLOCK DIAGRAM

TRANSFORMERREGULATORRECTIFIER

MATRIX KEYPADLCD DRIVERMICROCONTROLLER 8051

ZIF SOCKET

RESET CIRCUIT

OSCILLATOR CIRCUIT

LCD 3. 8051

The complete description regarding the interrupt structure of 8051 is given in chapter-5, INTERRUPTS of this manual.

3.1. MEMORY ORGANISATION OF 8051:8051 has got separate address spaces for program and data memory.

3.2. PROGRAM MEMORY:

A program memory is a block of memory which can be used to store a sequence of program codes. It can only be read from and not written into, under normal operating conditions.

There can be upto 64k bytes of program memory in 8051. in ROM and EPROM versions of these devices, if the special control signal EA* (External Access enable) to the appendix at the back of this manual for pin details is strapped to Vcc, then program fetches to addresses 000 to 0FFF are directed to the internal ROM. The program fetch will be from external memory, when EA* is grounded.

After reset, the CPU begins execution from address location 0000 of the program memory.3.3. DATA MEMORY:

Data memory is the Read/Write memory. Hence, it can be both read from and written into 8051 has got 128 bytes of internal data memory and 64k of external data memory.

3.4. INTERNAL DATA MEMORY:

Internal data memory addresses are one byte wide which includes 128 bytes of on-chip RAM plus a number of special function registers. The 128 bytes of RAM can be accessed either by direct addressing or by indirect addressing.

The lowest 32 bytes (00-1F) of on-chip RAM are grouped into 4 banks of 8 register each. Program instructions call out these registers as RO through R7. bits 3 and 4 in register bank is in use. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing.

Reset initializes the stack pointer register to 7 and it is incremented once to start from location 08, which is register R0 of second register bank. Hence, in order to use more than one register bank, the stack pointer should be initialized to a different location of RAM where it is not used for data storage.

3.5. EXTERNAL DATA MEMORY:

There can be upto 64k bytes of data memory external to the chip. External data memory addresses can be either 1 or 2 bytes wide depending on the addressing mode. The MOVX instruction can be used to access the external data memory.

External program and data memory may be combained, if desired, by enabling the external memory devices for both RD* and PSEN* cycles.

3.6. I/O STRUCTURE OF 8051:

a) PARALLEL PORT:

8051 has four 8-bit parallel ports. All four parallel ports are bi-directional. Each line consists of a latch, an output driver and an input buffer.

The four ports are named as port 0 (p0), port 1(p1), port 2(p2) and port 3 (p3a). they are bit addressable and has to be represented in the form PX, Y i.e. bit Y of port X while using bit addressing mode. PX.0 is the LSB (Least Significant Bit) of port X and PX.7 is the MSB (Most significant bit) of that port. Out of the four ports, port 0 and port 2 are used in accesses to external memory. All the port 3 pins are multifunctional. They are not only port pins, but also serve the functions of various special features as listed in Table-1.

The alternate functions can only be activated if the corresponding bit latch in the port SFR (Special Function Register) contains a1. Otherwise, the port pin is stuck at 0. Hence, only port 1 is available exclusively for the user. Port 3 pins can be used if their alternate functions are not used.

The output drivers of port 0 and port 2 and the input buffers of port 0 are used in accesses to external memory, port 0 outputs the low byte of the external memory address, time-multiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16-bits wide. Otherwise, port 2 pins continue to emit the p2 SFR content.

Port pin Alternate Function

P3.0P3.1P3.2P3.3P3.4P3.5P3.6

P3.7RxD (serial input port)TxD (Serial output port)INT0 (External interrupt 0)INT1 (External interrupt 1)T0 (Timer/counter 0 external input)T1 (Timer/counter 1 external input)WR (External data memory write strobe)RD (External data memory read strobe)

NOTE:For the complete details of various registers mentioned in the following sections, please refer to the section Registers of 8051 of this chapter.

b) TIMER/COUNTERS:

8051 has two 126-bit timer/counters namely Timer / counter 0 and timer / counter 1. they can be configured in any of the four operating modes, which are selected by bit modes 0,1 and 2 are the same for both the timer/counters. Mode 3 is different.

MODE 0:

Either Timer in mode 0 is an 8-bit counter with a divide-by-32 prescaler. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all is to all 0s, it sets the timer interrupt flag TF1.

The 12-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1 and the lower 5 bits of TL1. the upper 3 bits of TL1 are indeterminate and should be ignored. Setting the run flag TR1 does not clear the registers.

MODE 2:

Mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits.

MODE 2:

Mode 2 configures the Timer register as an 8-bit counter (TL1) with automatic reload. Overflow from TL1 not only sets TF1, but also reloads TL1 with the contents of TH1, which is preset by software. The reloads leave TH1 unchanged. Mode 2 operation is the same for timer 0 and 1.

MODE 3:

Timer 1 in mode 3 simply holds its count. The effect is the same as setting TR1 =0. Timer 0 in mode 3 establishes TL0 and TH0 as two separate counters.

c) SERIAL PORT:

The 8051 has a full Duplex Serial Port, meaning it can transmit and receive simultaneously received byte has been read from the receive register. The serial port receive and transmit registers are both accessed at special function register SBUF (Serial data Buffer). Writing to SUBF loads the transmit register. The serial port of 8051 can be employed in four modes, the details of which are presented below.

MODE 0:Mode 0 has a fixed baud rate which is 1/12 of the crystal oscillator frequency. To run the serial port in this mode, one of the timer/counters need to be set up only the SCON register needs to be defined.

Serial data enters and exists through RxD (Receive data). Tx D (Transmit Data) outputs the shift clock. 8 bits are transmitted/received with LSB taking the leading position.

MODE 1:

10 bits are transmitted or received: a start bit(0), 8 data bits and a stop bit(1). On receive, the stop bit goes into RB8 in special function register SCON. The Baud rate is variable. The baud rate can be generated by timer 0 and timer 1.

MODE 2: 11 bits are transmitted (through TxD) or received (through RxD); a start bit (0), 8 data bits (LSB), a programmable 9th data bit and a stop bit (1). on transmit, the 9th data bit can be assigned the value of 0 or 1. or, for example, the parity bit goes into RB8 in the special function registers SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the crystal oscillator frequency.MODE 3:

11 bits are transmitted (through TXD) or received (through RXD): a start bit (0) , 8 data bits (LSB first) , a programmable 9th data bit and a stop bit (1). Infact , Mode 3 is the same as Mode 2 in all respect in all respects expect the baud rate . The baud rate in Mode 3 is variable.

NOTE:

Please refer to Chapter 4, for generating baud rates using the on chip timer of 8051 , to access the onchip serial port in various modes, under the heading Onchip features of 8051.

3.7. REGSISTERS OF 8051.

The various special function registers available in the internal data memory 8051 are listed in Table 2. The table also indicated whether each one is only byte addressable or byte and bit addressable (marked with an asterisk *) and the addresses of those registers (i.e., On-chip RAM address.)

TABLE -2.

SYMBOL OF SFRNAME OF THE SFRADDRESS

*ACC*B*PSWSPDPTRDPLDPH*P0*P1*P2*P3*IP*IETMOD*TCONACCUMULATORB REGISTERPROGRAM STATUS WORDSTACK POINTERDATA POINTER 2 YTESLOW BYTEHIGH BYTEPORT 0PORT 1PORT 2PORT 3INTERRUPT PRIORITY CONTROLINTERRUPT ENABLE CONTROLTIMER/COUNTER MODE CONTROLTIMER/COUNTER CONTROLE0F0D081

82838090A0B0B8A88988

TABLE-2

SYMBOLNAMEADDRESS

TH0TL0TH1TL1*SCONSBUFPCONTIMER/COUNTER 0 HIGH BYTETIMER/COUNTER 0 LOW BYTETIMER/COUNTER 1 HIGH BYTETIMER/COUNTER 1 LOW BYTESERIAL CONTROLSERIAL DATA BUFFERPOWER CONTROL8C8A8D8B989987

Bit Addressable.

3.8. ACCUMULATOR:

ACC is the Accumulator register, The mnemonics for Accumulator-Specific instructions, however refer to the Accumulator as simply A. Accumulator is an important Register on which various special operations such as reading from or writing to an external memory , rotation , addition, subtraction, multiplication, division and various other operations can be done.

B REGISTER

Register B is used during multiply and drive operations. For other instructions, it can be treated as another scratch pad register.

PROGRAM STATUS WORD:

The PSW register contains several status bits that reflect the current state of the CPU. It contains the carry bit, the Auxillary carry bit, two register bank select bits, the over flow flag, the parity bit and two user-definable status flags. This register is bit addressable.

CYACF0RS1RS0OV -PD7D6D5D4D3D2D1D0

CYPSW.7Carry FlagACPSW.6Auxillary Carry FlagF0PSW.5Flag 0 available to the userRS1PSW.4Register bank selector BIT 1RS0PSW.3Register bank selector BIT 0OVPSW.2Over flow Flag -PSW.1User definable Flag PPSW.0Parity flag. Set/cleared by hardware after the execution of each instruction to indicate odd/even number of 1 bits in the accumulator.

NOTE:The value of RS0 and RS1 select the onchip register banks.RS1RS0REGISTER BANKADDRESS

00110101012300 0708 0F10 1718 1F

3.9. STACK POINTER:

The stack pointer register is 8 bits wide. It is incremented before data is stored during the execution of PUSH and CALL instructions. While the stackmay reside anywhere in the on-chip RAM, the stack pointer is initialized to 07 after a RESET. This causes the stack to begin at location 08.

3.10. DATA POINTER:

The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended function is to hold a 16-bit address for external memory access. It may be manipulated as a 16-bity register or as two independent 8-bit registers.

PORTS 0 TO 3:Port 0, port 1, port 2 and port 3 are the SFR latches of ports 0, 1, 2 and 3 respectively.

3.11. SERIAL DATA BUFFER:

The serial data buffer is actually two separate registers, a transmit buffer and a receive buffer register when data is written to SUBF, it goes to the transmit buffer where it is held for serial transmission. When data is read from SBUF, it comes from the receive buffer.

3.12. TIMER REGISTERS:

Register pairs (TH0, TL0), (TH1, TL1) are the 16-bit counting registers for Timer/counters 0 and 1 respectively.

3.13. CONTROL REGISTERS:

Special function registers IP, IE, TMOD, TCON, SCON and PCON contain control and status bits for the interrupt system, the Timer/counters and the serial port.3.14. PCON: POWER CONTROL REGISTER:

Bit 7 of PCON register is used to control the baud clock generated from the timer. In the case of 80C51BH, PCON register can be used to select the power down mode and Idle mode of operation. Please refer to the Intel data sheets of 80C51BH for the complete details of the above said modes. This register is not bit addressable.

Smod---GF1GF0PDIDLD7D6D5D4D3D2D1D0

SMO- Double baud rate bit. If timer 1 is used to generate baud rate and SMOD = 1, the baud rate is doubled when the serial port is used in modes 1, 2 or Bits 4,5,6- Not implemented, reserved for future use. User software should not write is to reserved bits. GF1, GF0- User definable, general purpose flag bits.PD- Power down bit. Setting this bit activates power down operation in the 80C51BH. In rest of the microcontrollers, PD and IDL bits does not serve any purpose.IDL- Idle mode bit. Setting this bit activates Idle mode operation of 80C51BH.If is are written to PD and IDL at the same time, PD takes precedence.3.15. IE: INTERRUPT ENABLE REGISTER:

IE register, with its bit addressing capability, is used to enable/disable all or any of the interrupts of 8051. if the bit is 0, the corresponding interrupt is disabled. If the bit is 1, the corresponding interrupt is enabled.

D7D6D5D4D3D2D1D0

EA-ET2ESET1EX1ET0EX0

EAIE.7- Diables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.IE.6- Not implemented, reserved for future use.ET2IE.5- Enable or disable the timer 2 overflow interrupt.ESIE.4- Enable or disable the serial port interruptET1IE.3- Enable or disable the timer 1 overflow interrupt.EX1IE.2- Enable or disable the external interrupt 1.ET0IE.1- Enable or disable the timer 0 overflow interrupt.EX0IE.0- Enable or disable the external interrupt 0.3.16. IP: INTERRUPT PRIORITY REGISTER:

IP register is used to assign the priority for the interrupts of 8051. if the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1, the corresponding interrupt has a higher priority. Bit addressing is allowed with this register also.

D7D6D5D4D3D2D1D0

--PT2PSPT1PX1PT0PX0

IP.7,IP.6- Not implemented, reserved for future use.PT2IP.5- Defines the timer 2 interrupt priorityPSIP.4- Defines the Serial port interrupt priorityPT1IP.3- Defines the Timer 1 interrupt 1 priorityPX1IP.2- Defines External interrupt 1 priorityPT0IP.1- Defines the Timer 0 interrupt priorityPX0IP.0- Defines External Interrupt 0 priority.

3.17. TCON: TIMER/COUNTER CONTROL REGISTER:TCON register is used to control the entire operation of the timer/counters of 8051. This register can also be bit addressed.

TF1TR1TF0TR0IE1IT1IE0IT0D7D6D5D4D3D2D1D0

TF1TCON.7- Timer 1 overflow flag. Set by hardware when the Timer/Counter 1 over flows. Cleared by hardware as the processor vectors to the interrupt service routine.

TR1TCON.6- Timer 1 run control bit. Set/cleared by software to turn Timer/Counter 1 ON/OFF.

TF0TCON.5- Timer 0 overflow flag. Set by hardware when the Timer/counter 0 overflows. Cleared by hardware as the processor vectors to the service routine.

TR0TCON.4- Timer 0 run control bit. Set/cleared by software to turn Timer/counter 0 ON/OFF.IE1TCON.3- External interrupt 1 edge flag. Set by hardware when external interrupt edge is detected. Cleared by hardware when interrupt is processed.IT1TCON.2- Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt.

IE0TCON.1- External Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared by hardware when interrupt is processed.

IT0TCON.0- Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupt.

TMOD: TIMER/COUNTER MODE CONTROLS REGISTER. NOT BIT ADDRESSABLE:TMOD register is used to specify the mode of operation of Timers / counters of 8051.D7D6D5D4D3D2D1D0

GATE C/T* M1 M0 GATE C/T* M1 M0

TIMER 1TIMER 0GATE- When TRx is set and GATE =1, TIMER/COUNTERx will runonlywhile INTx pin is high. When GATE =0, TIMER/COUNTERx will run only while TRx = 1C/T*- Timer or counter selector, cleared for timer operation. Set for counter operation.M1,M0- Mode selector bit.

3.18. SCON: SERIAL PORT CONTROL REGISTER. BIT ADDRESSABLE:

SCON register is used to specify the mode in which the serial port is to work. TI (Transmit interrupt) / RI (Receiver Interrupt) flag(s) of SCON register can be used to check whether the transmission/reception is over.

SM0SM1 SM2RENTB8RB8TI RID7D6D5D4D3D2D1D0

SM0, SM1SCON.7, SCON.6- Serial port mode specifier.

SM2SCON.5- Enables the multiprocessor communication feature in modes 2 &3. in mode 2 or 3, if SM2 is set to 1, then RI will not be activated if the received 9th data bit (RB8) is0. in mode 1, if SM2 = 1, then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0.RENSCON.4- Set/cleared by software to enable/disable reception of serial data.

TB8SCON.3- The 9th bit that will be transmitted in modes 2 &3. Set/cleared by software.

RB8SCON.2- In mode 2 & 3, is the 9th data bit that was received. In mode 1, if SM2 =0, RB8 is the stop bit that was received. In mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software.

TISCON.1- Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software.

RISCON.0- Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes. Must be cleared by software.

3.19. ADDRESSABLE MODES:

The 8051 instruction operate on data stored in internal CPU registers, external memory or on the I/O ports. There are a number of methods in which these registers, memory and I/O ports can be addressed, called addressing modes. This section giuves a brief summary of the various types of addressing modes available in 8051. These modes are:

Immediate Direct Indirect Register Register specific Indexed

3.20. MEDIATE ADDRESSING:

In this mode, the data to be operated upon is in the location immediately following the opcode. For example, the instruction,MOVA,#41Loads the A ccumulator with the hex value 41.# Signifies IMMEDIATE ADDRESSING.

3.21. DIRECT ADDRESSING:

In direct addressing, the operand is specified by an 8-bit address field in the instruction. Only internal data RAM and SFRs can be directly addressed. For example, the instruction,INC20Increments the contents of the on-chip data RAM address 20 by one.

3.22. INDIRECT ADDRESSING:

In indirect addressing, the instruction specifes a register which contains the address of the operand. Both internal and external RAM can be indirectly addressed.

The address register for 8-bit addresses can be R0 or R1 of the selected register bank or the stack pointer. The address register for 16-bit addresses can only be the 16-bit data pointer register, DPTR. For example, the instruction,

MOVX@DPTR,A

Writes the contents of the accumulator to the address held by the DPTR register.3.23. REGISTER ADDRESSING:

The register banks, containing registers R0 through R7, can be accessed by certain instruction which carry a 3-bit register specification within the opcode of the instruction. Instructions that access the registers this way are code efficient, since this mode eliminates an address byte.

When the instruction is executed, one of the eight registers in the selected bank is accessed. One of the four banks is selected at the execution time by the two bank select bits in the PSW. For example, the instruction,MOVA,R0Copies the contents of the register R0 to the accumulator.

3.24. REGISTER-SPECIFIC INSTRUCTIONS:

Some instructions are specific to a certain register. Stating in other words, the opcode itself contains the implied operand or the operand destination. For example, some instruction always operate on the accumulator or data pointer, etc., so no address byte is needed to point to it. The opcode itself does that needed to point to it. The opcode itself does that instructions that refer to the Accumulator as A assemble as accumulator-specific opcodes. Such instructions are one byte long. The instructionRRAIs such an instruction which operates only on the accumulator. This instruction when executed rotates the contents of accumulator one bit towards right.3.25. INDEDDRESSING:

Only program memory can be accessed with indexed addressing and it can only be read. This addressing mode is intended for reading look-up tables in program memory. A 16-bit base register points to the base of the table and the accumulator is set up with the table entry number. The address of the table entry in program memory is formed by adding the accumulator data to the base pointer. The instruction,MOVA,@A+DPTRReads the contents of program memory, whose address is obtained by adding the contents of DPTR and accumulator and copies it to the accumulator.

Another type of indexed addressing is used in the case jump instruction. In this case, the destination address of a jump instruction is computed as the sum of the contents of base pointer and accumulator.

3.26 I/O ADDRESSES OF PERIPHERALS IN MICRO-51 AND MP-I (8051)

This manual is formulated as a user manual common for both Micro-51 and Micro power-I based 8031/8051 piggyback boards. Since almost all the features are common for both the kits, the worked out examples given in chapters 2, 3 and 4 will work in both the kits. But, the peripherals addresses will differ.

Having this in mind, the addresses of all the peripherals provided in both the kits are tabulated in table-3 and are given a general name. In the worked out examples, only these general names are mentioned. The user has to substitute the correct address depending on the kit in which the user is working.

TABLE 3:NAME OF THE PERIPHERALADDRESS IN Micropower-iADDRESS IN Micro-51GENERAL NAME

8279 DATA PORT8279 CONTROL PORT8253 CHANNEL 08253 CHANNEL 18253 CHANNEL 28253 CONTROL8251 DATA PORT8251 CONTROL PORT8255-1 PORT A8255-1 PORT B8255-1 PORT C8255-1 CONTROL8255-2 PORT A8255-2 PORT B8255-2 PORT C8255-2 CONTROL8255-3 PORT A8255-2 PORT B8255-2 PORT C8255-2 CONTROLTAPE WIRTE8259 ICW18259 ICW28259 ICW38259 ICW4

8259 OCW18259 OCW28259 OCW38251_2 DATA8251_2 CONTROLDAC DATAADC DATAADC SOCPRINTER STATUS & ADC EOC

PRINTER CONTROLPRINTER DATAADC CHANNEL SELECTTAPE READEPROM PROG

A000A001A004A005A006A007A008A009A00CA00DA00EA00FA010A011A012A013----A014A018A018A019A019

A019A018A018A01CA01DA020A024A028

A02C

A034A034

A038A03C-E000E001E008E009E00AE00BE004E005E00CE00DE00EE00FE010E011E012E013E014E015E016E017E01C----

--------

E024

E020E028

-E024E018DSP_DATDSP_CNTTMR_CH0TMR_CH1TMR_CH2TMR_CNTSER_DATSER_CNTAPORT_1BPORT_1CPORT_1CNT_1APORT_2BPORT_2CPORT_2CNT_2APORT_3BPORT_3CPORT_3CNT_3TPE_WRICW1ICW2ICW3ICW4OCW1OCW2OCW3COM2_DAT COM2_CNT DAC -DAT ADC - DAT ADCSOC

PRNSTAADCEOCPRNCNTPRNDAT

ADCCHSTPERDEPISEL

CHAPTER 2

SOFTWARE EXAMPLES

4. KEY PAD

The predominant interface between humans and computers is the keyboard. Keyboards range in complexity from the up-down buttons used for elevators to the personal computer, with the addition of function keys and numeric pads. One of the first mass users for the microcontroller was to interface between the keyboard and the main processor in personal computers. Industrial and commercial applications fall somewhere in between these extremes, using layouts that might feature from six to twenty keys.

The keyboard application program must guard against the following possibilities

More than one key pressed (simultaneously or released in any sequence) Key pressed and held Rapid key press and releaseAll of these situations can be addressed by hardware or software.

4.1. KEY SWITCH FACTORS:

The universal key characteristic is the ability to bounce. The key contacts vibrate open and closed for a number of milliseconds when the key is hit and often when it is released. These rapid pulses are not discernible to the human, but they last a relative eternity in the microsecond dominated life of the microcontroller. Keys may be purchased that do not bounce or keys may be denounced with the RS flip-flops or denounced in software with time delays.

4.2. KEYBOARD CONFIGURATIONS:

Keyboards are commercially produced in

i) hypothetical wiring keyboard , lead per key ii) X-Y matrix keyboardiii) Coded keyboard

The lead per key configuration is typically used when there are very few keys to be sensed. Since each key could tie up a port pin, it is suggested that the number be kept to 16 or fewer for this keyboard type. This configuration is the most costs effective for a small number of keys.

The X-Y matrix connections are very popular when the number of keys exceeds 10.Coded keyboards were evolved originally for telephonic applications involving touch tone signaling.

5. LCD DISPLAY

5.1. INTRODUCTION:

Liquid crystal displays (LCDs) have materials which combine the properties of both liquids and crystals. Rather than having a melting point, they have a temperature range within which the molecules are almost as mobile as they would be in a liquid, but are grouped together in an ordered form similar to a crystal.

An LCD consists of two glass panels, with the liquid crystal material sand witched in between them. The inner surface of the glass plates are coated with transparent electrodes which define the character, symbols or patterns to be displayed polymeric layers are present in between the electrodes and the liquid crystal, which makes the liquid crystal molecules to maintain a defined orientation angle.

One each polarisers are pasted outside the two glass panels. These polarisers would rotate the light rays passing through them to a definite angle, in a particular direction

When the LCD is in the off state, light rays are rotated by the two polarisers and the liquid crystal, such that the light rays come out of the LCD without any orientation, and hence the LCD appears transparent. When sufficient voltage is applied to the electrodes, the liquid crystal molecules would be aligned in a specific direction. The light rays passing through the LCD would be rotated by the polarisers, which would result in activating / highlighting the desired characters.

The LCDs are lightweight with only a few millimeters thickness. Since the LCDs consume less power, they are compatible with low power electronic circuits, and can be powered for long durations.

The LCDs doing generate light and so light is needed to read the display. By using backlighting, reading is possible in the dark. The LCDs have long life and a wide operating temperature range.

Changing the display size or the layout size is relatively simple which makes the LCDs more customer friendly.

The LCDs used exclusively in watches, calculators and measuring instruments are the simple seven-segment displays, having a limited amount of numeric data. The recent advances in technology have resulted in better legibility, more information displaying capability and a wider temperature range. These have resulted in the LCDs being extensively used in telecommunications and entertainment electronics.

5.2. POWER SUPPLY:

The power supply should be of +5V, with maximum allowable transients of 10mv. To achieve a better / suitable contrast for the display, the voltage (VL) at pin 3 should be adjusted properly.

A module should not be inserted or removed from a live circuit. The ground terminal of the power supply must be isolated properly so that no voltage is induced in it. The module should be isolated from the other circuits, so that stray voltages are not induced, which could cause a flickering display.

5.3. HARDWARE:

Develop a uniquely decoded E strobe pulse, active high, to accompany each module transaction. Address or control lines can be assigned to drive the RS and R/W inputs.

Utilize the Hosts extended timing mode, if available, when transacting with the module. Use instructions, which prolong the Read and Write or other appropriate data strobes, so as to realize the interface timing requirements.

If a parallel port is used to drive the RS, R/W and E control lines, setting the E bit simultaneously with RS and R/W would violate the modules set up time. A separate instruction should be used to achieve proper interfacing timing requirements.5.4. MOUNTING:

Cover the display surface with a transparent protective plate, to protect the polarizer. Dont touch the display surface with bare hands or any hard materials. This will stain the display area and degrade the insulation between terminals.

Do not use organic solvents to clean the display panel as these may adversely affect tape or with absorbant cotton and petroleum benzene. The processing or even a slight deformation of the claws of the metal frame will have effect on the connection of the output signal and cause an abnormal display.

Do not damage or modify the pattern wiring, or drill attachment holes in the PCB. When assembling the module into another equipment, the space between the module and the fitting plate should have enough height, to avoid causing stress to the module surface.

Make sure that there is enough space behind the module, to dissipate the heat generated by the ICs while functioning for longer durations. When an electrically powered screwdriver is used to install the module, ground it properly.

While cleaning by a vacuum cleaner, do not bring the sucking mouth near the module. Static electricity of the electrically powered driver or the vacuum cleaner may destroy the module.

5.5. ENVIRONMENTAL PRECAUTIONS:

Operate the LCD module under the relative condition of 40C and 50% relative humidity. Lower temperature can cause retardation of the blinking speed of the display, while higher temperature makes the overall display discolor.

When the temperature gets to be within the normal limits, the display will be normal. Polarization degradation, bubble generation or polarizer peel-off may occur with high temperature and humidity.

Contact with water or oil over a long period of time may cause deformation or colour fading of the display. Condensation on the terminals can cause electro-chemical reaction disrupting the terminal circuit.

5.6. TROUBLE SHOOTING:

When the power supply is given to the module, with the pin 3 (VL) connected to ground, all the pixels of a character gets activated in the following manner:

All the characters of a single line display, as in CDM 16108.The first eight characters of a single line display, operated in the two-line display mode, as in CDM 16116.

The first line of characters of a two-line display as in CDM 16216 and 40216. The first and third line of characters of a four-line display operated in the two-line display mode, as in CDM 20416.

If the above mentioned does not occur, the module should be initialized by software. Make sure that the control signals E , R/W and RS are according to the interface timing requirements.

5.7. IMPROPER CHARACTER DISPLAY:

When the characters to be displayed are missing between, the data read/write is too fast. A slower interfacing frequency would rectify the problem.

When uncertainty is there in the start of the first characters other than the specified ones are rewritten, check the initialization and the software routine.

In a multi-line display, if the display of characters in the subsequent lines doesnt takes place properly, check the DD RAM addresses set for the corresponding display lines.

When it is unable to display data, even though it is present in the DD RAM, either the display on/off flag is in the off state or the display shift function is not set properly. When the display shift is done simultaneous with the data writa operation, the data may not be visible on the display.

If a character not found in the font table is displayed, or a character is missing, the CG ROM is faulty and the controller IC have to be changedIf particular pixels of the characters are missing, or not getting activated properly, there could be an assembling problem in the module.5.8. CRYSTALONICS DISPLAY:

INTRODUCTION:

Crystalloids dot matrix (alphanumeric) liquid crystal displays are available in TN, STN types, with or without backlight. The use of C-MOS LCD controller and driver ICs result in low power consumption. These modules can be interfaced with a 4-bit or 8-bit micro processor /Micro controller.

The built-in controller IC has the following features:

Correspond to high speed MPU interface (2MHz) 80 x 8 bit display RAM (80 Characters max) 9,920 bit character generator ROM for a total of 240 character fonts. 208 character fonts (5 x 8 dots) 32 character fonts (5 x 10 dots) 64 x 8 bit character generator RAM 8 character generator RAM 8 character fonts (5 x 8 dots) 4 characters fonts (5 x 10 dots) Programmable duty cycles 1/8 for one line of 5 x 8 dots with cursor1/11 for one line of 5 x 10 dots with cursor1/16 for one line of 5 x 8 dots with cursor Wide range of instruction functions display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift, display shift.5.9. FUNCTIONAL DESCRIPTION OF THE CONTROLLER IC

REGISTERS:

The controller IC has two 8 bit registers, an instruction register (IR) and a data register (DR). The IR stores the instruction codes and address information for display data RAM (DD RAM) and character generator RAM (CG RAM). The IR can be written, but not read by the MPU.

The DR temporally stores data to be written to /read from the DD RAM or CG RAM. The data written to DR by the MPU, is automatically written to the DD RAM or CG RAM as an internal operation.

When an address code is written to IR, the data is automatically transferred from the DD RAM or CG RAM to the DR. data transfer between the MPU is then completed when the MPU reads the DR. likewise, for the next MPU read of the DR, data in DD RAM or CG RAM at the address is sent to the DR automatically. Similarly, for the MPU write of the DR, the next DD RAM or CG RAM address is selected for the write operation.

5.10. THE REGISTER SELECTION TABLE IS AS SHOWN BELOW:

RSR/WOperation

00IR write as an internal operation

01Read busy flag (DB7) and address counter (DB0 to DB6)

10DR write as an internal operation (DR to DD RAM or CG RAM)

11DR read as an internal operation (DD RAM or CG RAM to DR)

5.11. BUSY FLAG:

When the busy flag is1, the controller is in the internal operation mode, and the next instruction will not be accepted.When RS = 0 and R/W = 1, the busy flag is output to DB7.The next instruction must be written after ensuring that the busy flag is 0.

5.12. ADDRESS COUNTER:

The address counter allocates the address for the DD RAM and CG RAM read/write operation when the instruction code for DD RAM address or CG RAM address setting, is input to IR, the address code is transferred from IR to the address counter. After writing/reading the display data to/from the DD RAM or CG RAM, the address counter increments/decrements by one the address, as an internal operation. The data of the address counter is output to DB0 to DB6 while R/W = 1 and RS = 0.

5.13. DISPLAY DATA RAM (DD RAM):

The characters to be displayed are written into the display data RAM (DD RAM), in the form of 8 bit character codes present in the character font table. The extended capacity of the DD RAM is 80 x 8 bits i.e. 80 characters.5.14. CHARATCER GENERATOR ROM (CG ROM)

The character generator ROM generates 5 x 8 dot 5 x 10 dot character patterns from 8 bit character codes. It generates 208, 5 x 8 dot character patterns and 32, 5 x 10 dot character patterns.

5.15. CHARACTER GENERATOR RAM (CG RAM)

In the character generator RAM, the user can rewrite character patterns by program. For 5 x 8 dots, eight character patterns can be written, and for 5 x 10 dots, four character patterns can be written.

5.16. INTERFACING THE MICROPROCESSOR / CONTROLLER:

The module, interfaced to the system, can be treated as RAM input/output, expanded or parallel I/O.Since there is no conventional chip select signal, developing a strobe signal for the enable signal (E) and applying appropriate signals to the register select (RS) and read/write (R/W) signals are important.

The module is selected by gating a decoded module address with the host processors read/write strobe. The resultant signal, applied to the LCDs enable (E) input, clocks in the data. The E signal must be a positive going digital strobe, which is active while data and control information are stable and true. The falling edge of the enable signal enables the data / instruction register of the controller. All module timings are referenced to specific edges of the E signal. The E signal is applied only when a specific module transaction is desired. The read and write strobes of the host, which provides the E signals, should not be linked to the modules R/W line. An address bit which sets up earlier in the hosts machine cycle can be used as R/W.

When the host processor is so fast that the strobes are too narrow to serve as the E pulse

1) Prolong these pulses by using the hosts Ready input2) Prolong the host by adding wait states3) Decrease the Hosts Crystal frequency.

6. TRANSFORMER

a. Action:

A transformer changes (transforms) an alternating voltage from one value to another. It consists of two coils, called the primary and secondary winding, which are not connected electrically. The windings are either one on top of the other or are side by side on an iron, iron-dust or air core.

A transformer works by electromagnetic induction: a.c. is supplied to the primary and produces a changing (alternating) voltage in the secondary. It is important that as much as possible of the magnetic field produced by the primary passes through the secondary. A practical arrangement designed to achieve this in an iron-cored transformer. In which the secondary is wound on top of the primary. You should also notice that the induced voltage in the secondary is always of opposite polarity to the primary voltage.

Too large a current in a transformer causes magnetic saturation of the core i.e. the magnetization of the core is a maximum and it is no longer able to follow changes of magnetizing current. Particular care is required when there is a D.C. component.

A transformer with two secondaries is represented in fig 6.14; it both steps-up and steps-down the primary voltage. The step-down secondary voltage is 6 V a.c. what is the step-up one?

If the voltage is stepped-up by a transformer the current is stepped- down in proportion and vice versa. This must be so if we assume that all the electrical energy given to the primary appears in the secondary. We can then say:Power in primary = power in secondary(Or)VPIP = VsIsWhere IP and Is are the primary and secondary currents respectively.

Therefore in a perfect transformers, if Vs double VP,Is is half IP. In practice Is is less than half Ip because of small energy losses in the transformer arising from the resistance of the windings of copper wire, causing the current in them to produce heat, eddy currents in iron and iron dust cored transformers, (reduce by laminations), and the magnetic field of the primary not passing entirely through the secondary.

b. Types of Transformers:

Mains:

Mains transformers are used at a.c. mains frequency (50 Hz Britain), their primary coil being connected to the 240 V a.c. supply. Their secondary windings may be step-up or step-down or they may have one or more of each. They have laminated iron cores and are used in power supply units. Sometimes the secondary has a center-tap-sec Units 20.2.

Step-down toroidal types are becoming popular. They have virtually no external magnetic field and a screen between primary and secondary windings gives safety and electrostatic screening. Their pin connections are brought out to a 0.1-inch grid, which makes them ideal for printed circuit board (p.c.b.) mounting.

Isolating transformers have a one-to-one turns ratio (i.e. ns/np = 1/1) and are safety devices for separating a piece of equipment from the mains supply. They do not change the voltage.

Audio frequency:

Audio frequency transformers, as illustrated in also have laminated iron cores and are used as output matching transformers to ensure the maximum transfer of power from the a.f. output stage to the loudspeaker in, for example, a radio set or amplifier.

Radio frequency:

Radio frequency transformers usually have adjustable iron-dust cores and form part of the tuning circuits in a radio. They are enclosed in a small aluminum screening can to stop them radiating energy to other parts of the circuit.

7. ADVANTAGES

1. No need for manual monitoring 2. Intimation speed is too fast 3. Cost of controlling unit is low 4. Easy to handle.

8. APPLICATION

* Automobile Applications* Home Appliances* Object Counter* Electricity Board Applications