Local Trigger Unit for NA62

Marián Krivda1) , Cristina Lazzeroni1) , Vlado Černý2), Tomáš Blažek2), Roman Lietava1)2)

1) University of Birmingham, UK2) Comenius University, Bratislava, Slovakia

15/12/2010 1

Content

• General view• Status of LTU production and tests• Status of firmware • Status of software• Usage of LTU boards for Run2011• News from TTC upgrade meeting• Summary

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Clock distribution and data flow

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LTU+

TTCex

LTU+

TTCex

LTU+

TTCex

LTU+

TTCex

40 MHz clock

source

. . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . .

TTC partition

TTCrx TTCrx TTCrx TTCrx

Trigger inputs

For jitter < 50 ps RMSQPLL must be used !

QPLL QPLL QPLL QPLL

FEE FEE FEE FEE

CHOKE/ERROR

Triggers

TTCClock +Triggers

Sync.card

L0TP

LTU+TTCex+(20dB att./TTCoc)

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40 MHz clock

source

6U VME cards 1 LTU+TTCex per detector !!!

Local Trigger UnitLTU

Optical transmission of A and B channel

TTCex

ser. data channel Aser. data channel B

Trig. data from L0 processor

Burst

clock

clock

31 optical outputs to FEE

Detector CHOKE/ERROR

LVDS (7)

Warning ejection (WE)

Monitoring of TTCTTCit

TTCoc 1:32

Status of LTU production and tests• First 3 LTU boards

are produced– 3 faulty components

LMS1583-1.5– 2 faulty components

PDU15F– 1 PCB damaged by

replacing the faulty component

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Status of LTU production and tests• Problems after replacement of one faulty

component (2 unconnected pads and microscopic hole)

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Status of LTU production and tests• Performed tests

– VME FPGA connections– LTU FPGA connections– Flash Memory test– SnapShot memory test– LEDs test– Front panel connectors test

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VME

BU

S

FRO

NT

PAN

EL

FLASH MEMORYstores code to be loaded into LTU FPGA

VME FPGAbasic "firmware"

LTU FPGA

LTU logic

FRONT PANEL I/O connectors

OSCILOSCOPE connectors

LTU testing software: LTU main components

• Computer speaks via VME bus to VME FPGA which distributes the communication further to inner LTU parts

• LTU FPGA is programmed to perform LTU logic operations• The LTU logic reacts to control commands from computer (by for example sending a

signal from a particular point inside LTU into front panel I/O connector or sending the value back to computer via VME FPGA and VME bus

• Snap shot memory to provide the possibility of logging of 26 ms of the front panel dataThe testing software tests the communication between those main blocks

Snap shot memory

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Testing software guides the operator via screen prompts like "Connect the oscilloscope to connector B"

"You should see clock signal""Press enter when ready“

Phase 0:Testing that LTU (VME FPGA) reacts to VME busPhase 1:tests the flash memory writing and reading back random dataPhase 2:loads phase 2 logic into LTU FPGAchecks success of PLL clock locktests snap shot memory by writing and reading back random datatests that data logging into snap shot memory is functional Phase 3: loads phase 3/4 logic into LTU FPGAtest R/W operations to LTU FPGAPhase 4:sending various signals to specific front panel connectors and testing their presence by oscilloscope15/12/2010 9

LTU testing software: Testing procedure

News from TTC upgrade meeting• PHOTON lasers replace by OCP lasers (300 USD/pc), median

life of OCP estimated to more than 88 years• possible replacement of TRR1B43 by PD-LD (68 EUR/pc) or

Ficer (28EUR/pc), to be qualified early 2011 • new TTCex:

1. New PLL to replace obsolete VCXO2. Standalone frequency compliant with QPLL locking range3. Ability to turn on-off each laser individually and monitor their status4. Available in January 2011

• possible replacement of TTCrq board with TTC-FMC board, ref. design (HW + Firmware) in 2011, better connector, 2 ways (TTCrq flavor, Light flavor)

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Usage of LTUs for Run2011

• Usage of PULSER (ECL) input on LTU board15/12/2010 11

LTU+

TTCex

LTU+

TTCex

LTU+

TTCex

LTU+

TTCex . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . .

TTC partition

TTCrx TTCrx TTCrx TTCrx

QPLL QPLL QPLL QPLL

FEE FEE FEE FEE

TTCClock +Triggers

40 MHz clock

sourceECL fan-outTrigger inputs

Status of firmware

• Written some modules in Verilog (ALICE LTU is wiritten in AHDL)l0_logic (top module), pll, led, clock_check, gray_counter, gray2bin, adc, busy, ttcvi_emu, vi_fifo1024x6, l0fifo_write, l0_fifo

• Simulations in CADENCE

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Status of softwareReminder: DIM architecture• DIM servers running on VME processor in the crate• DIM clients running anywhere in the world

All services implemented on both the client and server sides

Adapting to details of the new NA62 LTU firmware will be done in a short time after the firmware is ready

New stuff: SIM proxies to provide interface to RUNCONTROL and/or DCS

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VME processor VME driver LTU

DIM/SMI proxy

DIM clients SMI GUI

LTULTU

DIM/SMI architecture

DIM/SMI proxy

DIM/SMI proxy

Ob

SMI DOMAIN"SMI_LTU"

Obj Obj Obj

CEDAR

VETO

STRAW

TCP/IP

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• What we presented here is a proof of concept. Details concerning SMI objects and actions are to be discussed with RUNCONTROL programmers.

• We are able to provide SMI proxies to be connected to (maybe third party) SMI managers

• We are ready if it is decided that RUNCONTROL and/or DCS would be based on SMI15/12/2010 16

Summary concerning SMI

Summary

• We have asked to produce next 2 LTU boards in order to check quality of production

• If there will be any faulty component we will send the board back to company for replacement

• Basic firmware and software for testing of components on the LTU is ready

• Final firmware written in Verilog, partially done, simulation in CADENECE set-up.

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