lna design for 10 ghz bandwidth - uio
TRANSCRIPT
![Page 1: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/1.jpg)
LNA design in CMOS for 10 GHz gbandwidth
Mats Risopatron Knutsen,Master student Nanoelectronics group g p
Dept. of InformaticsUniversity of OsloUniversity of Oslo
![Page 2: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/2.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Challenges in the design of LNAs with bandwidth towards 10 GHz
• Implemented circuit• Implemented circuit
• Measurements
![Page 3: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/3.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Challenges in the design of LNAs with bandwidth towards 10 GHz
– Lower supply voltage Fewer topologies– Lower supply voltage Fewer topologies
M t hi d b d idth h t ith– Matching and bandwidth enhancement with as few inductors as possible
– Lower dynamic range Lower SNR
![Page 4: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/4.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Challenges in the design of LNAs with bandwidth towards 10 GHz
• Implemented circuit• Implemented circuit– PLS performance– Matching properties
• Measurements
![Page 5: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/5.jpg)
LNA design in CMOS for 10 GHz bandwidth
I l t d i it• Implemented circuit
– InverterbasedInverterbased
– Splitting ‐loadpeaking stagepeaking stage
– Implementedwithoutbondwiremodel
![Page 6: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/6.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Implemented circuit
– S21 15.1 dB
– Bandwidth 0 4 8 6 GHz0.4‐8.6 GHz
NF 5 8 dB– NF < 5.8 dB
![Page 7: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/7.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Implemented circuit– Matching approachesg pp
2011.03.09 7
![Page 8: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/8.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Challenges in the design of LNAs with bandwidth towards 10 GHz
• Implemented circuit• Implemented circuit
• Measurements – ResultsResults– Reasons for degradation
![Page 9: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/9.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Measurements
– Gain 9.5±2dBbetween 0.3 andbetween 0.3 and3.6 GHzReverse gain 30– Reverse gain 30 dB higher than PLSPLS
– “Spiky” responses9
![Page 10: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/10.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Measurements
– S11 and S22
– Total reflectionin large parts ofin large parts ofthe sweep
10
![Page 11: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/11.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Measurements
– Open and shortedshortedbond wiretest benchestest benchesincludedResonates at– Resonates at above 9 GHz
11
![Page 12: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/12.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Measurement,reasons for degradation from PLS to gmeasurements
– Reactive nature of bond wire and pad degrades matching propertiesmatching properties
– S12 results indicate cross talk on PCB– Noisy measurement environment
12
![Page 13: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/13.jpg)
LNA design in CMOS for 10 GHz bandwidth
• Summary:
– LNA design in CMOS for 10 GHz is a challenge• Reducing the number of inductors still achieve theReducing the number of inductors, still achieve the bandwidth and matching properties
• Maintaining the simulated performance from PLS toMaintaining the simulated performance from PLS to measurements
– Good models of bond wire and pad are essentialGood models of bond wire and pad are essential to implement in the design phase for a good resultsresults
![Page 14: LNA design for 10 GHz bandwidth - UiO](https://reader030.vdocuments.mx/reader030/viewer/2022013001/61cb6044253bfb6fa57a21f8/html5/thumbnails/14.jpg)
LNA design in CMOS for 10 GHz bandwidth
• References:• S‐F. Chao, J‐J Kuo, C‐L. Lin, M‐D‐ Tsai and H. Wang, “A DC‐11.5 GHz Low‐
d b d l f l d d kPower, Wideband Amplifier Using Splitting‐Load Inductive Peaking Technique,” in IEEE Microwave and Wireless Components Letters, Vol 18, NO 7, July 2008
• P. Heydari, “Design and Analysis of a Performance‐Optimized CMOS UWB Distributed LNA,” in IEEE Journal of Solid‐State Circuits, Vol 42, No 9, September 2007September 2007
• S.B‐T. Wang, Design of Ultra‐Wideband RF Front‐End, Berkeley: PhD dissertation, University Of California, Berkeley, 2005
• W. Sansen, Analog Design Essentials, Springer, 2006