175

List of Publications

(1) Chandra Shekhar, Raj Singh, A. S. Mandal, S. C. Bose, Ravi Saini and Pramod

Tanwar, “Application Specific Instruction set Processors: Redefining Hardware-

Software Boundary,” In Proceedings of 17th

International Conference on VLSI

Design (VLSI-2004), Mumbai, pp. 915-918, IEEE Press, January 5-9, 2004.

(2) Ravi Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Raj Singh and Chandra

Shekhar, “Design of an Application Specific Instruction set Processor for

Parametric Speech Synthesis,” In Proceedings of 17th

International Conference on

VLSI Design (VLSI-2004), Mumbai, January 5-9, pp. 915-918, IEEE Press, 2004.

(3) Ravi Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Raj Singh and Chandra

Shekhar, “Architecture Design of a Floating Point Arithmetic and Trigonometric

Function Processor” at International Conference on Communication, Devices and

Intelligent Systems (CODIS 2004), Kolkata, January, 2004.

(4) Ravi Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Raj Singh and Chandra

Shekhar, “Architecture of an Application Specific Instruction Set Processor for

Parameter Speech Synthesis” in Workshop on Spoken Language Processing at

TIFR, Mumbai.

(5) Ravi Saini, Pramod Tanwar, S. Bhattacharya, A. S. Mandal, S. C. Bose, Raj Singh

and Chandra Shekhar, “Architecture Studies and Synthesis for Floating Point

Multiplication” at IETE Golden Jubilee Seminar on EDA: Issues and Challenges,

Jaipur, 2003.

(6) Ravi Saini, Pramod Tanwar, S. Bhattacharya, A. S. Mandal, S. C. Bose, Raj Singh

and Chandra Shekhar, “Hardware Architecture and Implementation of

Exponential, Trigonometric and Square-root Functions” at IETE Golden Jubilee

Seminar on EDA: Issues and Challenges, Jaipur, 2003.

176

(7) R. Saini, Pramod Tanwar, A. S. Mandal, S. C. Bose, Sudhir Kumar, Raj Singh

and Chandra Shekhar, “Design of Voice chip”: A Hardware Implementation of

Parametric Speech Synthesis Engine For Embedded Applications, Paper in

International Symposium on Speech Technology and Processing Systems

(iSTEPS-2004), New Delhi, November, 2004.

(8) Ravi Saini, B. Prasad, A. S. Mandal, S. C. Bose, Raj Singh and Chandra Shekhar,

“Design of an Application Specific Instruction Set Processor for Parametric

Speech Synthesis” paper in IMS Conference-2006, Kurukshetra, 2006.

177

Appendix A

1. RT-level VHDL code of FASC Block

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.all; entity fasc is port(dbus : inout std_logic_vector(31 downto 0); clock,reset : in std_logic; FASC_flag : out std_logic; b2fc: in std_logic_vector(3 downto 0); f2bc: in std_logic_vector(3 downto 0)); end; architecture rtl_fp_add of fasc is component BARREL_SHIFTER port(direction : in std_logic; fill_bit : in std_logic; shift : in unsigned (4 downto 0); input : in unsigned (23 downto 0); output:out unsigned(23 downto 0); guard, round, sticky: out std_logic); end component; component LEAD1_FIND port(A: in unsigned(23 downto 0); Z: out unsigned(4 downto 0); Zbit: out std_logic); end component; type state is (st_init,st0,st1,st_result); signal adder_st : state; signal result_reg : unsigned(31 downto 0); signal inter_reg : unsigned(31 downto 0); signal final_sp_res,final_res:unsigned(31 downto 0); signal sum_of_sig,sum1:unsigned(24 downto 0); signal sum_reg:unsigned(24 downto 0); signal lead0_oup,lead0_oup_reg:unsigned(4 downto 0); signal sign1,sign2,sign_fin : std_logic;

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signal sign1_after_swap,sign2_after_swap : std_logic; signal sp_check_true_reg : std_logic; signal en_sp_check_true_reg : std_logic; signal start_reg,sp_check_true : std_logic; signal exp1,exp1_after_swap : unsigned(7 downto 0); signal exp2,exp2_after_swap : unsigned(7 downto 0); signal exp_fin : unsigned(7 downto 0); signal D,D_reg : unsigned(7 downto 0); signal sig1,sig1_after_swap : unsigned(23 downto 0); signal sig2,sig2_after_swap : unsigned(23 downto 0); signal sig2_modify_reg : unsigned(23 downto 0); signal sig2_2scomp,sig_fin : unsigned(23 downto 0); signal barr_align_out : unsigned(23 downto 0); signal input_for_barrel : unsigned(23 downto 0); signal g,r,s,g1,r1,s1,Zbit,res_neg_reg,swap_reg : std_logic; signal res_neg,en_res_neg_reg : std_logic; signal fill_bit,direction,swap : std_logic; signal rh_shift,count : unsigned(4 downto 0); signal en_D_reg,en_load_op1,en_load_op2 : std_logic; signal en_sig2_modify: std_logic; signal en_inter_reg : std_logic; signal en_sum_reg,fill_bit1: std_logic; signal en_lead0_oup_reg,direction1: std_logic; signal en_result_reg,en_swap_reg: std_logic; begin --------------------------------------------------- --Send o/p from functional unit to bus --------------------------------------------------- fasc2bus : process(result_reg,f2bc) begin if(f2bc = "0100") then dbus <= std_logic_vector(result_reg); else dbus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; end if; end process; --------------------------------------------------- load_start_reg : process(clock) begin if (clock'event and clock = '1') then if (reset = '1') then start_reg <= '0'; elsif ( b2fc = "0010" or b2fc = "0011") then start_reg <= '1';

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else start_reg <= '0'; end if; end if; end process; --------------------------------------------------- -- load Op1 in 1st cycle--------------------------- load_op1 : process(clock) begin if (clock'event and clock = '1' ) then if(b2fc = "0001") then sign1 <= dbus(31); exp1 <= unsigned(dbus(30 downto 23)); sig1 <= unsigned('1' & dbus(22 downto 0)); end if; end if; end process; --------------------------------------------------- -- load op2 in 2nd cycle -------------------------- load_op2_add : process(clock) begin if (clock'event and clock = '1' ) then if((b2fc = "0010") or (b2fc = "0011")) then exp2 <= unsigned(dbus(30 downto 23)); sig2 <= unsigned('1' & dbus(22 downto 0)); end if; end if; end process; --------------------------------------------------- -- load sign2 in 2nd cycle-and op is subtraction----- load_op2_sub : process(clock) begin if (clock'event and clock = '1' ) then if(b2fc = "0010") then sign2 <= dbus(31); elsif(b2fc = "0011") then sign2 <= not(dbus(31)); end if; end if; end process; --------------------------------------------------- load_op1_after_swap : process(clock) begin if (clock'event and clock = '1' ) then if(en_load_op1 = '1') then if(swap = '1') then sign1_after_swap <= sign2;

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exp1_after_swap <= exp2; sig1_after_swap <= sig2; else sign1_after_swap <= sign1; exp1_after_swap <= exp1; sig1_after_swap <= sig1; end if; end if; end if; end process; --------------------------------------------------- load_op2_after_swap : process(clock) begin if (clock'event and clock = '1' ) then if(en_load_op2 = '1') then if(swap = '1') then exp2_after_swap <= exp1; sig2_after_swap <= sig1; else exp2_after_swap <= exp2; sig2_after_swap <= sig2; end if; end if; end if; end process; --------------------------------------------------- load_op2_sign2_after_swap : process(clock) begin if (clock'event and clock = '1' ) then if(en_load_op2 = '1') then if(swap = '1') then sign2_after_swap <= sign1; else sign2_after_swap <= sign2; end if; end if; end if; end process; --------------------------------------------------- -- 1st cycle or st_init------------------------------ set_swap_flag : process(exp1,exp2) begin if (exp1>=exp2) then D <= exp1 - exp2; swap <= '0'; elsif(exp1<exp2) then

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D <= exp2 - exp1; swap <= '1'; else D <= exp1 - exp2; swap <= '0'; end if; end process; store_swap_reg : process(clock) begin if (clock'event and clock = '1')then if(en_swap_reg = '1') then swap_reg <= swap; end if; end if; end process; store_D_reg : process(clock) begin if (clock'event and clock = '1')then if(en_D_reg = '1') then D_reg <= D; end if; end if; end process; --------------------------------------------------- --------------------------------------------------- -- 2nd cycle or st0------------------------------ check_for_sp_cases:process(exp1_after_swap,exp2_after_swap,sig1_after_swap, sig2_after_swap, sign1_after_swap,sign2_after_swap,D_reg) begin if((exp1_after_swap<23 and exp2_after_swap<23)and(sign1_after_swap/=sign2_after_swap)) then final_sp_res <= "00000000000000000000000000000000"; sp_check_true <= '1'; elsif(exp1_after_swap = 0) then final_sp_res <= sign2_after_swap & exp2_after_swap & sig2_after_swap(22 downto 0); sp_check_true <= '1'; elsif(exp2_after_swap = 0) then

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final_sp_res <= sign1_after_swap & exp1_after_swap & sig1_after_swap(22 downto 0); sp_check_true <= '1'; elsif(exp1_after_swap = 0 and exp2_after_swap = 0) then final_sp_res <= sign1_after_swap & exp1_after_swap & sig1_after_swap(22 downto 0); sp_check_true <= '1'; elsif(D_reg > 23) then final_sp_res <= sign1_after_swap & exp1_after_swap & sig1_after_swap(22 downto 0); sp_check_true <= '1'; elsif((exp1_after_swap=exp2_after_swap) and (sig1_after_swap=sig2_after_swap) and (sign1_after_swap/=sign2_after_swap)) then final_sp_res <= "00000000000000000000000000000000"; sp_check_true <= '1'; else final_sp_res <= "00000000000000000000000000000000"; sp_check_true <= '0'; end if; end process; store_sp_check_reg : process(clock) begin if (clock'event and clock = '1')then if(en_sp_check_true_reg = '1') then sp_check_true_reg <= sp_check_true; end if; end if; end process; --------------------------------------------------- fin_result : process(clock) begin if (clock'event and clock = '1') then if(en_inter_reg = '1')then inter_reg <= final_sp_res; end if; end if; end process; ---------------------------------------------------- check_for_2scomp : process(sig2_after_swap,sign1_after_swap,sign2_after_swap) variable v1 : unsigned(23 downto 0); begin v1 := "000000000000000000000000"; if(sign1_after_swap /= sign2_after_swap) then

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v1 := not(sig2_after_swap); sig2_2scomp <= v1 + 1; else sig2_2scomp <= sig2_after_swap; end if; end process; ---------------------------------------------------- set_fillbit_dir : process(sign1_after_swap,sign2_after_swap) begin if(sign1_after_swap /= sign2_after_swap) then fill_bit1 <= '1'; direction1 <= '1';--right shift else fill_bit1 <= '0'; direction1 <= '1'; end if; end process; --------------------------------------------------- --Alignment process --------------------------------------------------- rh_shift <= D(4 downto 0); B1_barr : BARREL_SHIFTER port map( direction1, fill_bit1, rh_shift, sig2_2scomp, barr_align_out, g,r,s ); --------------------------------------------------- load_swap2_modify_reg : process(clock) begin if (clock'event and clock = '1')then if(en_sig2_modify = '1') then sig2_modify_reg <= barr_align_out; end if; end if; end process; --------------------------------------------------- -- 3rd cycle or st1------------------------------

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sum_of_sig <= ('0' & sig1_after_swap) + ('0' & sig2_modify_reg); l1 : lead1_find port map (sum1(23 downto 0),lead0_oup,Zbit); check_res_neg : process(sum_of_sig,sign1_after_swap,sign2_after_swap) variable v1 : unsigned(24 downto 0); begin v1 := "0000000000000000000000000"; if(sign1_after_swap/=sign2_after_swap and sum_of_sig(24)='0'and sum_of_sig(23)='1')then v1 := not(sum_of_sig); sum1 <= v1 + 1; res_neg <= '1'; else sum1 <= sum_of_sig; res_neg <= '0'; end if; end process; --------------------------------------------------- store_sig_sum : process(clock) begin if (clock'event and clock = '1') then if(en_sum_reg = '1')then sum_reg <= sum1; end if; end if; end process; --------------------------------------------------- store_res_neg_reg : process(clock) begin if (clock'event and clock = '1') then if(en_res_neg_reg = '1')then res_neg_reg <= res_neg; end if; end if; end process; --------------------------------------------------- store_lead0_oup : process(clock) begin if (clock'event and clock = '1') then

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if(en_lead0_oup_reg = '1')then lead0_oup_reg <= lead0_oup; end if; end if; end process; --------------------------------------------------- -- Normalisation----------------------------------- -- 4th cycle or st_result------------------------------ laod_input_for_barrel:process(sum_reg,sign1_after_swap,sign2_after_swap,lead0_oup_reg) begin if (sign1_after_swap = sign2_after_swap and sum_reg(24)= '1') then fill_bit <= sum_reg(24); direction <= '1';--right shift count <= "00001"; input_for_barrel <= sum_reg(23 downto 0); elsif(sign1_after_swap /= sign2_after_swap) then fill_bit <= '0'; direction <= '0';--left shift count <= lead0_oup_reg; input_for_barrel <= sum_reg(23 downto 0); else input_for_barrel <= sum_reg(23 downto 0); fill_bit <= '0'; direction <= '0'; count <= "00000"; end if; end process; B2 : BARREL_SHIFTER port map( direction, fill_bit, count, input_for_barrel, sig_fin, g1,r1,s1 ); fin_exp_cal:process(exp1_after_swap,sign1_after_swap,sign2_after_swap,sum_reg,lead0_oup_reg) begin if (sign1_after_swap = sign2_after_swap and sum_reg(24) = '1') then

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exp_fin <= exp1_after_swap + 1; elsif(sign1_after_swap /= sign2_after_swap) then exp_fin <= exp1_after_swap - lead0_oup_reg; else exp_fin <= exp1_after_swap; end if; end process; final_res <= sign_fin & exp_fin & sig_fin(22 downto 0); --------------------------------------------------- -- sign calculation---------------------------- Sign_calculation:process(sign1_after_swap,sign2_after_swap,res_neg_reg,swap_reg) begin if(sign1_after_swap /= sign2_after_swap) then if (sign1_after_swap='0' and sign2_after_swap='1' and swap_reg='1')then sign_fin <= '0'; elsif (sign1_after_swap='1' and sign2_after_swap='0' and swap_reg='1')then sign_fin <= '1'; elsif (sign1_after_swap='0' and sign2_after_swap='1' and swap_reg='0' and res_neg_reg='0')then sign_fin <= '0'; elsif (sign1_after_swap='1' and sign2_after_swap='0' and swap_reg='0' and res_neg_reg='0')then sign_fin <= '1'; elsif (sign1_after_swap='0' and sign2_after_swap='1' and swap_reg='0' and res_neg_reg='1')then sign_fin <= '1'; elsif (sign1_after_swap='1' and sign2_after_swap='0' and swap_reg='0' and res_neg_reg='1')then sign_fin <= '0'; else sign_fin <= '0'; end if; else sign_fin <= sign1_after_swap; end if; end process; load_result_reg : process(clock) begin

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if (clock'event and clock = '1') then if(en_result_reg = '1')then if(sp_check_true_reg = '1') then result_reg <= inter_reg; else result_reg <= final_res; end if; end if; end if; end process; load_flag_reg : process(clock) begin if (clock'event and clock = '1') then if(sp_check_true_reg = '0') then if (sign_fin = '0' or exp_fin = 0) then FASC_flag <= '1'; else FASC_flag <= '0'; end if; else if (inter_reg(31) = '0' or inter_reg(30 downto 23) = 0) then FASC_flag <= '1'; else FASC_flag <= '0'; end if; end if; end if; end process; ------------------------------------------------- state_seq:process(clock) begin if (clock'event and clock = '1') then if (reset = '1') then adder_st <= st_init; else case adder_st is when st_init => if(start_reg = '1') then adder_st <= st0; else adder_st <= st_init; end if; when st0 =>

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adder_st <= st1; when st1 => adder_st <= st_result; when st_result => adder_st <= st_init; end case; end if; end if; end process; -------------------------------------------------------- -- controls for FP add---------------------------------- contorl_outputs : process(adder_st) begin case adder_st is when st_init => en_load_op1 <= '1'; en_load_op2 <= '1'; en_swap_reg <= '1'; en_D_reg <= '1'; en_sig2_modify <= '0'; en_inter_reg <= '0'; en_sum_reg <= '0'; en_lead0_oup_reg <= '0'; en_sp_check_true_reg <= '0'; en_res_neg_reg <= '0'; en_result_reg <= '0'; when st0 => en_load_op1 <= '0'; en_load_op2 <= '0'; en_swap_reg <= '0'; en_D_reg <= '0'; en_sig2_modify <= '1'; en_inter_reg <= '1'; en_sum_reg <= '0'; en_lead0_oup_reg <= '0'; en_sp_check_true_reg <= '1'; en_res_neg_reg <= '0'; en_result_reg <= '0'; when st1 => en_load_op1 <= '0'; en_load_op2 <= '0'; en_swap_reg <= '0'; en_D_reg <= '0'; en_sig2_modify <= '0';

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en_inter_reg <= '0'; en_sum_reg <= '1'; en_lead0_oup_reg <= '1'; en_sp_check_true_reg <= '0'; en_res_neg_reg <= '1'; en_result_reg <= '0'; when st_result => en_load_op1 <= '0'; en_load_op2 <= '0'; en_swap_reg <= '0'; en_D_reg <= '0'; en_sig2_modify <= '0'; en_inter_reg <= '0'; en_sum_reg <= '0'; en_lead0_oup_reg <= '0'; en_sp_check_true_reg <= '0'; en_res_neg_reg <= '0'; en_result_reg <= '1'; when others => null; end case; end process; end rtl_fp_add;

2. RT-level VHDL code of FMPY Block

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.all; entity FMPY is port(dbus : inout std_logic_vector(31 downto 0); clock,reset : in std_logic; b2fc : in std_logic_vector(3 downto 0); f2bc : in std_logic_vector(3 downto 0)); end FMPY; architecture rtl_FMPY of FMPY is type multiplier_state is (mpy_reset,mpy1,mpy2,mpy3, mpy4,mpy5); signal start_mpy : std_logic;

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signal mpy_result_reg : std_logic_vector(23 downto 0); signal mpy_state : multiplier_state; signal mcnd_reg, mplr_reg : std_logic_vector(23 downto 0); signal mplr_6bits : std_logic_vector(5 downto 0); signal select_24_6 : std_logic_vector(1 downto 0); signal en_mpy_pipeline_reg : std_logic; signal en_mpy_result_reg : std_logic; signal en_sign_result_reg : std_logic; signal en_exp_add : std_logic; signal en_exp_diff : std_logic; signal en_rh_shift : std_logic; signal en_Z_out : std_logic; signal clr_mpy_result_reg : std_logic; signal clr_mpy_start : std_logic; signal sign1 : std_logic; signal sign1_reg : std_logic; signal sign2_reg : std_logic; signal sign_result : std_logic; signal bias : std_logic_vector(8 downto 0); signal exp1 : std_logic_vector(8 downto 0); signal exp2 : std_logic_vector(8 downto 0); signal exp3 : std_logic_vector(8 downto 0); signal exp4 : std_logic_vector(8 downto 0); signal exp1_reg : std_logic_vector(8 downto 0); signal exp2_reg : std_logic_vector(8 downto 0); signal exp_add_reg : std_logic_vector(8 downto 0); signal exp_diff_reg : std_logic_vector(8 downto 0); signal exp_fin : std_logic_vector(8 downto 0); signal sig_fin : std_logic_vector(22 downto 0); signal mpy_out : std_logic_vector(29 downto 0); signal mpy_pipeline_reg : std_logic_vector(29 downto 0); signal mpy_partial_sum : std_logic_vector(29 downto 0); signal mpy_result_inter : std_logic_vector(29 downto 0); signal mpy_partialsum_or_zero : std_logic_vector(29 downto 0); signal z : std_logic_vector(31 downto 0); begin bias <= "001111111"; --------------------------------------------------------- FMPY2bus : process(f2bc, z) begin if (f2bc = "0101") then dbus <= z; else

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dbus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; end if; end process; --------------------------------------------------------- load_mcnd_reg : process(clock) begin if (clock'event and clock = '1') then if(b2fc = "0100") then mcnd_reg <= '1' & dbus(22 downto 0); exp1_reg <= '0' & dbus(30 downto 23); sign1_reg <= dbus(31); end if; end if; end process; --------------------------------------------------------- load_mplr_reg : process(clock) begin if (clock'event and clock = '1') then if(b2fc = "0101") then mplr_reg <= '1' & dbus(22 downto 0); exp2_reg <= '0' & dbus(30 downto 23); sign2_reg <= dbus(31); end if; end if; end process; --------------------------------------------------------- Pstart_mpy : process(clock) begin if (clock'event and clock = '1') then if (reset = '1') then start_mpy <= '0'; elsif (b2fc = "0101") then start_mpy <= '1'; else start_mpy <= '0'; end if; end if; end process; ------------------------------------------------------------ -- mux for selecting the lower six bits of multiplier ------------------------------------------------------------ twentyfour_to_six_select : process(select_24_6, mplr_reg) begin case select_24_6 is when "00" =>

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mplr_6bits <= mplr_reg(5 downto 0); when "01" => mplr_6bits <= mplr_reg(11 downto 6); when "10" => mplr_6bits <= mplr_reg(17 downto 12); when "11" => mplr_6bits <= mplr_reg(23 downto 18); when others => null; end case; end process; ------------------------------------------------------------ -- add exp1 and exp2 and store the sum into exp_add_reg ------------------------------------------------------------ exp1 <= std_logic_vector(unsigned(exp1_reg)+unsigned(exp2_reg)); expadd : process(clock) begin if (clock'event and clock = '1') then if (en_exp_add = '1') then exp_add_reg <= exp1; end if; end if; end process; ------------------------------------------------------------ exp2 <= std_logic_vector(unsigned(exp_add_reg)-unsigned(bias)); expdiff : process(clock) begin if (clock'event and clock = '1') then if (en_exp_diff = '1') then exp_diff_reg <= exp2; end if; end if; end process; ------------------------------------------------------------

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mpy_out <= std_logic_vector(unsigned(mcnd_reg)*unsigned(mplr_6bits)); multiplier_pipeline_reg : process(clock) begin if (clock'event and clock = '1') then if (en_mpy_pipeline_reg = '1') then mpy_pipeline_reg <= mpy_out; end if; end if; end process; ------------------------------------------------------------ -- calculating xor of operands sign, store the result in -- register sign_result ------------------------------------------------------------ sign_reg : process(sign1_reg, sign2_reg) begin sign1 <= sign1_reg xor sign2_reg; end process; signreg : process(clock) begin if (clock'event and clock = '1') then if (en_sign_result_reg = '1') then if(unsigned(exp1_reg) = 0 or unsigned(exp2_reg) = 0) then sign_result <= '0'; else sign_result <= sign1; end if; end if; end if; end process; ------------------------------------------------------------ -- mux selecting the output of 30bit adder either zero,shifted -- right,or simply the o/p of adder ------------------------------------------------------------ mpy_partial_sum<=std_logic_vector(unsigned(mpy_result_inter)

194

+ unsigned(mpy_pipeline_reg)); cl_p:process( en_rh_shift, clr_mpy_result_reg, mpy_partial_sum) begin if ( clr_mpy_result_reg = '0') then mpy_partialsum_or_zero <= "000000000000000000000000000000"; elsif( en_rh_shift = '1' and mpy_partial_sum(29) = '0') then for i in 29 downto 1 loop mpy_partialsum_or_zero(i) <= mpy_partial_sum(i-1); end loop; mpy_partialsum_or_zero(0) <= '0'; else mpy_partialsum_or_zero <= mpy_partial_sum; end if; end process; ------------------------------------------------------------ multiplier_result_reg : process(clock) begin if (clock'event and clock = '1') then if (en_mpy_result_reg = '1') then mpy_result_reg <= mpy_partialsum_or_zero(29 downto 6); end if; end if; end process; intermediate : process(mpy_result_reg) begin mpy_result_inter <= "000000" & mpy_result_reg; end process; ------------------------------------------------------------ -- selecting the exponent on the basis of the msb of adder -- o/p in the last cycle ------------------------------------------------------------ exp3 <= std_logic_vector(unsigned(exp_diff_reg) + 1);

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exp_select : process( mpy_partial_sum,exp_diff_reg,exp3) begin if ( mpy_partial_sum(29) = '0') then exp4 <= exp_diff_reg; else exp4 <= exp3; end if; end process; ------------------------------------------------------------ -- check for special case i.e. zero ------------------------------------------------------------ exp_select_final : process(exp1_reg, exp2_reg, exp4, mcnd_reg, mplr_reg, mpy_partialsum_or_zero) begin if (exp1_reg="000000000" and mcnd_reg(22 downto 0)="00000000000000000000000") then exp_fin <= "000000000"; sig_fin <= "00000000000000000000000"; elsif (exp2_reg="000000000" and mplr_reg(22 downto 0)="00000000000000000000000") then exp_fin <= "000000000"; sig_fin <= "00000000000000000000000"; elsif (exp1_reg="000000000" and mcnd_reg(22 downto 0)="00000000000000000000000" and exp2_reg="000000000" and mplr_reg(22 downto 0)="00000000000000000000000") then exp_fin <= "000000000"; sig_fin <= "00000000000000000000000"; else exp_fin <= exp4; sig_fin <= mpy_partialsum_or_zero(28 downto 6); end if; end process; ------------------------------------------------------------ -- storing the final result in register z. ------------------------------------------------------------

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output : process(clock) begin if (clock'event and clock = '1') then if (en_Z_out = '1') then z <= sign_result & exp_fin(7 downto 0) & sig_fin; end if; end if; end process; ------------------------------------------------------------ -- controller for the above multiplier ------------------------------------------------------------ controlword : process ( mpy_state ) begin case mpy_state is when mpy_reset => select_24_6 <= "00"; en_mpy_pipeline_reg <= '0'; en_mpy_result_reg <= '1'; clr_mpy_result_reg <= '0'; en_sign_result_reg <= '0'; en_exp_add <= '0'; en_exp_diff <= '0'; en_rh_shift <= '0'; en_Z_out <= '0'; when mpy1 => select_24_6 <= "00"; en_mpy_pipeline_reg <= '1'; en_mpy_result_reg <= '1'; clr_mpy_result_reg <= '0'; en_sign_result_reg <= '0'; en_exp_add <= '0'; en_exp_diff <= '0'; en_rh_shift <= '0'; en_Z_out <= '0'; when mpy2 => select_24_6 <= "01"; en_mpy_pipeline_reg <= '1'; en_mpy_result_reg <= '1';

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clr_mpy_result_reg <= '1'; en_sign_result_reg <= '1'; en_exp_add <= '0'; en_exp_diff <= '0'; en_rh_shift <= '0'; en_Z_out <= '0'; when mpy3 => select_24_6 <= "10"; en_mpy_pipeline_reg <= '1'; en_mpy_result_reg <= '1'; clr_mpy_result_reg <= '1'; en_sign_result_reg <= '1'; en_exp_add <= '1'; en_exp_diff <= '0'; en_rh_shift <= '0'; en_Z_out <= '0'; when mpy4 => select_24_6 <= "11"; en_mpy_pipeline_reg <= '1'; en_mpy_result_reg <= '1'; clr_mpy_result_reg <= '1'; en_sign_result_reg <= '0'; en_exp_add <= '0'; en_exp_diff <= '1'; en_rh_shift <= '0'; en_Z_out <= '0'; when mpy5 => select_24_6 <= "00"; en_mpy_pipeline_reg <= '0'; en_mpy_result_reg <= '1'; clr_mpy_result_reg <= '1'; en_sign_result_reg <= '0'; en_exp_add <= '0'; en_exp_diff <= '0'; en_rh_shift <= '1'; en_Z_out <= '1'; end case; end process; mpycontrol : process(clock) begin

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if (clock'event and clock='1') then if (reset = '1') then mpy_state <= mpy_reset; elsif (( mpy_state = mpy_reset )and (start_mpy = '0')) then mpy_state <= mpy_reset; elsif (( mpy_state = mpy_reset )and (start_mpy = '1')) then mpy_state <= mpy1; elsif ( mpy_state = mpy1 ) then mpy_state <= mpy2; elsif ( mpy_state = mpy2 ) then mpy_state <= mpy3; elsif ( mpy_state = mpy3 ) then mpy_state <= mpy4; elsif ( mpy_state = mpy4 ) then mpy_state <= mpy5; elsif ( mpy_state = mpy5 ) then mpy_state <= mpy_reset; end if; end if; end process; end rtl_FMPY; 3. RT-level VHDL code of FDIV Block

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity Fdiv is port(dbus : inout std_logic_vector(31 downto 0); clock : in std_logic; reset : in std_logic; b2fc : in std_logic_vector(3 downto 0); f2bc : in std_logic_vector(3 downto 0));

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end Fdiv; architecture rtl_Fdiv of Fdiv is type state is (st_init, st0, st1, st_end); signal pres_st : state ; signal start,true_zero_reg : std_logic; signal sign1,sign2 : std_logic; signal sign_result,sign_inter : std_logic; signal en_sign1,en_sign2 : std_logic; signal en_exp1,en_exp2 : std_logic; signal en_sig1,en_sig2 : std_logic; signal preset_sig1,en_count : std_logic; signal preset_sig_diff_reg,en_sig_diff_reg: std_logic; signal en_sign_result,en_exp_result : std_logic; signal en_output_result,reset_count : std_logic; signal exp1,exp2,bias : signed(7 downto 0); signal exp_diff,exp_inter,exp_result : signed(7 downto 0); signal sig1,sig2,sig_diff_reg : signed(24 downto 0); signal sig1_inter,sig_inter : signed(24 downto 0); signal output,output_result : signed(31 downto 0); signal count : integer range 0 to 26; begin bias <= "01111111"; -------------------------------------------------------------- Fdiv2bus : process(f2bc, output_result) begin if (f2bc = "0110") then dbus <= std_logic_vector(output_result); else dbus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; end if; end process; -------------------------------------------------------------- Fdiv_decode1 : process(b2fc) begin if (b2fc = "0110") then preset_sig_diff_reg <= '1'; preset_sig1 <= '1'; en_exp1 <= '1';

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en_sign1 <= '1'; else preset_sig_diff_reg <= '0'; preset_sig1 <= '0'; en_exp1 <= '0'; en_sign1 <= '0'; end if; end process; -------------------------------------------------------------- Fdiv_decode2 : process(b2fc) begin if (b2fc = "0111") then en_sig2 <= '1'; en_exp2 <= '1'; en_sign2 <= '1'; else en_sig2 <= '0'; en_exp2 <= '0'; en_sign2 <= '0'; end if; end process; -------------------------------------------------------------- Fdiv_decode3 : process(clock) begin if (clock'event and clock = '1') then if (reset = '1') then start <= '0'; elsif (b2fc = "0111") then start <= '1'; else start <= '0'; end if; end if; end process; -------------------------------------------------------------- P_sig1 : process(clock) begin if (clock'event and clock = '1') then if (preset_sig1 = '1') then sig1 <= "01" & signed(dbus(22 downto 0)); elsif (en_sig1 = '1') then sig1 <= sig1_inter; end if; end if;

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end process; -------------------------------------------------------------- P_sig2 : process(clock) begin if (clock'event and clock = '1') then if (en_sig2 = '1') then sig2 <= "01" & signed(dbus(22 downto 0)); end if; end if; end process; -------------------------------------------------------------- P_exp1 : process(clock) begin if (clock'event and clock = '1') then if (en_exp1 = '1') then exp1 <= signed(dbus(30 downto 23)); end if; end if; end process; -------------------------------------------------------------- P_exp2 : process(clock) begin if (clock'event and clock = '1') then if (en_exp2 = '1') then exp2 <= signed(dbus(30 downto 23)); end if; end if; end process; -------------------------------------------------------------- P_sign1 : process(clock) begin if (clock'event and clock = '1') then if (en_sign1= '1') then sign1 <= dbus(31); end if; end if; end process; -------------------------------------------------------------- P_sign2 : process(clock) begin if (clock'event and clock = '1') then if (en_sign2= '1') then

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sign2 <= dbus(31); end if; end if; end process; -------------------------------------------------------------- P_counter : process(clock) begin if (clock'event and clock = '1') then if (reset_count = '1') then count <= 0; elsif (en_count = '1') then count <= count + 1; end if; end if; end process; -------------------------------------------------------------- P_sig_diff_reg : process(clock) begin if (clock'event and clock = '1') then if (preset_sig_diff_reg = '1') then sig_diff_reg <= "01" & signed(dbus(22 downto 0)); elsif (en_sig_diff_reg = '1') then sig_diff_reg <= sig_inter ; end if; end if; end process; -------------------------------------------------------------- sign_inter <= sign1 xor sign2; P_sign_result : process(clock) begin if (clock'event and clock = '1') then if (en_sign_result = '1') then sign_result <= sign_inter; end if; end if; end process; -------------------------------------------------------------- exp_diff <= exp1 - exp2; exp_inter <= exp_diff + bias; P_exp_result : process(clock)

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begin if (clock'event and clock = '1') then if (en_exp_result = '1') then exp_result <= exp_inter; end if; end if; end process; -------------------------------------------------------------- P_sig_diff : process(sig_diff_reg,sig1,sig2) variable sig_diff : signed(24 downto 0); begin sig_diff := sig_diff_reg - sig2; if (sig_diff(24) = '1') then sig1_inter <= sig1(23 downto 0) & '0'; sig_diff := sig_diff + sig2; else sig1_inter <= sig1(23 downto 0) & '1'; end if; sig_inter <= sig_diff(23 downto 0) & sig1(24); end process; -------------------------------------------------------------- check_for_zero : process(clock) begin if (clock'event and clock = '1') then if (exp1 = 0) then true_zero_reg <= '1'; else true_zero_reg <= '0'; end if; end if; end process; -------------------------------------------------------------- P_normal : process(sig1,sign_result,exp_result) begin if(sig1(23) = '1') then output(22 downto 0) <= sig1(22 downto 0); output(30 downto 23) <= exp_result; output(31) <= sign_result; else output(22 downto 0) <= sig1(21 downto 0) & '0'; output(30 downto 23) <= exp_result - 1; output(31) <= sign_result;

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end if; end process; -------------------------------------------------------------- P_output_result : process(clock) begin if (clock'event and clock = '1') then if (en_output_result = '1') then if (true_zero_reg = '1') then output_result <= "00000000000000000000000000000000"; else output_result <= output; end if; end if; end if; end process; -------------------------------------------------------------- add_sub : process(pres_st) begin case pres_st is when st_init => en_sig1 <= '0'; reset_count <= '1'; en_count <= '0'; en_sig_diff_reg <= '0'; en_sign_result <= '0'; en_exp_result <= '0'; en_output_result <= '0'; when st0 => en_sig1 <= '0'; reset_count <= '0'; en_count <= '0'; en_sig_diff_reg <= '0'; en_sign_result <= '1'; en_exp_result <= '1'; en_output_result <= '0'; when st1 => en_sig1 <= '1'; reset_count <= '0'; en_count <= '1'; en_sig_diff_reg <= '1';

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en_sign_result <= '0'; en_exp_result <= '0'; en_output_result <= '0'; when st_end => en_sig1 <= '0'; reset_count <= '0'; en_count <= '0'; en_sig_diff_reg <= '0'; en_sign_result <= '0'; en_exp_result <= '0'; en_output_result <= '1'; end case; end process add_sub; P_sequencer : process(clock) begin if (clock'event and clock = '1') then if (reset = '1') then pres_st <= st_init; else case pres_st is when st_init => if(start = '1') then pres_st <= st0; else pres_st <= st_init; end if; when st0 => if(true_zero_reg = '1') then pres_st <= st_end; else pres_st <= st1; end if; when st1 => if ( count < 23) then pres_st <= st1; else pres_st <= st_end; end if; when st_end =>

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pres_st <= st_init; end case; end if; end if; end process; end rtl_Fdiv; 4. RT-level VHDL code of SEXP Block library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.all; entity exp_sin_cos is port(Dbus : inout std_logic_vector(24 downto 0); clock, reset : in std_logic; b2fc : in std_logic_vector(3 downto 0); f2bc : in std_logic_vector(3 downto 0)); end exp_sin_cos; architecture rtl_exp_sin_cos of exp_sin_cos is type state is (init, exp1, exp2, exp3, exp4, exp5, exp_end); type exp_table is array(0 to 26) of signed(24 downto 0); component shifter port ( inp : in signed(24 downto 0); count : in signed(4 downto 0); sign : in std_logic; oup : out signed(24 downto 0)); end component; signal en_Xext_reg : std_logic; signal present_state : state; signal counter : integer range 0 to 27; signal Wi_Yi_reg : signed(24 downto 0); signal B_shifter_out : signed(24 downto 0); signal add_sub_out : signed(24 downto 0); signal mux2_out, selector_out : signed(24 downto 0); signal Xext_reg, Xint_reg : signed(24 downto 0); signal sub_out : signed(24 downto 0); signal modifier_out : signed(24 downto 0); signal cclogic_out, start_reg : std_logic;

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signal cc_reg, en_cc_reg,reset_cc_reg : std_logic; signal exp_rom_out : signed(24 downto 0); signal sin_cos_rom_out : signed(24 downto 0); signal count : signed(4 downto 0); signal en_Wi_Yi_reg, reset_Wi_Yi_reg : std_logic; signal preset_Wi_Yi_reg : std_logic; signal en_Xint_reg : std_logic; signal selector_control,zero_force_control : std_logic; signal add_sub_control1,add_sub_control2 : std_logic; signal reset_start_reg : std_logic; signal preset_count : std_logic; signal reset_count : std_logic; signal en_count,sign_control : std_logic; signal cc_control : std_logic; begin --------------------------------------------------------- Sexp2bus : process(f2bc,Wi_Yi_reg) begin if (f2bc = "1001") then dbus <= std_logic_vector(Wi_Yi_reg); else dbus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZ"; end if; end process; --------------------------------------------------------- Sexp_decode : process(b2fc) begin if (b2fc = "1001") then en_Xext_reg <= '1'; else en_Xext_reg <= '0'; end if; end process; --------------------------------------------------------- PXext_reg : process(clock) begin if (clock'event and clock = '1') then if ( en_Xext_reg = '1') then Xext_reg <= signed(Dbus); end if; end if; end process; --------------------------------------------------------- Pstart_reg : process(clock) begin if (clock'event and clock = '1') then

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if ( reset = '1') then start_reg <= '0'; elsif ( b2fc = "1001") then start_reg <= '1'; else start_reg <= '0'; end if; end if; end process; ------------------------------------------------------------ PXint_reg : process(clock) begin if (clock'event and clock = '1') then if (en_Xint_reg = '1') then Xint_reg <= selector_out; end if; end if; end process; Pcounter : process(clock) begin if (clock'event and clock = '1') then if(preset_count = '1') then counter <= 1; elsif(reset_count = '1') then counter <= 0; elsif (en_count = '1') then counter <= counter + 1; end if; end if; end process; ------------------------------------------------------------ PWi_Yi_reg : process(clock) begin if (clock'event and clock = '1') then if(preset_Wi_Yi_reg = '1') then Wi_Yi_reg <= "0100000000000000000000000"; elsif(reset_Wi_Yi_reg = '1') then Wi_Yi_reg <= "0000000000000000000000000"; elsif (en_Wi_Yi_reg = '1') then Wi_Yi_reg <= add_sub_out; end if; end if; end process;

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------------------------------------------------------------ mux2_out <= Wi_Yi_reg; ------------------------------------------------------------ Pselector : process(sub_out,Xext_reg,selector_control) begin if ( selector_control = '0') then selector_out <= sub_out; elsif ( selector_control = '1') then selector_out <= Xext_reg; end if; end process; ------------------------------------------------------------ modifier_out <= exp_rom_out; ------------------------------------------------------------ Pcc_logic : process(sub_out,cc_control) begin if ( cc_control = '0') then if (sub_out <= 0) then cclogic_out <= '1'; else cclogic_out <= '0'; end if; else if (sub_out >= 0) then cclogic_out <= '1'; else cclogic_out <= '0'; end if; end if; end process; ------------------------------------------------------------ Pcc_reg : process(clock) begin if (clock'event and clock = '1') then if (en_cc_reg = '1') then cc_reg <= cclogic_out; end if; end if; end process; ------------------------------------------------------------ -- instance of barrel shifter

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------------------------------------------------------------ count <= to_signed(counter,5); b1 : shifter port map ( mux2_out, count, mux2_out(24), B_shifter_out); ------------------------------------------------------------ Padd_sub1 : process(mux2_out,B_shifter_out,add_sub_control1) begin if (add_sub_control1 = '1') then add_sub_out <= mux2_out - B_shifter_out; elsif (add_sub_control1 = '0') then add_sub_out <= mux2_out + B_shifter_out; end if; end process; ------------------------------------------------------------ Padd_sub2 : process(modifier_out,Xint_reg,add_sub_control2) begin if (add_sub_control2 = '1') then sub_out <= Xint_reg - modifier_out; elsif (add_sub_control2 = '0') then sub_out <= Xint_reg + modifier_out; end if; end process; ------------------------------------------------------------ Pexp_rom_out : process(counter) constant exp_rom1 : exp_table := (("0000000000000000000000000"), ("1101001110100011011110100"), ("1110110110010110100111100"), ("1111011101110100001110001"), ("1111101111011110100110100"), ("1111110111110111110101001"), ("1111111011111101111110101"), ("1111111101111111011111111"), ("1111111110111111111000000"), ("1111111111011111111110000"), ("1111111111101111111111100"), ("1111111111110111111111110"), ("1111111111111100000000000"), ("1111111111111110000000000"),

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("1111111111111111000000000"), ("1111111111111111100000000"), ("1111111111111111110000000"), ("1111111111111111111000000"), ("1111111111111111111100000"), ("1111111111111111111110000"), ("1111111111111111111111000"), ("1111111111111111111111100"), ("1111111111111111111111110"), ("1111111111111111111111111"), ("0000000000000000000000000"), ("0000000000000000000000000"), ("0000000000000000000000000")); constant exp_rom : exp_table := (("0010110001011100100001011"), ("0001100111110011001000111"), ("0000111001000111111110111"), ("0000011110001001110000011"), ("0000001111100001010001100"), ("0000000111111000001010011"), ("0000000011111110000001010"), ("0000000001111111100000001"), ("0000000000111111111000000"), ("0000000000011111111110000"), ("0000000000001111111111100"), ("0000000000000111111111111"), ("0000000000000011111111111"), ("0000000000000001111111111"), ("0000000000000000111111111"), ("0000000000000000011111111"), ("0000000000000000001111111"), ("0000000000000000001000000"), ("0000000000000000000100000"), ("0000000000000000000001111"), ("0000000000000000000001000"), ("0000000000000000000000011"), ("0000000000000000000000001"), ("0000000000000000000000000"), ("0000000000000000000000000"), ("0000000000000000000000000"), ("0000000000000000000000000")); begin if(Xint_reg(24) = '0') then exp_rom_out <= exp_rom(counter);

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else exp_rom_out <= exp_rom1(counter); end if; end process; ------------------------------------------------------------ -- controller for the above exp ------------------------------------------------------------ controls : process ( present_state ) begin case present_state is when init => preset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '0'; en_Xint_reg <= '0'; reset_cc_reg <= '1'; en_cc_reg <= '0'; preset_count <= '0'; reset_count <= '1'; en_count <= '0'; selector_control <= '0'; add_sub_control1 <= '0'; cc_control <= '0'; reset_start_reg <= '0'; add_sub_control2 <= '0'; when exp1 => preset_Wi_Yi_reg <= '1'; en_Wi_Yi_reg <= '0'; en_Xint_reg <= '1'; reset_cc_reg <= '0'; en_cc_reg <= '0'; preset_count <= '1'; reset_count <= '0'; en_count <= '0'; selector_control <= '1'; add_sub_control1 <= '0'; cc_control <= '0'; reset_start_reg <= '0'; add_sub_control2 <= '1'; when exp2 => preset_Wi_Yi_reg <= '0';

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en_Wi_Yi_reg <= '0'; en_Xint_reg <= '0'; reset_cc_reg <= '0'; en_cc_reg <= '1'; preset_count <= '0'; reset_count <= '0'; en_count <= '0'; selector_control <= '1'; add_sub_control1 <= '0'; cc_control <= '0'; reset_start_reg <= '0'; add_sub_control2 <= '1'; when exp3 => preset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '0'; en_Xint_reg <= '0'; reset_cc_reg <= '0'; en_cc_reg <= '0'; preset_count <= '0'; reset_count <= '0'; en_count <= '0'; selector_control <= '0'; add_sub_control1 <= '0'; cc_control <= '0'; reset_start_reg <= '0'; add_sub_control2 <= '1'; when exp4 => preset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '1'; en_Xint_reg <= '1'; reset_cc_reg <= '0'; en_cc_reg <= '0'; preset_count <= '0'; reset_count <= '0'; en_count <= '1'; selector_control <= '0'; add_sub_control1 <= '1'; Cc_control <= '0'; reset_start_reg <= '0'; add_sub_control2 <= '1'; when exp5 => preset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '1'; en_Xint_reg <= '1';

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reset_cc_reg <= '0'; en_cc_reg <= '0'; preset_count <= '0'; reset_count <= '0'; en_count <= '1'; selector_control <= '0'; add_sub_control1 <= '0'; cc_control <= '0'; reset_start_reg <= '0'; add_sub_control2 <= '0'; when exp_end => preset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '0'; en_Xint_reg <= '0'; reset_cc_reg <= '0'; en_cc_reg <= '0'; preset_count <= '0'; reset_count <= '0'; en_count <= '0'; selector_control <= '0'; add_sub_control1 <= '0'; cc_control <= '0'; reset_start_reg <= '1'; add_sub_control2 <= '0'; end case; end process; exp_fsm : process(clock) begin if (clock'event and clock='1') then if (reset = '1') then present_state <= init; else case present_state is when init => if (start_reg = '1') then present_state <= exp1; else present_state <= init; end if;

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when exp1 => present_state <= exp2; when exp2 => present_state <= exp3; when exp3 => if (cc_reg = '1') then present_state <= exp4; else present_state <= exp5; end if; when exp4 => if (counter = 24) then present_state <= exp_end; else present_state <= exp2; end if; when exp5 => if (counter = 24) then present_state <= exp_end; else present_state <= exp2; end if; when exp_end => present_state <= init; end case; end if; end if; end process; end rtl_exp_sin_cos; 5. RT-level VHDL code of SCOS Block library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use work.all; entity SCOS is port(dbus : inout std_logic_vector(24 downto 0); clock, reset : in std_logic;

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b2fc :in std_logic_vector(3 downto 0); f2bc : in std_logic_vector(3 downto 0)); end SCOS; architecture rtl_SCOS of SCOS is type state is (init,sin_cos1,sin_cos2,sin_cos4,sin_cos5, sin_cos6,sin_cos7,sin_cos_end); type rom_0_25_25 is array(0 to 25) of signed(24 downto 0); component shifter port ( inp : in signed(24 downto 0); count : in signed(4 downto 0); sign : in std_logic; oup : out signed(24 downto 0)); end component; signal present_state : state; signal counter : integer range 0 to 26; signal Wi_Yi_reg, Zi_reg : signed(24 downto 0); signal Ziold_reg, mux1_out : signed(24 downto 0); signal B_shifter_out : signed(24 downto 0); signal add_sub_out : signed(24 downto 0); signal mux2_out, selector_out : signed(24 downto 0); signal Xext_reg, Xint_reg : signed(24 downto 0); signal sub_out : signed(24 downto 0); signal modifier_out : signed(24 downto 0); signal cclogic_out, start_reg : std_logic; signal sin_cos_rom_out : signed(24 downto 0); signal count : signed(4 downto 0); signal en_Wi_Yi_reg, reset_Wi_Yi_reg : std_logic; signal en_Zi_reg, preset_Zi_reg : std_logic; signal en_Ziold_reg, en_Xint_reg : std_logic; signal mux1_control,mux2_control,mux3_control : std_logic; signal selector_control,zero_force_control : std_logic; signal add_sub_control1,add_sub_control2 : std_logic; signal preset_count : std_logic; signal reset_count : std_logic; signal en_count,sign_control : std_logic; constant zero : signed(24 downto 0) := "0000000000000000000000000"; begin --------------------------------------------------------- load_Xext_reg : process(clock) begin

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if (clock'event and clock = '1') then if ( b2fc = "1000") then Xext_reg <= signed(dbus); end if; end if; end process; --------------------------------------------------------- load_start_reg : process(clock) begin if (clock'event and clock = '1') then if (reset = '1') then start_reg <= '0'; elsif ( b2fc = "1000") then start_reg <= '1'; else start_reg <= '0'; end if; end if; end process; --------------------------------------------------------- SCOS2bus : process(f2bc, Zi_reg) begin if ( f2bc = "1000") then dbus <= std_logic_vector(Zi_reg); else dbus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZ"; end if; end process; --------------------------------------------------------- PXint_reg : process(clock) begin if (clock'event and clock = '1') then if (en_Xint_reg = '1') then Xint_reg <= selector_out; end if; end if; end process; ------------------------------------------------------------ PZi_reg : process(clock) begin if (clock'event and clock = '1') then if (preset_Zi_reg = '1') then Zi_reg <= "0010011011011101000001010"; -- 1/k elsif (en_Zi_reg = '1') then Zi_reg <= add_sub_out; end if;

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end if; end process; ------------------------------------------------------------ PZiold_reg : process(clock) begin if (clock'event and clock = '1') then if (en_Ziold_reg = '1') then Ziold_reg <= Zi_reg; end if; end if; end process; ------------------------------------------------------------ Pcounter : process(clock) begin if (clock'event and clock = '1') then if(preset_count = '1') then counter <= 1; elsif(reset_count = '1') then counter <= 0; elsif (en_count = '1') then counter <= counter + 1; end if; end if; end process; ------------------------------------------------------------ PWi_Yi_reg : process(clock) begin if (clock'event and clock = '1') then if(reset_Wi_Yi_reg = '1') then Wi_Yi_reg <= "0000000000000000000000000"; elsif (en_Wi_Yi_reg = '1') then Wi_Yi_reg <= add_sub_out; end if; end if; end process; ------------------------------------------------------------ Pmux1 : process(Wi_Yi_reg,Ziold_reg,mux1_control) begin if ( mux1_control = '0') then mux1_out <= Wi_Yi_reg; elsif ( mux1_control = '1') then mux1_out <= Ziold_reg; end if;

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end process; ------------------------------------------------------------ Pmux2 : process(Wi_Yi_reg,Ziold_reg,mux2_control) begin if ( mux2_control = '0') then mux2_out <= Wi_Yi_reg; elsif ( mux2_control = '1') then mux2_out <= Ziold_reg; end if; end process; ------------------------------------------------------------ Pselector : process(sub_out,Xext_reg,selector_control) begin if ( selector_control = '0') then selector_out <= sub_out; elsif ( selector_control = '1') then selector_out <= Xext_reg; end if; end process; ------------------------------------------------------------ Pmodifier : process(zero_force_control,sin_cos_rom_out) begin if ( zero_force_control = '1') then modifier_out <= zero; else modifier_out <= sin_cos_rom_out; end if; end process; ------------------------------------------------------------ Pcc_logic : process(sub_out) begin if (sub_out >= 0) then cclogic_out <= '1'; else cclogic_out <= '0'; end if; end process; ------------------------------------------------------------ -- instance of barrel shifter ------------------------------------------------------------ count <= to_signed(counter,5);

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b1 : shifter port map ( mux1_out, count, mux1_out(24), B_shifter_out); ------------------------------------------------------------ Padd_sub1 : process(mux2_out,B_shifter_out,add_sub_control1) begin if (add_sub_control1 = '1') then add_sub_out <= mux2_out - B_shifter_out; elsif (add_sub_control1 = '0') then add_sub_out <= mux2_out + B_shifter_out; end if; end process; ------------------------------------------------------------ Padd_sub2 : process(modifier_out,Xint_reg,add_sub_control2) begin if (add_sub_control2 = '1') then sub_out <= Xint_reg - modifier_out; elsif (add_sub_control2 = '0') then sub_out <= Xint_reg + modifier_out; end if; end process; ------------------------------------------------------------ Psin_cos_rom_out : process(counter) constant sin_cos_rom : rom_0_25_25 := (("0011001001000011110101000"), ("0001110110101100010001110"), ("0000111110101101100101101"), ("0000011111110101011011101"), ("0000001111111110101100000"), ("0000000111111111110100011"), ("0000000011111111111110101"), ("0000000001111111111111110"), ("0000000000111111111111111"), ("0000000000011111111111111"), ("0000000000001111111111111"), ("0000000000000111111111111"), ("0000000000000011111111111"), ("0000000000000001000000000"), ("0000000000000000100000000"), ("0000000000000000010000000"), ("0000000000000000001000000"),

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("0000000000000000000100000"), ("0000000000000000000010000"), ("0000000000000000000001000"), ("0000000000000000000000100"), ("0000000000000000000000010"), ("0000000000000000000000001"), ("0000000000000000000000001"), ("0000000000000000000000001"), ("0000000000000000000000000")); begin sin_cos_rom_out <= sin_cos_rom(counter); end process; ------------------------------------------------------------- controller for the above exp ------------------------------------------------------------ controls : process ( present_state ) begin case present_state is when init => reset_Wi_Yi_reg <= '1'; en_Wi_Yi_reg <= '0'; preset_Zi_reg <= '0'; en_Zi_reg <= '0'; en_Ziold_reg <= '0'; en_Xint_reg <= '0'; preset_count <= '0'; reset_count <= '1'; en_count <= '0'; mux1_control <= '0'; mux2_control <= '0'; selector_control <= '0'; add_sub_control1 <= '0'; zero_force_control <= '0'; add_sub_control2 <= '0'; when sin_cos1 => reset_Wi_Yi_reg <= '1'; en_Wi_Yi_reg <= '0'; preset_Zi_reg <= '1'; en_Zi_reg <= '0'; en_Ziold_reg <= '0'; en_Xint_reg <= '1'; preset_count <= '0';

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reset_count <= '0'; en_count <= '0'; mux1_control <= '0'; mux2_control <= '0'; selector_control <= '1'; add_sub_control1 <= '0'; zero_force_control <= '1'; add_sub_control2 <= '0'; when sin_cos2 => reset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '0'; preset_Zi_reg <= '0'; en_Zi_reg <= '0'; en_Ziold_reg <= '1'; en_Xint_reg <= '0'; preset_count <= '0'; reset_count <= '0'; en_count <= '0'; mux1_control <= '0'; mux2_control <= '0'; selector_control <= '0'; Add_sub_control1 <= '0'; zero_force_control <= '1'; add_sub_control2 <= '0'; when sin_cos4 => reset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '0'; preset_Zi_reg <= '0'; en_Zi_reg <= '1'; en_Ziold_reg <= '0'; en_Xint_reg <= '1'; preset_count <= '0'; reset_count <= '0'; en_count <= '0'; mux1_control <= '0'; mux2_control <= '1'; selector_control <= '0'; add_sub_control1 <= '1'; zero_force_control <= '0'; add_sub_control2 <= '1'; when sin_cos5 => reset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '1'; preset_Zi_reg <= '0';

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en_Zi_reg <= '0'; en_Ziold_reg <= '0'; en_Xint_reg <= '0'; preset_count <= '0'; reset_count <= '0'; en_count <= '1'; mux1_control <= '1'; mux2_control <= '0'; selector_control <= '0'; add_sub_control1 <= '0'; zero_force_control <= '0'; add_sub_control2 <= '1'; when sin_cos6 => reset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '0'; preset_Zi_reg <= '0'; en_Zi_reg <= '1'; en_Ziold_reg <= '0'; en_Xint_reg <= '1'; preset_count <= '0'; reset_count <= '0'; en_count <= '0'; mux1_control <= '0'; mux2_control <= '1'; selector_control <= '0'; add_sub_control1 <= '0'; zero_force_control <= '0'; add_sub_control2 <= '0'; when sin_cos7 => reset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '1'; preset_Zi_reg <= '0'; en_Zi_reg <= '0'; en_Ziold_reg <= '0'; en_Xint_reg <= '0'; preset_count <= '0'; reset_count <= '0'; en_count <= '1'; mux1_control <= '1'; mux2_control <= '0'; selector_control <= '0'; add_sub_control1 <= '1'; zero_force_control <= '0'; add_sub_control2 <= '0';

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when sin_cos_end => reset_Wi_Yi_reg <= '0'; en_Wi_Yi_reg <= '0'; preset_Zi_reg <= '0'; en_Zi_reg <= '0'; en_Ziold_reg <= '0'; en_Xint_reg <= '0'; preset_count <= '0'; reset_count <= '0'; en_count <= '0'; mux1_control <= '0'; mux2_control <= '0'; selector_control <= '0'; add_sub_control1 <= '0'; zero_force_control <= '0'; add_sub_control2 <= '0'; end case; end process; exp_fsm : process(clock) begin if (clock'event and clock='1') then if (reset = '1') then present_state <= init; else case present_state is when init => if (start_reg = '1') then present_state <= sin_cos1; else present_state <= init; end if; when sin_cos1 => present_state <= sin_cos2; when sin_cos2 => if (cclogic_out = '1') then present_state <= sin_cos4; else present_state <= sin_cos6;

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end if; when sin_cos4 => present_state <= sin_cos5; when sin_cos5 => if (counter = 24) then present_state <= sin_cos_end; else present_state <= sin_cos2; end if; when sin_cos6 => present_state <= sin_cos7; when sin_cos7 => if (counter = 24) then present_state <= sin_cos_end; else present_state <= sin_cos2; end if; when sin_cos_end => present_state <= init; end case; end if; end if; end process; end rtl_SCOS; 6. RT-level VHDL code of IGEN Block library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity IGEN is port (clock,reset : in std_logic; b2fc : in std_logic_vector(3 downto 0); f2bc : in std_logic_vector(3 downto 0); dbus : out std_logic_vector(19 downto 0)); end IGEN; architecture rtl_IGEN of IGEN is

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type state is (state_ran0,state_ran1,state_ran2,state_ran3,state_ran4); component random port( sreg : in std_logic_vector(14 downto 0); rand : out signed(14 downto 0)); end component; signal ran_state : state; signal start_noise_reg : std_logic; signal reset_count : std_logic; signal preset_S_reg : std_logic; signal en_S_reg : std_logic; signal reset_noise_reg : std_logic; signal en_noise_reg : std_logic; signal en_count : std_logic; signal S_reg : signed(14 downto 0); signal S_mod : std_logic_vector(14 downto 0); signal mult_out : signed(14 downto 0); signal sub_out : signed(19 downto 0); signal add_out : signed(19 downto 0); signal noise_reg : signed(19 downto 0); signal one_bit_rshift : signed(19 downto 0); signal counter : integer range 0 to 13; constant second_sub : signed(19 downto 0) := "00000100000000000000"; begin ---------------------------------------------------------------- load_start_IGEN : process(clock) begin if (clock'event and clock = '1') then if (reset = '1') then start_noise_reg <= '0'; elsif (b2fc = "1111") then start_noise_reg <= '1'; else start_noise_reg <= '0'; end if; end if; end process; ---------------------------------------------------------- IGEN2bus : process(f2bc,noise_reg) begin if (f2bc = "1010") then dbus <= std_logic_vector(noise_reg);

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else dbus <= "ZZZZZZZZZZZZZZZZZZZZ"; end if; end process; ------------------------------------------------------------- PS_reg : process(clock) begin if(clock'event and clock = '1') then if (preset_S_reg = '1') then S_reg <= "000000000000001"; elsif (en_S_reg = '1') then S_reg <= mult_out; end if; end if; end process; -------------------------------------------------------------- Pnoise_reg : process(clock) begin if(clock'event and clock = '1') then if (reset_noise_reg = '1') then noise_reg <= "00000000000000000000"; elsif (en_noise_reg = '1') then noise_reg <= add_out; end if; end if; end process; ---------------------------------------------------------------- Pcounter : process(clock) begin if(clock'event and clock = '1') then if (reset_count = '1') then counter <= 1; elsif (en_count = '1') then counter <= counter + 1; end if; end if; end process; ----------------------------------------------------------- S_mod <= std_logic_vector(S_reg); U1 : random port map(S_mod, mult_out); sub_out <= (("00000" & S_reg) - second_sub); one_bit_rshift <= sub_out(19) & sub_out(19 downto 1);

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add_out <= ( one_bit_rshift + noise_reg); --controller for the random no. generator Pcontrolword : process(ran_state) begin case ran_state is when state_ran0 => preset_S_reg <= '1'; en_S_reg <= '0'; reset_noise_reg <= '0'; en_noise_reg <= '0'; reset_count <= '0'; en_count <= '0'; when state_ran1 => preset_S_reg <= '0'; en_S_reg <= '0'; reset_noise_reg <= '1'; en_noise_reg <= '0'; reset_count <= '1'; en_count <= '0'; when state_ran2 => preset_S_reg <= '0'; en_S_reg <= '1'; reset_noise_reg <= '0'; en_noise_reg <= '1'; reset_count <= '0'; en_count <= '0'; when state_ran3 => preset_S_reg <= '0'; en_S_reg <= '1'; reset_noise_reg <= '0'; en_noise_reg <= '1'; reset_count <= '0'; en_count <= '1'; when state_ran4 => preset_S_reg <= '0'; en_S_reg <= '1'; reset_noise_reg <= '0'; en_noise_reg <= '1';

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reset_count <= '0'; en_count <= '0'; end case; end process; --state sequencer for the random no. generator noise_control : process(reset, clock) begin if ( clock'event and clock = '1') then if (reset = '1') then ran_state <= state_ran0; else case ran_state is when state_ran0 => ran_state <= state_ran1; when state_ran1 => if (start_noise_reg = '0') then ran_state <= state_ran1; elsif (start_noise_reg = '1') then ran_state <= state_ran2; end if; when state_ran2 => ran_state <= state_ran3; when state_ran3 => if (counter < 10 ) then ran_state <= state_ran3; else ran_state <= state_ran4; end if; when state_ran4 => ran_state <= state_ran1; end case; end if; end if; end process; end rtl_IGEN;