limits of low noise performance of detector readout front ends in cmos technology

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, V o l . 37. NO. 11, NOVEMBER 1990 1375

Limits of Low Noise Performance of Detector Readout Front Ends

in CMOS Technology

Abstract -The limits of the noise performance of detector readout front ends in CMOS technology have been studied. A theoretical minimal number of equivalent noise charge (ENC) that can be achieved by a CMOS technology is derived, taking both the thermal noise and 1/f noise into account. Design criteria and techniques of CMOS readout front ends are presedted so as to fully exploit the maximal capability of a CMOS technology. The optimal input transistor dimensions and bias conditions of charge sensitive amplifiers (CSA) are analytically determined. For readout front ends using semi-Gaussian pulse shapers, the optimal number of integrators and the optimal peaking time are determined as well from the point of view of achieving the best detector resolution.

In order to verify the theoretical analyses, a charge sensitive amplifier and a fourth-order semi-Gaussian pulse shaper with 1-ps peaking time have been designed in a standard 3-pm CMOS technology. Calculations and computer simulations show that by optimal design of input CSA and semi-Gaussian pulse shaper, a detector resolution as low as 600 equivalent noise electrons can be obtained for a 40-pF detector capacitance.

I. INTRODUCTION N ELEMENTARY-particle physics, the energies of I radiation particles are measured by means of a semi-

conductor detector readout system. A principal schema of such a detection system is depicted in Fig. 1. An inverse biased diode (Si or Oe) detects radiation events by gener- ating electron-hole pairs proportional to the absorbed energies. A low-noise charge sensitive amplifier (CSA) is widely used at the front end due to its low noise configu- ration and insensitivity of the gain to the detector capacitance variations. The generated charge Q is integrated onto a small feedback capacitance C,, which gives rise to a step voltage signal at the output of the CSA with an amplitude equal to Q/C,. The step signal is fed to a main amplifier, often called a pulse shaper, where pulse shaping is performed primarily to optimize the S/N ratio of the system. In all cases, the resulting output signal is a rather narrow pulser suitable for further processing. De- pending on applications, the pulse processing unit can be simply a multichannel analyzer (MCA), a series of dis- criminators, or sample-hold circuits in a multichannel

Manuscript received July 13, 1989: revised June 18, 1990. This paper

The authors are with the Katholieke Universiteit Leuven, B-3030

IEEE Log Number 9038545.

was recommended by Associate Editor R. K. H a t e r .

Heverlee, Belgium.

H V

, t I1

II Cf

Fig. 1. Principal block diagram of a detector readout system.

system to store the informations for serial readout. For resolution analyses, the detail of the circuits in the processing unit is of no concern and only the CSA and the pulse shaper will be considered.

In most modern semiconductor detector systems, printed circuit and hybrid electronics are still the main approaches to the readout front ends. Discrete junction field effect transistors (JFET’s) are used universally as input amplifying elements mainly due to their high input impedance and low noise characteristics. As the number of identical readout channels is continually increasing, the requirements of low power consumption, low noise, and small size of the readout electronics become more severe. For example, a silicon microstrip detector used in high energy and collider experiments can contain up to 1000 strips with a readout pitch of only several 10 p m [11-[31. To read out such a large number of channels, the printed circuits and hybrid electronics currently available are clearly inadequate and monolithic integration seems to be the only approach to the design of the readout system.

Recently, continuing efforts have been made to imple- ment multichannel readout systems in a monolithic form [4]-[7]. CMOS technologies have been chosen for integration due to the high integration density, low power consumption, and capability of combining both digital and analog circuits on the same chip. As the CMOS approach is just in the beginning phase, no comprehensive study has been published so far on the maximal capability of CMOS technology for the implementation of detector readout systems.

It is the aim of this paper to determine the upper limit of the detector resolution that can be achieved by using a CMOS approach, and to show design criteria and tech-

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niques of readout front ends in order to fully exploit the capability of CMOS technology. In the next section, the resolution of a detector readout system implemented in a CMOS technology is calculated, taking both the thermal and l/f noise into account. It is the first time that a generalized analysis is performed for a CMOS detector readout system using a semi-Gaussian pulse shaper of an arbitrary order. In Section 111, the optimal design of charge sensitive amplifiers, which are the key building blocks of detector readout front ends, is performed. The theoretical maximal resolution and optimal input transistor dimensions and bias conditions will be derived. A CMOS CSA matching a 40-pF detector capacitance is designed to check the theoretical analyses. Section IV is devoted to the optimal design of CMOS pulse shapers where the optimal order and the optimal peaking time are determined from the point of view of achieving the best detector resolution. A design example will be given to illustrate the theoretical analyses. It is shown that by optimal design of the CSA and the pulse shaper detector resolution as low as 600 equivalent noise electrons can be achieved for a detector with 40-pF capacitance. This is more than a factor of two better than the best results recently published [41, [51, [71.

11. EQUIVALENT NOISE CHARGES In the detector world, the noise performance of a

detector readout system is generally expressed as the equivalent noise charge (ENC). The equivalent noise charge ENC is defined as the ratio of the total integrated rrns noise at the output of the pulse shaper to the signal amplitude due to one electron charge q. Clearly, the ENC depends on the characteristics of both the charge sensitive amplifier and the pulse shaper. Many studies have been performed on the pulse shapers in terms of the S/N performance and counting-rate behavior [81, [9]. It has been concluded that the optimum choice of pulse shaper depends strongly on applications, and for a given applica- tion one must assess the trade-offs among different design parameters. In this paper all analyses will be carried out for semi-Gaussian shapers, which are the most common pulse shapers employed in readout systems [41, [81.

In principle, either the time-domain or frequency- domain approach can be used to calculate the ENC of a detector readout system [9]-[ll]. While the analysis in the frequency domain is more straightforward and familiar to most scientists, the time-domain approach is more conve- nient for making comparison of the S/N performances between different pulse shapers. The reason is that it gives an intuitive picture of the effect of the different pulse shaper parameters on the S/N performance. How- ever, the time-domain approach has thus far been limited to the treatment of the thermal and shot noise. The l/f noise can not be dealt with by this method. As CMOS technologies have inherently much higher l/f noise, the frequency domain analysis must be adopted in order to investigate the effect of l/f noise.

r I ...............................................................................

: 2

n integrators ...............................................................................

Semi-Gaussian shaper

Fig. 2. Noise sources in a detector readout system.

The noise of a detector readout front end can always be represented by an equivalent input voltage noise generator and an equivalent input current noise generator, as shown in Fig, 2. c d represents the detector capacitance. With the generally accepted assumption that the total system noise is dominated by the input device of the CSA, the two equivalent input noise sources are given by

(2) ' e q i = . 2 [ S ( C G S + C G D ) ] 2 r c ? q i

where gm is the transconductance, C,, is the gate-source capacitance, and C,, is the gate-drain capacitance of the input MOS transistor. The first term in (1) represents the channel thermal noise and the second term represents the l /f noise of the input MOS transistor where K , is the l /f noise coefficient of the CMOS process used [12], [13]. In addition to the amplifier noise, the detector leakage current and its associated bias network give rise to another noise component, which is the shot noise. It is generally expressed as

i: = 2q1, ( 3 ) where I, is the sum of the detector leakage current and the equivalent noise current of the bias network.

From the expressions (11, (21, and (3) , the total noise power spectrum at the output of the charge sensitive amplifier is calculated to be

The first term is due to the amplifier noise and the second is the contribution of the detector leakage current and its associated bias network. In order to calculate the ENC the total integrated rms noise at the output of the pulse shaper must be calculated. The transfer function of a semi-Gaussian pulse shaper consisting of one RC differentiator and n integrators (see Fig. 2) is given by

H ( s ) = [ - 1 ::J [ ~ 1 +As7,]n (5)

where T, is the time constant of the differentiator and integrators, and A is the dc gain of the integrators. The number n of integrators is called the order of the semi- Gaussian shaper. The noise power spectrum at the output of CSA is weighted by the transfer function ( 5 ) of the

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B (:, n - f ) 1.57 0.39 0.20 0.12 0.086

SANSEN AND CHANG: DETECTOR READOUT FRONT ENDS

shaper. The total integrated rms noise is then given by

7

0.063 0.051 In order to calculate the ENC of the detector system, the signal amplitude at the pulse shaper output due to one electron charge must be determined as well.

A. Signal Amplitude Due to One Electron Charge The signal due to one electron charge delivered by the

detector can be represented as a Dirac current impulse, the integral of which is equal to q corresponding to one electron charge. It can be shown that the output signal of the CSA is an exponentially rising step function with a time constant T , proportional to the detector capacitance and inversely proportional to the GBW of the core amplifier. The steady state amplitude of the step signal is equal to q/Cf. In practice, the value of T~ can be made as low as several nanoseconds so that the output signal can be approximated as an ideal step signal with an amplitude of q / C f . In the frequency domain, the signal at the output of the pulse shaper is simply given by the product of the transfer function H ( s ) of the pulse shaper and the Laplace transform of the step signal that is equal to q/sCCf . By taking the inverse Laplace transform of the product, the output signal in the time domain is obtained:

B ( i , n + l )

n!2e2n,n2n

2 2

(7)

1.57 1.17 0.98 0.86 0.77 0.71 0.66

7.39 13.64 19.92 26.20 32.48 38.76 45.04

where T,, called peaking time of the shaper, is defined by T$ = n ~ , . Equation (7) has a semi-Gaussian pulse shape in the time domain. It can be easily verified by taking the derivative of (7) with respect to time t that the signal VOut(t> reaches the peak amplitude at the peaking time 7,.

The peak amplitude of the signal pulse is calculated by evaluating (7) at peaking time T , and is given by

qAnnn

C, n !e" V,"tnl,X = ___.

The peak amplitude is thus proportional to the generated charge q. Therefore, by measuring the peak amplitude the energy of radiation particles can be determined. Note that for n = 1 the above expression is reduced to the classical expression for the simplest first order RC - RC pulse shapers [81.

The ENC of the detector system is calculated as the ratio of the total integrated rms noise in (6) to the peak amplitude of the output signal given in (8). As the total noise power spectrum u,(s) in (4) or (6) contains three independent noise components, which are the channel thermal noise, l/f noise, and the shot noise, it is better to deal with each component separately.

B. ENC Due to Channel Thermal Noise: ENC, The thermal noise source associated with the channel

resistance of the input MOS transistor is given by the first term in (1). Filling in the general expression (61, the total

integrated rms thermal noise becomes explicitly as given by

where C, = C, + C, + C,, + CGD. In general, the above integral cannot be solved under a closed form. Fortu- nately, for all practical cases where n is an integer, it can be shown that the solution of the above integral is given by the following equation:

\ - - ,

where B ( x , y ) is the beta-function. Dividing the above expression to the signal amplitude due to one electron charge, the ENC, due to the channel thermal noise is obtained:

This is a general expression for the ENC, due to the channel thermal noise and is valid for all detector systems using semi-Gaussian pulse shapers of an arbitrary order. For the simplest RC - RC semi-Gaussian pulse shaper, (11) reduces to the classical expression for ENC, [81. From (11) the effect of the pulse shaper characteristics on the detector resolution can be evaluated. Obviously, the use of pulse shapers with large peaking time T , always has the effect of limiting the thermal noise. Evaluation of the effects of the order n on the ENC, is clearly more complicated. For clearness, the values of B(3 /2 , n - 1/2) and last product term are listed in Table I. With the help of Table I the value of the ENC, can be calculated from (1 1). For example, for a detector readout front end having C, = 60 pF, gm = 10 mS, n = 4, and T , = 1 ps, the ENC, is calculated from (11) to be 390 noise electrons.

C. ENC Due to 1 / f Noise: ENCf In the design of detector readout systems using discrete

JFET transistors the effect of l/fnoise has been generally neglected. However, as a CMOS process has much higher l/f noise, its effect on the detector resolution must be examined as well. The l/f noise source of the input MOS transistor is given by the second term in (1).

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Evaluation of the integral (6) for the l/f noise yields as the total rms output l/f noise:

The ENCf is calculated as the ratio of (12) to (8). It is given by

An important conclusion drawn from (13) is that the ENC, due to the l / f noise is totally independent of the time constant T , of the pulse shaper and only slightly depends on the number of the integrators in the pulse shaper. It strongly depends on the process parameters K,, CO,, and the input MOS transistor dimensions. If an MOS input transistor with WL = 30 000 p m 2 is used and the CMOS process used has Kf = 6.1OP3' C2/cm2 and C,,x = 0.8 fF/pm2 [12], [13], then for the same example above, the ENCf is calculated to be 380 noise electrons, which is comparably as important as the channel thermal noise.

D. ENC Due to 241, Noise: ENC, For the noise component 2q10, due to the detector

leakage current and the associated bias circuit, the integral (6) is calculated to be

111. OPTIMAL DESIGN OF CHARGE SENSITIVE AMPLIFIERS

In the previous section, the ENC's of the detector system using a semi-Gaussian shaper have been analytically derived. The design parameters of the CSA that affect the ENC's are the input MOS transistor dimensions and dc bias conditions. A careful examination of the three ENC's given by (111, (131, and (15) reveals that the optimization of each ENC separately is equivalent to minimizing the equivalent input noise current in parallel with the signal source due to each noise source. This allows optimizing the noise performance of the CSA separately without any reference to the characteristics of the pulse shaper, which makes the calculations easier. However, to optimize the total ENC,, the shaper characteristic must be taken into account as well, which will result in analyses that are too complicated. To avoid elaborate calculations and the loss of insight into the optimization procedures, each ENC is optimized individu- ally at first. Once the effects of the input transistor dimensions and dc bias conditions on each ENC are well-determined, the optimization of the total ENC, can be obtained numerically.

In order to determine the effect of the input transistor dimensions and dc bias conditions on the ENC's, the input capacitance and transconductance of the input MOS transistor must be explicitly expressed in terms of these parameters as given by

The corresponding ENC, is given by

In contrast to the ENC,, due to the channel thermal noise, ENC, is proportional to the peaking time 7, of the pulse shaper. Furthermore, it depends only on the shaper characteristics and is totally independent of the characteristics of the CSA. The value of the function B(1/2 , n + 1/2) is given in Table I. For the same example above and assuming a total leakage current I , = 10 nA, from (15) the ENC, is calculated to be 230 noise electrons.

The total equivalent noise charge ENC, is simply given by the sum of the ENC's due to three individual noise sources given in (111, (131, and (15):

ENC, = dENC: + ENC; + ENC; . (16)

In the following sections the effect of the design parameters of CSA and pulse shaper on the ENC's will be investigated in more detail. The optimal input transistor characteristics of the CSA and the optimal peaking time and order n of the pulse shaper will be determined in order to obtain the minimal total ENC,.

2 3

C,, = -CO, WL and C,, = C,,WL, ( 17)

Combining (17) and (18) with the expression (11) for the ENC, due to the channel thermal noise, it can be easily seen that in order to minimize the ENC,, the minimal transistor gatelength L and the maximal dc bias level Z,, must be chosen. The transistor gatewidth W has a double effect. On the one hand, the increase in the gatewidth reduces the transistor channel thermal noise due to the increase in the transistor transconductance g,. On the other hand, the increase in the gatewidth impairs the S/N performance due to the increase in the input capacitance. As a result, an optimal gatewidth must exist for which the ENC, is minimal. It is calculated by solving the equation of the derivative of (11) with respect to the gatewidth W. It is given by

where a is defined as CUL = L +3L,, which is very close to unity for long channel devices. Filling the optimal WO,,

7- 7

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due to the channel thermal noise and requirements re- lated to the GBW and the response speed, etc., a minimal transistor gatelength should be chosen. The corresponding minimal ENCfmi, is obtained by filling (21) in (13) as given by

ENC& =

This theoretical minimal ENCfmin is totally independent of any design parameters of the CSA and depends only on the process parameters for a given detector capacitance. Furthermore, it depends only slightly on the order of the pulse shaper as will be shown in the next section. The fact that for a given capacitive source ENC,,, only depends on the basic process parameters K , and CO, means that it sets the lowest limit of ENC that can be achieved by using a specific CMOS technology. In Fig. 3 , the ENCfmi, is plotted as a function of detector capacitances together with the ENCdmi,. For small detector capacitance the effect of ENCfmi, is very important, while for a large detector capacitance ENC,,, plays the most significant role. It should be emphasized that it is always possible to lower the ENC,,, curve by increasing dc bias current or peaking time, but the curve ENC,,,,, on the other hand, cannot be changed without process improvement. It gives the maximal capability of a CMOS technology. For example, using a CMOS technology with Kf = 6.10-31 C2,cm2 and cox = o.8 fF/Pm2 [12~, it is not possible to design a CMOS readout system for a detector of 40 pF with a total ENC, lower than 340 electrons.

As mentioned in the previous section, in contrast to ENC, and ENC,, ENCo depends only on the detector and shaper characteristics and is totally independent of

CSA, ENCo is not significant. The final goal is to minimize the total equivalent noise

charges ENC, given by expression (16) rather than in& vidual ENC, and ENC,. Since the optimal input transistor gatewidths for ENC, and ENCf are different, it is not

-50 50 loo 150 2oo 250 300 350 400 450 500 Fig. 3. Theoretical minimal ENC's versus detector capacitance for

= 1 ps. NMOS input: L = 3 pm, semi-Gaussian shaper n = 4, IDS = 0.5 mA, K , = 6.'10-" C2,,?cm2.

in (11) yields the minimal ENC,, which is given by

128 (C, + C,)' L 6

J ~ ~ o s ( c , + c,> ENC;,~, = ?kz-

. (20)

This is the theoretical minimal ENC, due to the channel thermal noise of the input MOS transistor of the CSA. In order to minimize this minimum, a transistor with a minimal channel L must be chosen and a high DC bias current must be used. Also, the parasitic capacitances and feedback capacitance should be kept at minimum, in spite of the fact that they are noiseless components. For designers engaged in the detector design it is interesting to

tor capacitance C,. Fig. 3 shows the minimal ENCdmi, as a function of the detector capacitance C, in the case of using a fourth-order ( n = 4) semi-Gaussian shaper with 1 % ~ peaking time. As expected, the minimal ENC,min increases with the detector capacitance C,. For example,

the ENCdmin as a function Of the detec- characteristics of the CSA, so that for the design of the

if a detector with 40-pF capacitance is using an nMoS input transistor with cm2/V's, and IDS = 0.5 mA, then from (20) the

to be read Out

= 3pm, /1. = 6oo possible to derive optimal input transistor dimensions for ENC, analytically so that a numerical approach based on the results for ENC, and ENC, must be used. Fig. 4 shows schematically the effects of the transistor gatewidth on the ENC,, ENCf, and the sum of both ENC7s. It is readily recognized that the optimal gatewidth for the total ENC differs from the optimal for ENC, and ENC,

tion where the detector capacitance is given it is always possible to find the optimal gate W based on the numerical approach. As a rule of thumb one can approximate the optimal gatewidth simply as the average of both optima.

To verify the theoretical analyses, a CMOS CSA has been designed and integrated in a standard 3-pm CMOS technology with 1-pF feedback capacitance for 40-pF detector capacitance. The circuit schematic is shown in Fig. 5 . The core amplifier is basically a folded cascode ampli-

ENC,,, is calculated to be 345 noise electrons. While for ENC, an optimal transistor gatewidth exists,

for is minimal. It is derived by solving the equation of the

given by

an Optima' gate area is found for which

derivative Of (I3) with respect to gate area wL and is and lies between both. Clearly, for each specific applica-

(21)

The existence of the optimal gate area rather than gatewidth stems from the fact that the l/f noise source depends on WL and is independent of W / L ratio [12], [131. It means that as far as ENC, is concerned, either W or L may be chosen freely to meet the noise matching condition (21). However, taking into account the ENC,

3(c, + Cf> WLOPt = 2aC0x '

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1 o3

+ ENcd + END

ENCd+f - t w Iml I "

1 o3 1 o4 1 o5 Fig. 4. Effect of input transistor gatewidth W on ENC's. Parameters

are the same as in Fig. 3.

700 ENC's

400

300

200

100 0 2 4 6 8 10 12 14 16 18 20 22 24

Fig. 6. Effect of order n of shaper on ENC's of a readout system with T, = 1 ps.

[e I GND

R f Fig. 5. Circuit schematic of designed low noise CMOS CSA.

+ ENcd + ENCf +- ENCs - E N a

1 o3

102

fier. It can be shown that the impedances at the node 2 is low ( = l /gm2) for frequencies higher than go, /27rC, where go, is the output conductance of the cascode transistor M2. Since the frequency go, / 2xC, is very low, the Miller effect can be generally neglected.

In order to achieve the best noise performance the optimal input transistor dimensions are determined ac- cording to the above analyses. A bias current of 0.5 mA is chosen for the input transistor considering the noise and response speed requirements. As shown in (20) the higher the dc bias current the lower the thermal noise contribution will be. The maximal dc bias current is mainly limited by the available power supply V,, and dc bias voltages of MOS transistors. Once the input transistor noise is optimized the noise of other transistors must be minimized as well. This can be easily carried out because the input transistor provides a large power gain. Hand calculations and computer simulations show that the input MOS transistor contributes more than 90% to the total amplifier noise.

IV. OPTIMAL DESIGN OF PULSE SHAPERS The transfer function of a semi-Gaussian pulse shaper

given in ( 5 ) is fully characterized by the following three parameters: the time constant 7 , of the differentiator and

integrators, the dc gain A of integrators, and the number of integrators. As shown in the Section 11, the three ENC's are completely independent of the dc gain of integrators so that only 7, and n should be optimized from the point of view of achieving minimal number of total ENC,. Mathematically, the optimal 7, and n must be found by solving the following set of equations simulta- neously:

d ENC, = O

a7,

a ENC, -- - 0.

dn Unfortunately, the above set of equations can not be solved analytically. To obtain insight into the effects of T~ and n on the noise performance of the detector system, numerical methods must be adopted. In Fig. 6 the effect of order n on the three ENC's and total ENC, is plotted for a given peaking time 7, of 1 ps, while in Fig. 7 the effect of peaking time 7, is illustrated for n = 4. From Fig. 6 it is clear that when the peaking time T , is given, both ENC, and ENC, decrease with the order n. An inverse effect is observed for ENC, for n > 2. These combined effects lead to the important conclusion that for a given peaking time 7, an optimal order n of the

T

SANSEN AND CHANG: DETECTOR READOUT FRONT ENDS 1381

shaper exists for which the total ENC, is minimum. At first sight, the existence of the optimal order n or the increase in ENC, with n is not feasible. In fact, it is the direct result of the constraint T , = T, / n required to en- sure the output pulse to reach the top value at the peaking time 7,. This constraint means that if the peaking time T~ is given, then the time constant T , of the differentiator and integrators must be varied in inverse propor- tion to the order n of the shaper. The higher the order n , the smaller the T~ must be and the wider the frequency range that is covered by the transfer characteristic of the shaper.

Fig. 7 shows the effect of T , on the S/N performance of a shaper. As has been widely observed [SI, for a given order n of the shaper, ENC, is inversely proportional to T,, ENC, is proportional to it, and ENCf is independent of it. This results in an optimum peaking time from the point of view of the S/N performance. It can be shown that the optimum T , corresponds with the time at which the contributions of ENC, and ENC, are equal. It is interesting to note that for a given order n of the shaper, the optimum T, can be directly solved from the equation (23a), which is given by

It is worthwhile comparing the optimum T , of shapers in a CMOS technology with the shapers employing discrete JFET input devices. For a CMOS technology, the optimum T~ is always larger due to the negligible shot noise of the MOS transistor. Furthermore, the high l/f noise in a CMOS technology makes the curve around the optimum T$ more flat so that the choice of T, is less critical than in the case of using JFET. In practice, other constraints such as high counting rate requirement and pile-up problem [8] may force one to choose a peaking time T~ shorter than the optimum one.

The above noise analyses and discussions enable circuit designers to determine the optimal pulse shaper characteristics for a given detector capacitance in terms of S/N performance. As an example, a fourth-order semi- Gaussian shaper ( n = 4) with the corresponding optimal peaking time ~ , = 1 ps has been designed in a CMOS technology. In order to limit the number of active and passive components and power consumptions, which are very important for multichannel systems, the fourth-order integrator is realized as a cascade of two second-order integrators. Each of them is designed using only one active gain block as shown in Fig. 8. It can be shown that under the following condition:

=1 ( 2 5 ) grn3(R1+ Rz)', 4(1+ grn',)C,

the transfer function of the circuit in Fig. 8 is given by

Fig. 8. Circuit schematic of a second-order integrator using one OTA.

where g, is the transconductance of the OTA and T~ =

C,/grn3 and T* = ( R I + R2)C,. Equation (26) represents the transfer function of a second-order integrator with the time constant T , = 2 ~ ~ 7 ~ / ( T ~ + 7,). It is important to note that as long as g,R, >> 1, the condition (25) depends only on the ratios of gm's, R's, and C's that can be precisely controlled in an IC process. Also, in this case the gain of integrator is given by A = 1 + R , / R I , and the integrator time constant is T~ = 2 ~ ~ .

It should be noted that although the noise performance of the shaper is much less important compared to that of the CSA, care must be taken to limit the 1/ f noise of the shaper. Because in the frequency range lower than 1/27r~,, the noise of the CSA is attenuated by the differentiator so that the I / f noise of the pulse shaper turns out to be significant.

The total readout front end composed of the CSA of Fig. 5 and pulse shaper designed in this section has been simulated with SPICE. The output pulse and noise spec- tral density are shown in Fig. 9(a) and (b). The simulated value of the peak amplitude is exactly same as the theo- retically calculated one. A slight delay in the peaking time is due to the finite rise time of the step signal at the output of the CSA and parasitic poles within the pulse shaper. In the passband of the shaper, the noise of the input transistor contributes more than 70%. At low frequency the l /f noise of the shaper and the noise of resistances in the differentiator and integrators have significant contributions, while at high frequency the reduction of the contribution of the input transistor is due to the high frequency rolloff of the CSA. The total ENC, due to both the CSA and pulse shaper is about 600 electrons for a 40-pF detector capacitance. This value can only be reduced by increasing the input transistor bias current and the use of large capacitances in the integrators and differentiator.

V. CONCLUSIONS

The maximal capability of a CMOS technology for implementing an integrated semiconductor detector readout system has been analyzed in terms of the detector

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3.50

3.25

3.00

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2.50

2.25

2.00

Vout (t) [VI

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

(a)

10-4 -”

10-5

10-6

10-7

10-8

10-9

10-10 .. freq[Hzl y

1 o5 106 1 o7 (b)

Fig. 9. (a) Transient response of designed CMOS readout system using fourth-order semi-Gaussianxlse shaper with 7, = 1 ps. (b) Total output noise of designed C OS readout system and contribution of input MOSFET.

resolution. The theoretical lowest equivalent noise charge ENC that can be achieved by using a CMOS technology is calculated. Design criteria and techniques of both CSA’s and pulse shapers are analytically derived. For the design of CSAs, it is shown that optimal input transistor dimensions and dc bias conditions exist from the point of view of achieving the best detector resolution. The important effect of l/f noise is studied and it is concluded that l/f noise in a CMOS process sets the lowest limit of the detector resolution, especially for detectors with small capacitances. For instance, for a detector having 40-pF capacitance the best resolution obtainable by using a CMOS technology is about 340 noise electrons.

In contrast to the optimal design of CSA’s, the optimal design of semi-Gaussian pulse shapers depends not only on the noise in MOS transistors, but also on the noise of the detector and its associated bias network. For a given detector it is shown that when a peaking time is given, an optimal order of shaper can be determined. On the other hand, if the order of the shaper is given, the optimal peaking time can be found as well.

To verify the theoretical analyses, a charge sensitive amplifier matching a 40-pF detector capacitance and a fourth-order semi-Gaussian pulse shaper with 1-ps peaking time are designed in a standard 3-bm CMOS technol-

ogy. Calculations and computer simulations show that a detector resolution as low as 600 noise electrons can be obtained, which is the best result among all recently published ones. A further reduction of this value is only possible by increasing the bias currents of the CSA and integrated capacitances in the pulse shaper.

ACKNOWLEDGMENT The authors would like to thank Canberra Semiconduc-

tor N.V, Olen, Belgium for their encouragement and support.

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F. S. Goulding and D. A. Landis, “Signal processing for semiconductor detectors,” IEEE Trans. Nucl. Sci., vol. NS-29, pp. 1125-1 141, Junec:982. F. S. Goulding, Pulse-shaping in low noise nuclear amplifier: A physical approach to noise analysis,” Nuclear Instrum. and Meth-

M. 0. Deighton, “A time-domain method for calculating noise of active integrator used in pulse amplitude spectrometry,” Nuclear Instrum. and Methods, 58, pp. 201-212, 1968. E. Gatti and P. F. Manfredi, Processing the Signal from Solid-State Detectors in Elementary-Particle Physics. SocietP Italiana di Fisica, 1986. W. Sansen, “Integrated low noise amplifiers in CMOS technology,” Nuclear Instrum. and Methods in Phys. Research, A253, pp.

Z. Y. Chang and W. Sansen, “Test structure for evaluation of l / f noise in CMOS technologies,” Proc. ICMTS ’89, pp. 143-146; 1989.

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ods, 100, pp. 493-504, 1972.

427-433, 1987.

m

Willy M. C. Sansen (S’66-M’72-SM’86), for a biography and photo please see page 1084 of the September 1990 issue of this TRANSACTIONS.

m

Zhong Yuan Chang (S’88) received the engi- neering degree in electronics from the Katholieke Universiteit Leuven, Heverlee, Bel- gium in 1985, where he is currently a research assistant working towards the Ph.D. degree.

His research interests are in the design and implementation of low noise analog CMOS and BJT integrated circuits for HiFi, biomedical, and particle detector readout applications.

limits of low noise performance of detector readout front ends in cmos technology

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