ledit layout tool - guceee.guc.edu.eg/courses/electronics/elct706...elct 706 ic design session #1...
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![Page 1: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/1.jpg)
LEDIT Layout Tool
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
![Page 2: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/2.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
1. Create new Layout - File New - Browse:
LEDIT83SamplesTechmosismhp_ns5.tdb
![Page 3: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/3.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
2. Create New Cell
- Menu Bar Cell New
![Page 4: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/4.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
3. Setup Design Technology - Menu Bar Setup Design - Technology Name: SCN3MSUB - 1 Lambda = 0.25u=1/4
![Page 5: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/5.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- Setup Grid Step = 1 Lambda
3. Setup Design Technology
![Page 6: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/6.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
4. LEDIT Hints
Poly
Active
Metal 1
Metal 2
N-well
N-select
P-select
Selection mode
Drawing mode
DRC: Design Rules Check
Netlist Extraction for the layout
Naming Ports
Poly Contact
Active Contact
Merge
![Page 7: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/7.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
5. LEDIT Shortcuts
CTRL + C Copy
CTRL + V Paste
CTRL + X Cut
CTRL + (,, up, down) move
CTRL + A Select all
W Zoom to selection
![Page 8: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/8.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
6. CMOS Inverter Layout
- Develop a suitable layout for a CMOS inverter with 0.25um technology using the following aspect ratios:
(W/L)n=1u/0.5u (W/L)p=2u/0.5u
- For a 0.25um technology
• 1u = 1/0.25= 4 Lambda • 0.5u = 2 Lambda • 2u = 8 Lambda
![Page 9: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/9.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
6.1. Active Layer for PMOS
8λ = Wp = 2µm
Hints: To move any Layer: 1. Select the layer 2. Press ALT + Click in the middle of the layer and move it. To edit the size of any Layer: 1. Select the layer 2. Press ALT + Click on the layer side required to edit.
![Page 10: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/10.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
6.2. PSelect and N-Well Layer for PMOS
Min Active - PSelect = 3λ
Min = 3λ
Min Active - Well = 6λ
Min = 6λ
Hint: Perform a DRC Check after each step
![Page 11: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/11.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
Design Rules Check
Browse to the location where you want the text file to be generated
To write the errors in a text file for easy tracking of errors
![Page 12: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/12.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
6.3. Active and N-Select Layers for NMOS
4λ = Wn = 1µm
Min Active - Well = 6λ
Min Active - NSelect = 3λ
![Page 13: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/13.jpg)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
6.4. Poly Layer for NMOS and PMOS Gates
Min Extension outside Active = 2λ
Min = 3λ
2λ = Ln = Lp = 0.5µm
![Page 14: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/14.jpg)
6.5. Active Contact and Metal Layer for Drain/Source Connections
Active Contact Exact Size: 2λ× 2λ Min metal overlap on
active contact 1λ
Min Active overlap on
active contact 1.5λ
ERORR!!! Distance = 1λ < Min (1.5 λ)
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
![Page 15: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/15.jpg)
6.5. Active Contact and Metal Layer for Drain/Source Connections
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- Add Extra Active Regions - Press shift and select them all - Merge them together by
pressing the Merge Icon
![Page 16: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/16.jpg)
6.6. Poly Contact and Metal Layer for Gate Connections
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
![Page 17: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/17.jpg)
6.7. Add Port Names
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
![Page 18: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/18.jpg)
7. Extract the netlist of the layout
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
Browse to the location where you want the netlist file to be generated
Adjust the path of mhp_ns5.ext
![Page 19: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/19.jpg)
8. Open the Generated Netlist file on PSpice
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
![Page 20: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/20.jpg)
9. Check the generated netlist and Adjust the nodes as required
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
MOS definition on Pspice M1 Drain Gate Source Bulk model_name L= W= N.B. We will Connect the Source and Bulk together
![Page 21: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/21.jpg)
9. Check the generated netlist and Adjust the nodes as required
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
- Change the MOS models to CMOSP and CMOSN models
- Connect the source of the NMOS to GND - Connect the dc VDD and the pulse Vin - Perform a transient simulation
![Page 22: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/22.jpg)
10. Save the Netlist as .cir file then Re-open the .cir file
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
![Page 23: LEDIT Layout Tool - GUCeee.guc.edu.eg/Courses/Electronics/ELCT706...ELCT 706 IC Design Session #1 Dr. Ahmed Madian Eng. Salma Hesham 6.1. Active Layer for PMOS 8λ = W p = 2µm Hints:](https://reader033.vdocuments.mx/reader033/viewer/2022041608/5e360a0b6895da053e18d261/html5/thumbnails/23.jpg)
10. Simulate the netlist to test the inverter functionality
ELCT 706 IC Design Session #1
Dr. Ahmed Madian Eng. Salma Hesham
Vout = V(4)
Vin = V(1)