lecture07 capacitance resistance

8/3/2019 Lecture07 Capacitance Resistance

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Lecture 7 ECE 425

Lecture 7 -- Capacitance and Resistance in

VLSI Structures


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Lecture 7 ECE 425

Outline

Overview of next few lectures

Determining capacitance and resistance of CMOS

structures


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Lecture 7 ECE 425

Upcoming Lectures

Three-lecture sequence on circuit speed

Determining resistances and capacitances

Calculating gate speed

Logical effort -- a method for estimating the speed of

multi-gate structures.


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Lecture 7 ECE 425

Delay Estimation

Computing delay exactly requires knowing L, R, C, anddoing painful calculus

Therefore, we make approximations that are close

enough for design work

Always keep in mind the inaccuracy of fabrication Typically use either capacitance-only or RC delay models

depending on physical distance between structures

Today, were going to focus on how to determine the

capacitance and resistance of VLSI structures

Next time, we talk about how to use that to estimate delay


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Lecture 7 ECE 425

Transistors

Capacitance

Care about three capacitances: source, drain, gate

Resistance

Approximate resistance of gate terminal as infinite

(current only flows into gate to charge/discharge gatecap)

Resistance from source-drain is complex function of

Vds, Vgs and depends on what region the device

operates in

Often approximate as Reff, based on the time

required to charge/discharge a unit capacitance


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Lecture 7 ECE 425

Transistor Capacitance

Source, drain capacitances are between diffusion and bulk

Gate capacitance is sum of Cgs (gate-source

capacitance), Cgd (gate-drain capacitance), Cgb (gate-bulk

capacitance)


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Source and Drain Capacitances

Also called Diffusion capacitance (Cd)


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Source, Drain Capacitance

Caused by the depletion region at the diffusion-substratejunction

Also occurs if you use diffusion as a wire, can use

same methods to calculate.

Exact value depends on the potential across the junctionVj and the area of the depletion region

For simplicity, we conservatively assume Vj = 0, and thus Cd= Cd0


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Lecture 7 ECE 425

Source, Drain Capacitance

Under this model, two components to diffusioncapacitance

Area: Cja * a * b

Perimeter Cjp * (2a + 2b)


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MOSFET Capacitances: Diffusion

Bottom

Side wa

Side wall

Source

Channel-stop

Subst

W

xj

LS

AMI 1.5um Model

+CJ = 2.73 E-4 [F/ m^2] PB = 0.979 MJ = 0.54 CJ max=0.27fF/

+CJSW = 1.42 E-10 [F/ m] PBSW = 0.99 MJSW = 0.1 CJsw max=0.142

CJSWG 6 41E 11 [F/ ] PBSWG 0 99 MJSWG 0 1 CJ 0 06


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Lecture 7 ECE 425

Gate Capacitance is a Bit More Complex

Start with idealized MOS capacitor


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Lecture 7 ECE 425

Ideal MOS Capacitor

In accumulation, gate oxide acts as a parallel-platecapacitor

In depletion, the depletion layer (non-conductive) acts as

a dielectric, creating a second capacitor in series with the

gate oxide

D = depth of depletion layer


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MOS Capacitor in Inversion


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MOS Capacitor in Inversion


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Combined Behavior


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Back to the Transistor


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Transistor

In a transistor, the inversion layer is replentished by thesource/drain, so transistors should always follow the

slow capacitance curve, regardless of switching speed


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Regions of Operation


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Linear Region Continued


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Saturation


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Summary


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Lecture 7 ECE 425

More Summary

Gate capacitance is approximately equal to C0, the gate-oxide capacitance for most regions of operation

Exception is when Vgs is close to Vt


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Lecture 7 ECE 425

Well assume that the circuit switches quickly through thisregion and approximate (conservatively)

Simpler way to express this is

Cox (gate capacitance per unit area) is one of the

parameters of a fab process


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Lecture 7 ECE 425

Example


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MOSFET Capacitances: Over Overlap capacitances are

Cgso and Cgdo

Values are given by unit

width:

WxCC

WxCC

doxGDO

doxGSO

=

=

xd xd

Ld

Polysilicon gate

Top view

Source

n+

doxGDOgdo

doxGSOgso

xCWCC

xCWCC

==

==

/

/

WxCC

WxCC

doxGDO

doxGSO

=

=

SPICE Model TSMC 0.35um

+CGDO = 2.69E-10 CGSO = 2.69E-10 CGBO = 1E-


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Part 2: Wires

Whenever two conducting layers overlap, they create acapacitor

Well approximate this using parallel-plate model for the

most part


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Typical Parameters from CMOSN Process


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Example 1


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Example 1


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Example 2


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Example 2


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Complications


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Resistance


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Example


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Sheet Resistivities


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Non-Rectangular Regions

General approach is to maintain a lookup table ofcommon shapes and their equivalent resistance in

squares

Parameterize by the ratio of important dimensions


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Example Resistances


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Finding Resistances of Wires

1. Break wires up into regions that you know how to find theresistance in squares of

2. Sum resistance in squares along appropriate paths

3. Multiply by sheet resistance

For wires that split, treat each portion as a segment and do

series/parallel combinations to get total resistance


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Example


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Example 2


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Wrapping Up

Reading Section 2.6

Section 4.5

Next time: Gate-level delay estimation

lecture07 capacitance resistance

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