Sam Palermo Analog & Mixed-Signal Center

Texas A&M University

ECEN620: Network Theory Broadband Circuit Design

Fall 2012

Lecture 1: Introduction

Why Broadband Circuits?

• Broadband circuits are used in many wireline and wireless communication systems

• Trends in processor design and the growing demand for digital connectivity are pushing data rates and bandwidth requirements in these systems

• In this class, we will study key clocking, amplifier, and logic circuits that enable these communication systems to scale in performance

2

Class Topics

• Broadband circuit design methodologies

• Clocking circuits • Phase-Locked Loops (PLLs) • Clock-and-Data Recovery systems (CDRs)

• Broadband amplifiers • Transimpedance, limiting, and variable-gain amplifers

• High-Speed Logic • Design techniques for high-speed CMOS and CML logic

3

Analog Circuit Sequence

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326 Pre/Co-Requisite

Administrative

• Instructor: • Sam Palermo • 315E WERC Bldg., 845-4114, spalermo@ece.tamu.edu • Office hours: MW 3:00pm-4:30pm

• Lectures: MWF 10:20am-11:10am, ETB 1003

• Class web page • http://www.ece.tamu.edu/~spalermo/ecen620.html

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Class Material

• Textbook: Class Notes and Technical Papers

• Key References • Phaselock Techniques, F. Gardner, John Wiley & Sons, 2005. • Design of Integrated Circuits for Optical Communications, B.

Razavi, McGraw-Hill, 2003. • Phase-Locked Loops: Design, Simulation, & Applications, R. Best,

McGraw-Hill, 1997. • Broadband Circuits for Optical Fiber Communication, E. Sackinger,

Wiley, 2005. • Design of Analog CMOS Integrated Circuits, B. Razavi, McGraw-

Hill, 2001.

• Class notes • Will hand out hard copies in class

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Grading

• Exams (60%) • Three midterm exams (20% each)

• Homework (20%)

• Collaboration is allowed, but independent simulations and write-ups • Need to setup CADENCE simulation environment • No late homework will be graded

• Final Project (20%)

• Groups of 1-2 students • Report and PowerPoint presentation required

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Prerequisites

• Circuits • ECEN474 or approval of instructor • Basic knowledge of CMOS gates, flops, etc… • Circuit simulation experience (HSPICE, Spectre)

• Systems

• Basic knowledge of s- and z-transforms • MATLAB experience

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Simulation Tools

• Matlab

• Cadence

• 90nm CMOS device models • Can use other technology models if they are a

130nm or more advanced CMOS node

• Other tools, schematic, layout, etc… are optional

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10

Preliminary Schedule

• Dates may change with reasonable notice

Analog IC Design Olympics (Extra Credit)

• Analog IC Design Olympics Contest is on September 15 • http://amsc.tamu.edu/olympics.htm • Register by August 31 at noon

• Open to all TAMU Grad Students

• Teams of 2 will compete in a circuit design contest

• Designs are judged by a distinguished industrial committee • Broadcom, NXP, Qualcomm, Silicon Labs, TSMC, TI, Stone Soup Labs

• Extra Credit Opportunity • 20 points added to a homework score

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High-Speed Electrical Link System

TX

ChannelTX

data

Seria

lizer

PLLref clk

RX

Des

eria

lizer

RXdata

TX clk RX clk

D[n+1]D[n] D[n+2] D[n+3]TX data

TX clk

RX clk

CDR

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PLL Performance TxPLL RxPLL Min freq (GHz) 8.98 8.96 Max freq (GHz) 13.54 13.47 Mean freq (GHz) 11.26 11.22 Lock range (GHz) 4.56 4.52

+/-20.2% +/-20.1% Fine tune hold range 5.8% 5.8%

Quarter rate clock phase noise @ 10MHz offset (dBc/Hz)

-117.8 -117.7

Jitter, 1MHz-100MHz (ps rms) 1.5 1.4 Jitter, fc/1667-100MHz (ps rms) 0.64 0.64

-20

-15

-10

-5

0

5

0.1 1 10

Frequency (MHz)

Ga

in (

dB

) (2MHz,-3dB)

Measured Jitter Transfer Function

10GHz PLL Example

100mW Power consumption (with clock distribution)

[Meghelli (IBM) ISSCC 2006]

High-Speed Logic Example: Divide-by-2 with CML FF

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• High-speed logic blocks are required in numerous high-speed circuits, such as PLLs, CDRs, and equalizers

• Relative to CMOS logic, current-mode logic (CML) circuits can achieve higher bandwidth due to lower self-loading

• Additional bandwidth extension can be achieved with the addition of passives (inductors) and feedback

[Razavi]

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Detailed Serial-Link Receiver Architecture

Key Features: - Half-rate design - 5-tap continuously adaptive DFE - Variable gain amplifier - Digital CDR - ESD protection (HBM & CDM) - 130mW (with DFE and CDR logic)

T-Coil Compensation Network

50Ω

In_P In_N

(10G

b/s)

ESD

VGA

Vcm

PI PI

Phase rotator

2:8 DMUX

8:16 DMUX

CDR logic

I-Clock control

Q-Clock control I Q

DFE logic

Tap weights

C2-I C2-Q

Edge

Data Amp

From on-chip PLL (5GHz)

CML CMOS logic VDDA=1.2V

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2

D0

D1

D2

D3

2

2

2

(2.5

Gb/

s)

1

1

1

1 VDDIO=1V

DFE Block

Phase detector

VDD=1.0V

Data Amp Edge Clock

[Meghelli (IBM) ISSCC 2006]

CDR Loop

Data Z-1

Z-1

DMUX XORs

D

E

D

E

Early

Late

Digital Filter

I Rotator Control

Q Rotator Control

PI D/A

PI D/A C2-I

C2-Q

From

on-

chip

PLL

Data Clock

Edge Clock

Key Features: - Fully digital loop - Can handle up to +/- 4000ppm frequency offset - Independent I,Q control

Jitter Tolerance

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.00E+05 1.00E+06 1.00E+07 1.00E+08 1.00E+09

Modulation Frequency

Sine

Jitt

er (U

I pp)

Receiver Jitter tolerance curve ( BER<1e-9)

Tracking bandwidth ~9MHz

16 [Meghelli (IBM) ISSCC 2006]

Variable-Gain Amplifier (VGA) Example

Key Features: • Dual Diff Amps

• Half/Full Amplitude • Switched R Degen • 7 Bit Thermometer

• Multi-bit Slewrate • Glitchless Operation • Continuous Adjustment • Optimized with GA [Sorna (IBM) ISSCC 2005]

Optical Receiver Front-End

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[Razavi]

• Transimpedance amplifiers (TIAs) convert an input current signal into an output voltage with a transimpedance gain

• Limiting amplifier amplifies the TIA output to a reliable level to achieve a given BER with a certain decision element (comparator)

Next Time

• Linear circuit analysis review

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