Lecture 3. Understanding Transistors: Technology CharacterizationTechnology Characterization

Jaeha KimMixed-Signal IC and System Group (MICS)Mixed Signal IC and System Group (MICS)Seoul National Universityjaeha@ieee.orgj @ g

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Motivations Good circuit design starts with understanding transistors

that you build circuits withthat you build circuits with In a sense, you are asking the following questions:

Wh t I th t i t f (i t t )? What can I use these transistors for (intent; usage)? For each intent, what are the metrics that describe its quality?

Acknowledgements: Prof. Boris Murmann at Stanford Ref: Willy M.C. Sansen, “Analog Design Essentials”, Ch. 1.

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Every Device Has a Purpose When building a circuit, the designer utilize a different

property for each device (it is the “design intent”)property for each device (it is the design intent ) What are the possible ways to use transistors?

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Ways to Utilize MOS Transistors Current source

Resistor

VCCS VCCS

Switch

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MOS as a Resistor

MOS transistor operating in linear region acts as a resistor Linear region: VGS > Vth and VDS < VDS,sat,

According to the long-channel model:

And if VDS << VGS-Vth (=VDS,sat)

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Ron vs. Technology

For constant gate overdrive (Vov = VGS-Vth), the on-resistance per square decreases with technologyresistance per square decreases with technology

But, the maximum available VGS-Vth has been scaling d ( V L f 0 35 d t 90 )down (e.g. VDD Lmin from 0.35um down to 90nm) As a result, the minimum Ron stayed roughly constant Then what about below 65nm? Then what about below 65nm?

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Exercise: Analog Switch on CL

Required Ron < 0.5ns / 4pF = 125-ohms Ron varies VGS-Vth ( avg. of 2.0V and 1.4V) Calculate the minimum W/L required Actual Ron is found higher than predicted – can you guess why?

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Body Effect As bulk voltage (VBS)

drops the increased drops, the increased reverse-bias increases the depletion charge to the depletion charge to be inverted

Vth increases! Vth increases!

The parameter is technology dependent Check out how body effect is scaling with technologyy g gy

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MOS as a VCCS

+gmvgsvgs

-

MOS transistor operating in saturation region can be approximated as a VCCSapproximated as a VCCS

Long-channel model (square-law model) states:

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Closer Look at Gm: IDS vs. VGS

Weak inversion:

Strong inversion:

Velocity saturation:y

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Closer Look at Gm: Gm vs. VGS

Weak inversion:

Strong inversion:

Velocity saturation:y

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Transition Between Weak & Strong Inversion By equating the gm-expressions for weak and strong

inversion regions we can find where the transition occursinversion regions, we can find where the transition occurs

Transition point is: p

It means, to operate transistors in strong-inversion, gate- It means, to operate transistors in strong inversion, gateoverdrive must be at least 70mV

Note this is independent of the channel length L

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MOSFET Small-Signal Model

! !

gdgbgsgg CCCC !

gddbdd CCC !

Note: body effect (gmb) term is not includedNote: body effect (gmb) term is not included

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Output Resistance (ro = 1/gds) Non-zero gds (= dIDS/dVDS) is caused by two main effects

Channel length modulation (CLM) Channel length modulation (CLM) Threshold voltage variation (DIBL) Typically modeled as IDS (1+VDS) or (1+VDS/VEL)yp y DS ( DS) ( DS E )

CLM: the effective channel length decreases as VDS Leff = L - L L= (VD-VDsat)eff ( D Dsat)

DIBL: drain voltage can influence the field at the source of short-channel devices and therefore change Vthof short channel devices and therefore change Vth VTH = VTH0 – VDS

gd is not a good parameter for your designs to rely on gds is not a good parameter for your designs to rely on14

MOS Capacitance Model

C - gate capacitance Cg gate capacitance Cjc – depletion layer C C junction caps Csb, Cdb junction caps Col "overlap capacitance"

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Gate Capacitance vs. VGS

• Note: this picture ignores overlap and fringing components• Note: this picture ignores overlap and fringing components16

Junction Capacitance at Source/Drain Junction capacitances are nonlinear, too

C is a function of junction bias CJ is a function of junction bias1.0

0.8

0.9

bitr

ary

units

]

0.6

0.7

Cap

acita

nce

[arb

N+ junction area

0.4

0.5

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8N d lt (V)

N+ junction perimeterP+ junction areaP+ junction perimeter

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Node voltage (V)

Basic Figures of Merit

• Current efficiencySquare Law

• Current efficiency– Want large gm, for as little

current as possible D

mIg

OVV2

• Transit frequency mg OVV3 – Want large gm, without large Cgg

I t i i i

ggC 2L2

• Intrinsic gain– Want large gm, but no gds

ds

mgg

OVV2

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Device Characterization* gmid.sp* NMOS characterization, L=0.18um

.param gs=0.7

.param dd=1.8vds d 0 dc 'dd/2'vgs g 0 dc 'gs'mn d g 0 0 nch L=0.18um W=5um

.op

.dc gs 0.2V 1V 10mV DD

.probe ov = par('gs-vth(mn)')

.probe gm_id = par('gmo(mn)/i(mn)')* For BSIM4, use cggbm in the following line.probe ft = par('1/6.28*gmo(mn)/cggbo(mn)')

b d (' ( )/ d ( )').probe gm_gds = par('gmo(mn)/gdso(mn)')

.options post brief dccap

.inc cmos018.spend.end

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gm/ID Plot

40

30

35 0.18um NMOS2/VOVBJT (q/kT)

20

25

m/I D

[S/A

]

5

10

15g m

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

5

V [V]

VOV [V]

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Transit Frequency Plot

50

0.18um NMOS

40

0.18um NMOSSquare Law Model

20

30

f T [GH

z]

mgf 1

10

20f

ggT C

f2

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

V [V]

VOV [V]

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Intrinsic Gain Plot80

0.18um NMOS

60

70 Long Channel Model, =0.3

30

40

50

g m/g

ds

Short Channel Device

10

20

30

-0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

10

V [V]

VOV [V]

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Assignment – Technology Characterization Plot the Id-Vds curves for W/L=20/2 nMOS & pMOS

Characterize Ron (from linear region) for each VGS Characterize Ron (from linear region) for each VGS Characterize gm (from saturation region) for each VGS

Plot Id-Vgs curves for Vds=Vdd/2 Plot Id-Vgs curves for Vds=Vdd/2 Also plot as gm and gds as function Vgs

Characterize the capacitance components Characterize the capacitance components The components listed in slide 13 vs. Vds or Vgs

Measure second order effects such as: Measure second-order effects such as: Body effect: Vth vs. VBS Short-channel effect: Vth vs. L Narrow-channel effect: Vth vs. W

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Assignment – cont’d Plot the following parameters for a reasonable range of

g /ID and channel lengths for various technologiesgm/ID and channel lengths for various technologies Transit frequency (fT) Intrinsic gain (gm/gds) Current density (ID/W)

In addition, tabulate relative estimates of extrinsic capacitances Cgd/Cgg and Cdd/Cgg

Tip: try to automate the procedure as much as you can Using mulan/simba script

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Transit Frequency PlotNMOS, 0.18...0.5um (step=20nm), VDS=0.9V

20

25

L=0 18um

15

20

T [GH

z]

L=0.18um

5

10

f T

5 10 15 20

5

g /I [S/A]

L=0.5um

gm/ID [S/A]

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Sweet SpotNMOS, 0.18...0.5um, step=20nm

L=0 18um200

S/A

]

L=0.18um

• gm/ID ~ 10..12 S/A can be a good

150

*fT [G

Hz*

S can be a good choice for designs

in which power d d

50

100

g m/I D

* and speed are equally important

5 10 15 20

50

g /I [S/A]gm/ID [S/A]

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Intrinsic Gain PlotNMOS, 0.18...0.5um (step=20nm), VDS=0.9V

L 0 5

90

100 L=0.5um

70

80

g m/g

ds

40

50

60g

5 10 15 2030

40

g /I [S/A]

L=0.18um

gm/ID [S/A]

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Current Density Plot (Sizing Chart)NMOS, 0.18...0.5um (step=20nm), VDS=0.9V

101

W [A

/m] L=0.18um

I D/W

L=0.5um

5 10 15 20/I [S/A]gm/ID [S/A]

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VDS Dependence102

NMOS, L=0.18um

VDS=0.9V • V dependence DSVDS=0.4V

VDS=1.4V

• VDS dependence is relatively weak

D/W

[A/m

]

• Typically OK to work with plots

t d f 101I D generated for VDD/2

5 10 15 20g /I [S/A]

gm/ID [S/A]

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Extrinsic Capacitances (1)

1NMOS, L=0.18um

Cdd/C

Again, usually 0.8

Cdd/CggCgd/Cgg0.70

OK to work with estimates taken at V /20 4

0.6

taken at VDD/2

0.2

0.40.24

0 0.5 1 1.50

V [V]

VDS [V]

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Extrinsic Capacitances (2)

0.8NMOS, gm/ID=10S/A, VDS=0.9V

C /C

0.6

0.7Cgd/CggCdd/Cgg

0.4

0.5

0.2

0.3

0.2 0.25 0.3 0.35 0.4 0.45 0.50

0.1

L [m]31

Gate Leakage Current

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