lecture #28 - university of california, berkeleyee130/sp03/lecture/lecture28.pdf · spring 2003...
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EE130 Lecture 28, Slide 1Spring 2003
Lecture #28
ANNOUNCEMENTS• Quiz #6 next Thursday (May 8)
– Topics covered: MOSFET– Closed book; calculator, 6 pages of notes allowed
OUTLINE– MOSFET scaling– CMOS technology– Silicon on Insulator technology
Reading: Reader Part III, Chapter 4
EE130 Lecture 28, Slide 2Spring 2003
Short-Channel MOSFET VT• For short-channel MOSFETs, VT is usually defined as
the gate voltage at which the maximum barrier for electrons at the surface equals 2ψB. This is lower than the long-channel VT by an amount
Note: This equation assumes that rj > Wdm
To minimize VT roll-off, Nbody should be high enough to ensure that Lmin > 2Wdm
BG
bi
TWLDSbibi
dm
oxeT
qE
eVW
TV oxedm
ψψ
ψψ π
+=
+=∆ +−
2 where
)(24 )3(2/
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EE130 Lecture 28, Slide 3Spring 2003
Constant-Field Scaling• Voltages and MOSFET dimensions are scaled by the
same factor κ>1, so that the electric field remains unchanged
EE130 Lecture 28, Slide 4Spring 2003
Constant-Field Scaling (cont.)
• Circuit speed improves by κ
• Power dissipation per functionis reduced by κ2
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EE130 Lecture 28, Slide 5Spring 2003
VT Design Trade-Off
• Low VT is desirable for high ON current:Idsat ∝ (Vdd - Vt)η 1 < η < 1.5
• But VT is needed for low OFF current:
Low VT
High VT
IOFF,high VT
IOFF,low VT
VGS
log IDS
0
• Non-scaling factors:• kT/q• EG• Tinv
VT cannot be scaled aggressively!
EE130 Lecture 28, Slide 6Spring 2003
• Since VT cannot be scaled down aggressively, the power-supply voltage (VDD) has not been scaled down in proportion to the MOSFET channel length
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EE130 Lecture 28, Slide 7Spring 2003
Generalized Scaling• Electric field intensity increases by a factor α>1• Nbody must be scaled up by α to control short-channel effects
• Reliability andpower density are issues
EE130 Lecture 28, Slide 8Spring 2003
CMOS TechnologyBoth n-channel and p-channel MOSFETs arefabricated on the same chip (VTp = -VTn )
• Primary advantage:– Lower average power dissipation
• In steady state, either the NMOS or PMOS device is off, so there is no d.c. current path between VDD and GND
• Disadvantages:– More complex (expensive) process – Latch-up problem
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EE130 Lecture 28, Slide 9Spring 2003
p-substrate
NDn-well
NDn-well
NAp-well
Single-well technology• n-well must be deep enough
to avoid vertical punch-through
Need p-regions (for NMOS) and n-regions (for PMOS)on the wafer surface, e.g.:
NA
Twin-well technology• Wells must be deep enough
to avoid vertical punch-through p- or n-substrate(lightly doped)
EE130 Lecture 28, Slide 10Spring 2003
CMOS Latch-up
n+ p+ p+ n+ n+ p+
n-well p-Si
CMOS Inverter: Vin
Vout
VDD
Vin Vout
VDD
Equivalent circuit:
VSS
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EE130 Lecture 28, Slide 11Spring 2003
Coupled parasitic npn and pnp bipolar transistors:
If either BJT enters the active mode, the SCR will enter into the forward conducting mode (large current flowing between VDD and GND) if βnpnβpnp > 1
=> circuit burnout!Latch-up is triggered by a transient increase in current, caused by• transient currents (ionizing radiation, impact ionization, etc.)• voltage transients
• e.g. negative voltage spikes which forward-bias the pn junction momentarily
EE130 Lecture 28, Slide 12Spring 2003
How to Prevent CMOS Latchup
(a) n-well p-epip+-substrate
Rsub
npn
nn+ p-sub
Rwell
pnp
“retrograde well”
(b)
β
β
1. Reduce minority-carrier lifetimes in well/substrate2. Use highly doped substrate or wells:
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EE130 Lecture 28, Slide 13Spring 2003
Modern CMOS Fabrication Process
• A series of lithography, etch, and fill steps are used to create silicon islands isolated by oxide
• Lithography and implant steps are used to set NMOS and PMOS doping levels
p-type Silicon Substrate
p-type Silicon Substrate
Shallow Trench Isolation (STI) - oxide
p-type Silicon Substrate
EE130 Lecture 28, Slide 14Spring 2003
• A thin gate oxide is grown
• Poly-Si is deposited and patterned to form gate electrodes
• Lithography and implantation is used to form NLDD and PLDD regions
p-type Silicon Substrate
p-type Silicon Substrate
p-type Silicon Substrate
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EE130 Lecture 28, Slide 15Spring 2003
• A series of steps is used to form the deep source / drain regions as well as body contacts
• A series of steps is used to encapsulate the devices and form metal interconnections between them.
p-type Silicon Substrate
p-type Silicon Substrate
EE130 Lecture 28, Slide 16Spring 2003
Intel’s 90 nm CMOS Technology
To be used for volume manufacturing of ICson 300 mm wafers beginning this year
• Lgate = 50 nm
• Tox = 1.2 nm
• Strained Si channel
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EE130 Lecture 28, Slide 17Spring 2003
Strained Si
IDsat can be increased by enhancing field-effect mobilities, by straining the Si channel:
invDsat QvI ×∝
Courtesy of J. Hoyt, MIT
EE130 Lecture 28, Slide 18Spring 2003
Mobility Enhancement with Strain
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EE130 Lecture 28, Slide 19Spring 2003
14 nm CMOSFETsHokazono et al., Toshiba Corporation, presented at the International Electron Devices Meeting (San Francisco, CA) Dec. ‘02
• 1.3 nm SiOxNy gate dielectric
• Poly-Si0.9Ge0.1 gate
EE130 Lecture 28, Slide 20Spring 2003
Silicon on Insulator (SOI) Technology• Advantages over bulk-Si:
– very low junction capacitance– no body effect– soft-error immunity