lecture 20: package, power, and i/opages.hmc.edu/harris/class/e158/04/lect20.pdf · 20: package,...
TRANSCRIPT
Introduction toCMOS VLSI
Design
Lecture 20: Package, Power, and I/O
David Harris
Harvey Mudd CollegeSpring 2004
20: Package, Power, and I/O Slide 2CMOS VLSI Design
Outlineq Packagingq Power Distributionq I/Oq Synchronization
20: Package, Power, and I/O Slide 3CMOS VLSI Design
Packagesq Package functions
– Electrical connection of signals and power from chip to board
– Little delay or distortion– Mechanical connection of chip to board– Removes heat produced on chip– Protects chip from mechanical damage– Compatible with thermal expansion– Inexpensive to manufacture and test
20: Package, Power, and I/O Slide 4CMOS VLSI Design
Package Typesq Through-hole vs. surface mount
20: Package, Power, and I/O Slide 5CMOS VLSI Design
Multichip Modulesq Pentium Pro MCM
– Fast connection of CPU to cache– Expensive, requires known good dice
20: Package, Power, and I/O Slide 6CMOS VLSI Design
Chip-to-Package Bondingq Traditionally, chip is surrounded by pad frame
– Metal pads on 100 – 200 µm pitch– Gold bond wires attach pads to package– Lead frame distributes signals in package– Metal heat spreader helps with cooling
20: Package, Power, and I/O Slide 7CMOS VLSI Design
Advanced Packagesq Bond wires contribute parasitic inductanceq Fancy packages have many signal, power layers
– Like tiny printed circuit boardsq Flip-chip places connections across surface of die
rather than around periphery– Top level metal pads covered with solder balls– Chip flips upside down– Carefully aligned to package (done blind!)– Heated to melt balls– Also called C4 (Controlled Collapse Chip Connection)
20: Package, Power, and I/O Slide 8CMOS VLSI Design
Package Parasitics
Chip
Signal P
ins
PackageCapacitor
Signal P
ads
ChipVDD
ChipGND
BoardVDD
BoardGND
Bond Wire Lead Frame
Package
q Use many VDD, GND in parallel– Inductance, IDD
20: Package, Power, and I/O Slide 9CMOS VLSI Design
Heat Dissipationq 60 W light bulb has surface area of 120 cm2
q Itanium 2 die dissipates 130 W over 4 cm2
– Chips have enormous power densities– Cooling is a serious challenge
q Package spreads heat to larger surface area– Heat sinks may increase surface area further– Fans increase airflow rate over surface area– Liquid cooling used in extreme cases ($$$)
20: Package, Power, and I/O Slide 10CMOS VLSI Design
Thermal Resistanceq ∆T = θjaP
– ∆T: temperature rise on chip– θja: thermal resistance of chip junction to ambient– P: power dissipation on chip
q Thermal resistances combine like resistors– Series and parallel
q θja = θjp + θpa
– Series combination
20: Package, Power, and I/O Slide 11CMOS VLSI Design
Exampleq Your chip has a heat sink with a thermal resistance
to the package of 4.0° C/W. q The resistance from chip to package is 1° C/W.q The system box ambient temperature may reach
55° C.q The chip temperature must not exceed 100° C.q What is the maximum chip power dissipation?
20: Package, Power, and I/O Slide 12CMOS VLSI Design
Exampleq Your chip has a heat sink with a thermal resistance
to the package of 4.0° C/W. q The resistance from chip to package is 1° C/W.q The system box ambient temperature may reach
55° C.q The chip temperature must not exceed 100° C.q What is the maximum chip power dissipation?
q (100-55 C) / (4 + 1 C/W) = 9 W
20: Package, Power, and I/O Slide 13CMOS VLSI Design
Power Distributionq Power Distribution Network functions
– Carry current from pads to transistors on chip– Maintain stable voltage with low noise– Provide average and peak power demands– Provide current return paths for signals– Avoid electromigration & self-heating wearout– Consume little chip area and wire– Easy to lay out
20: Package, Power, and I/O Slide 14CMOS VLSI Design
Power Requirementsq VDD = VDDnominal – Vdroop
q Want Vdroop < +/- 10% of VDD
q Sources of Vdroop
– IR drops– L di/dt noise
q IDD changes on many time scales
clock gating
Time
Average
Max
Min
Power
20: Package, Power, and I/O Slide 15CMOS VLSI Design
Power System Modelq Power comes from regulator on system board
– Board and package add parasitic R and L– Bypass capacitors help stabilize supply voltage– But capacitors also have parasitic R and L
q Simulate system for time and frequency responses
VoltageRegulator
Printed CircuitBoard Planes
Packageand Pins
SolderBumps
BulkCapacitor
CeramicCapacitor
PackageCapacitor
On-ChipCapacitor
On-ChipCurrent Demand
VDD
Chip
PackageBoard
20: Package, Power, and I/O Slide 16CMOS VLSI Design
Bypass Capacitorsq Need low supply impedance at all frequenciesq Ideal capacitors have impedance decreasing with ωq Real capacitors have parasitic R and L
– Leads to resonant frequency of capacitor
104
105
106
107
108
109
1010
10-2
10-1
100
101
102
frequency (Hz)
impedance
1 µF
0.03 Ω
0.25 nH
20: Package, Power, and I/O Slide 17CMOS VLSI Design
Frequency Responseq Use multiple capacitors in parallel
– Large capacitor near regulator has low impedance at low frequencies
– But also has a low self-resonant frequency– Small capacitors near chip and on chip have low
impedance at high frequenciesq Choose caps to get low impedance at all frequencies
frequency (Hz)
impedance
20: Package, Power, and I/O Slide 18CMOS VLSI Design
Input / Outputq Input/Output System functions
– Communicate between chip and external world– Drive large capacitance off chip– Operate at compatible voltage levels– Provide adequate bandwidth– Limit slew rates to control di/dt noise– Protect chip against electrostatic discharge– Use small number of pins (low cost)
20: Package, Power, and I/O Slide 19CMOS VLSI Design
I/O Pad Designq Pad types
– VDD / GND– Output– Input– Bidirectional– Analog
20: Package, Power, and I/O Slide 20CMOS VLSI Design
Output Padsq Drive large off-chip loads (2 – 50 pF)
– With suitable rise/fall times– Requires chain of successively larger buffers
q Guard rings to protect against latchup– Noise below GND injects charge into substrate– Large nMOS output transistor– p+ inner guard ring– n+ outer guard ring
• In n-well
20: Package, Power, and I/O Slide 21CMOS VLSI Design
Input Padsq Level conversion
– Higher or lower off-chip V– May need thick oxide gates
q Noise filtering– Schmitt trigger– Hysteresis changes VIH, VIL
q Protection against electrostatic discharge
AY
VDDH
VDDLA Y
VDDL
A Y
weak
weak
A
Y
20: Package, Power, and I/O Slide 22CMOS VLSI Design
ESD Protectionq Static electricity builds up on your body
– Shock delivered to a chip can fry thin gates– Must dissipate this energy in protection circuits
before it reaches the gatesq ESD protection circuits
– Current limiting resistor– Diode clamps
q ESD testing– Human body model– Views human as charged capacitor
PADR
Diodeclamps
Thingate
oxides
Currentlimitingresistor
DeviceUnderTest
1500 Ω
100 pF
20: Package, Power, and I/O Slide 23CMOS VLSI Design
Bidirectional Padsq Combine input and output padq Need tristate driver on output
– Use enable signal to set direction– Optimized tristate avoids huge series transistors
PAD
Din
Dout
En
Dout
En Y
Dout
NAND
NOR
20: Package, Power, and I/O Slide 24CMOS VLSI Design
Analog Padsq Pass analog voltages directly in or out of chip
– No buffering– Protection circuits must not distort voltages
20: Package, Power, and I/O Slide 25CMOS VLSI Design
MOSIS I/O Padq 1.6 µm two-metal process
– Protection resistors– Protection diodes– Guard rings– Field oxide clamps
Out
En
Out
PAD
In
264 Ω 185 Ω
In_bIn_unbuffered
600/3
240
160
90
4020
48