lecture 2-a - İzmir yüksek teknoloji...

CENG 314Embedded Computer Systems

Lecture 2-A

Review of Digital Logic and Computer Architecture Concepts

Asst. Prof. Tolga Ayav, Ph.D.

Department of Computer Engineeringİzmir Institute of Technology

1

Layers of a Computer System

High Level Sum := Sum + 1

Assembly MOV BX,SUM INC (BX)

Machine 1101010100001100 0010001101110101 1111100011001101

Register Transfer Fetch Instruction, Increment PC, Load ALU with SUM ...

Gate

Circuit

İzmir Institute of Technology Embedded Systems Lab.

General Structure of a Microprocessor

Von-Neumann model of acomputer


Binary, Octal, Hexadecimal numbers

Study conversions and aritmetic operations with binary and hexadecimal numbers!


Analogy between binary system and switches

Opened or Off. Closed or On.

A siren controlled by a switch

Binary signals are suitable for on-off control :


Logic Expressions

F = x AND y F = x OR y

AND OR NOT

The operation of the AND, OR, and NOT logic operators can be formally described by using a truth tables:


Boolean AlgebraGeorge Boole, in 1854, developed a system of mathematical logic, which we now

call Boolean algebra. Based on Boole’s idea, Claude Shannon, in 1938, showed that circuits built with binary switches can easily be described using Boolean algebra.


ExampleUse Boolean algebra to reduce the equation F(x,y,z) = (x' + y' + x'y' + xy) (x' + yz) as much as possible.

F = (x' + y' + x'y' + xy) (x' + yz) = (x' • 1 + y' • 1 + x'y' + xy) (x' + yz) by Identity Theorem 6a= (x' (y + y' ) + y' (x + x' ) + x'y' + xy) (x' + yz) by Inverse Theorem 9b= (x'y + x'y' + y'x + y'x' + x'y' + xy) (x' + yz) by Distributive Theorem 12a= (x'y + x'y' + y'x + y'x' + x'y' + xy) (x' + yz) by Idempotent Theorem 7b= (x' (y + y') + x (y + y')) (x' + yz) by Distributive Theorem 12a= (x' • 1 + x • 1) (x' + yz) by Inverse Theorem 9b= (x' + x) (x' + yz) by Identity Theorem 6a= 1 (x' + yz) by Inverse Theorem 9b= (x' + yz) by Identity Theorem 6a

Simplification is important because in the latter expression we need much fewer gates than the former one to implement the circuit.


Logic Gates and Circuit Diagrams

Logic symbols for the three basic logic gates: (a) 2-input AND; (b) 2-input OR; (c) NOT. Logic symbols for: (a) 3-input AND; (b) 4-input AND; (c) 3-input

OR; (d) 4-input OR; (e) 2-input NAND; (f) 2-input NOR; (g) 3-input NAND; (h) 3-input NOR; (i) 2-input XOR; (j) 2-input XNOR.

TruthTables


NOT implementation with transistor


Synthesizing Combinational CircuitsSynthesize a combinational circuit from the following truth table. a, b, c are input signals and x, y are output signals.

x = a'b'c' + a'bc' + a'bc + ab'c + abc'

y = a'bc' + ab'c' + ab'c=>


Simplification with Karnaugh Maps

Use the K-map method to minimize a 5-variable function :

F (v, w, x, y, z) = v'w'x'yz' + v'w'x'yz + v'w'xy'z + v'w'xyz + vw'x'yz' + vw'x'yz + vw'xyz' + vw'xyz + vwx'y'z + vwx'yz + vwxy'z + vwxyz.

F = v'w'xz + w'x'y + vw'y + vwz=>


Timing Hazards

2-to-1 multiplexer circuit

Timing trace

K-map

Using glitches to our advantages:

One-shot circuit: Generates a single pulse


Standard Combinational Components


Full Adder


Subtractor


Adder-Subtractor Combination


Decoder

(a) 3x8 Decoder truth table (b) Circuit (c) Logic symbol


Encoder

(a) 8x3 Encoder truth table (b) Circuit (c) Logic symbol


Multiplexer

2x1 multiplexer

8x1 multiplexer


Shifter, Rotator (1)


Shifter, Rotator (2)

4-bit shifter


Latches and Flip-Flops


S-R Latch

Switch bouncing problem

Solution with S-R Latch


D Latch

D Latch

D Latch with enable


ClockLatches are known as level-sensitive because their outputs are affected by their

inputs as long as they are enabled. Their memory state can change during this entire time when the enable signal is asserted. In a computer circuit, however, we do not want the memory state to change at various times when the enable signal is asserted.Instead, we like to synchronize all of the state changes to happen at precisely the same moment and at regular intervals.

Clock division with counter


D Flip-Flop


J-K Flip-Flop


T Flip-Flop


Sequential Circuits


FSM Models

Moore FSM

Mealy FSM


Example: Synthesizing a FSM circuit

Repeat {

Y := 0; -- s0

if (B = 0)

Y := 0; -- s1

else

Y := 1; -- s2

Y := 1; -- s3

}

Synthesis a FSM based on the C-like pseudo code given below:


1. State diagram

6. Circuit

2. Next state table

3. Implementation table

5. Output table

4. Equations

Solution:


Example: Basic Traffic Light Controller

Traffic light controller controls a traffic light at the intersection of a busy highway and a farm road. Normally, the highway light is green but if a sensor detects a car on the farm cars road, the highway light turns yellow then red. The farm road light then turns green until there are no cars or after a long timeout. Then, the farm road light turns yellow then red, and the highway light returns to green. The inputs to the machine are the car sensor, a short timeout signal, and a long timeout signal. The outputs are a timer start signal and the colors of the highway and farm road lights.

Please design a FSM circuit.

Input signals: S (short timeout), L (long timeout), C (car exists) Output signals: T(start timer), Red, Yellow, Green signals for HW and FR.


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