lecture 1lecture 1-- introductionintroduction · rtl hardware design using vhdl: coding for...

Lecture 1Lecture 1-- IntroductionIntroductionErnoErno SalminenSalminenTKTTKT 12121212 DigitaalijärjestelmienDigitaalijärjestelmien toteutustoteutusTKTTKT--1212 1212 DigitaalijärjestelmienDigitaalijärjestelmien toteutustoteutusTampere University of Technology Tampere University of Technology 20102010--2011201120102010 20112011

Department of Computer Systems

Lecture contentsLecture contents1. Course organization2. Introduction to implementing digital2. Introduction to implementing digital

systems

#2/43 Department of Computer SystemsSpring 2010 - Erno Salminen

Course GoalsCourse GoalsGet to know practical digital system designAware of challenges of digital system designDesign for efficiencyDesign for large scale Large module, large system, overall

development processDesign for portabilityDesign for portability Device independency, software dependency,

design reuse


CourseCourse DescriptionDescription Web: http://www.tkt.cs.tut.fi/kurssit/1212/

Note: This course is as POP-free as possible Lectures, Lectures,

Period 3 Tuesday 10-12 TB223 Wednesday 12-14 TC427 (three times in January! )

Period 4 Tuesday 10-12, TB222

Exercises Arto Perttula, Jussi Raasakka, Erno Salminen Periods 3-4

Tue 12-14, Tue 14-16 Wed 10 12 Wed 10-12 Thu 14-16 Fri 10-12


Course Description (2)Course Description (2) Course requirements:

Regular exam or two midterm examsS f l i / i k Succesful exercises/exercise work

Course primarily based on book:Course primarily based on book: RTL Hardware Design Using VHDL: Coding for

Efficiency, Portability, and Scalability. Chu, Pong P. (2006)(2006) Can be borrowed from the lecturer Available at TUT library

Snippets from other sources also Snippets from other sources also Available from the lecturer

Lectures and lecture notes should be enough for i th


passing the course

Course contentsCourse contents

I. VHDL language Very High Speed Integrated Circuit Hardware y g g

Description language = VHSIC HDL = VHDL Familiarize with the language constructs

II. Testbenches and simulators, synthesis, guidelines for re-use

III FPGA i it d i i f thIII. FPGA circuits, designing for themIV. Advanced topics: Multiple clock domains, clock

synchronization system design challengessynchronization, system design challenges


PreliminaryPreliminary scheduleschedule# Päivä Aika Sali Aihe# Päivä Aika Sali Aihe

1 4.1.2010 Ti 10-12 TB223 Kurssin järjestelyt, johdanto

2 11.1.2010 Ti 10-12 TB223 Johdanto, VHDL-perusteet #1, mm. entitiy ja arkkitehtuuri

3 12.1.2010 Ke 12-14 TC427 VHDL-perusteet #2 - prosessit, signaalit, tyypit

4 18 1 2010 Ti 10 12 TB223 VHDL per steet #3 paketit kirjastot operaattorit atrib tit

I.4 18.1.2010 Ti 10-12 TB223 VHDL-perusteet #3 - paketit, kirjastot, operaattorit, atribuutit

5 19.1.2010 Ke 12-14 TC427 VHDL combinational and sequential part design, generics, statements

6 25.1.2010 Ti 10-12 TB223 RTL-synteesi, tilakoneen toteuttaminen

7 26.1.2010 Ti 10-12 TC427 HDL-testipenkit

8 1 2 2010 Ti 10 12 TB223 HDL i l t itII 8 1.2.2010 Ti 10-12 TB223 HDL-simulatorit

9 8.2.2010 Ti 10-12 TB223 Uudelleenkäyttö, VHDL coding guidelines

- 23.2.2010 Ti 10-12 TB223 Välikoe luentojen 1-8 aiheista , ei tarvitse eikä voi ilmoittautua

10 2.3.2010 Ti 10-12 TB223 FPGA-piirit yleensä

II.

viikko 9 Tenttiviikko

11 8.3.2010 Ti 10-12 TB222 Tosielämän FPGA: Altera Stratix III, case study SDRAM, 1. välikokeenkäsittely

12 15.3.2010 Ti 10-12 TB222 Sekalaisia huomioita

13 22 3 2010 Ti 10-12 TB222 Kellotus ja synkronointi Vierailuluento (aika vielä varmistamatta)

III.

13 22.3.2010 Ti 10-12 TB222 Kellotus ja synkronointi. Vierailuluento (aika vielä varmistamatta)

14 29.3.2010 Ti 10-12 TB222 Kellotus ja synkronointi.

15 5.4.2010 Ti 10-12 TB222 IP-lohkot

(x) 12.4.2010 Ti 10-12 TB222 (varalla)

16 19 4 2010 Ti 10 12 TB222 Järjestelmäsuunnittelun haasteita Kertaus

IV.


16 19.4.2010 Ti 10-12 TB222 Järjestelmäsuunnittelun haasteita, Kertaus

- 26.4.2010 Pääsiäisloma

(x) 12.4.2010 Ti 10-12 TB222 (varalla)

Exercise workExercise workSimple audio synthesizer implemented on

FPGA development boardp Each of the four buttons produces different tone Sound is heard from the external speakers


DE2 development boardBlock diagram of the synthesizer

During the exercises, you’ll learnDuring the exercises, you’ll learn1. to describe, synthesize, and verify digital

systems using VHDLy g De facto standard in European microelectronic

industry2. to read data sheets3. to use I2C bus developed by Philips. Serial bus used e.g. in car industry

4. to operate Wolfson audio codec chip also used in some iPods


Exercises in practiceExercises in practice The first exercise on week 1, 4-7.01.2010

Presence is mandatory on the 1st or 2nd week More information available at the first exercise More information available at the first exercise

Weekly exercises in TC417 (Linux class) Done alone or in groups of two Five guidance sessions per week Five guidance sessions per week

Presence is not required Return is mandatory, email to [email protected]

Each exercise is returned within two weeks (due Sunday ( y23:59)

Possibility to gain 6 bonus points to the passed exam

You must report (avg) hours per person for eachexercise


Reserve enough timeReserve enough timeExercises take 3-4h/week on average but verification is harder than you thinky large variations between groups

Start early!y

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Getting the development boards and Getting the development boards and softwaressoftwaresStudents may borrow an FPGA kit

to do exercises and own hobby j tprojects.

You may keep the kit if you write a BSc/MSc thesis for Department ofBSc/MSc thesis for Department of Computer Systems.

Next pickups Tue 11.1 at 10-11 and Th 13 1 13 14 f th TH305Thu 13.1 13-14 from the room TH305

http://www.tkt.cs.tut.fi/Opetus/Fpga_board

Students may install the neededStudents may install the needed EDA tools to their own computer http://www.tkt.cs.tut.fi/tools/public/tutorials/me

ntor/licensing/licensing html


ntor/licensing/licensing.html

Action pointsAction points1. Apply for a Birdland account if you do not

have one (http://www.cs.tut.fi/lintula/)2. Fill and sign Access application and

confidentiality agreementR t th f t t b 545 (Ti Return the form to post box 545 (Timo Rintakoski)

3. Register to one of the exercise groups3. Register to one of the exercise groups

4. Optional: You may install the needed SW4. Optional: You may install the needed SW tools to your home computer

5. Optional: You may borrow an Altera DE2


yFPGA board

DI-tutkinto 30 opEsitiedot/Koulutusohjelma-

Kandidaatin tutkinto 25 op

Yksinkertaistetut kurssien esitiedot 11/12, laatinut ESYksinkertaistetut kurssien esitiedot 11/12, laatinut ES

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TKT-1212 DigJärjTot8 op (k3)

TKT-2431 SoC-Suunn

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TKT-1400 ASIC I

TKT-3541 Soc-Alustat

5 op (k3)

TKT-1506ASIC II

TKT-1101 DigTeknPer.

4 op (s1)

TKT-1202 DigSuunn5 op (s1)

TKT-1220 Aritmetiikka

4 op (k3)

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TKT-1410 SuunnVarm

5 op (s3)

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TKT-3200 Ti t k t k I

TKT-1110 Mik

TKT-1230 Laboratorio

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TKT-3526P D i

TKT-2526Project work

5-8 op

TKT-9626/9636Seminar

3-6 opTKT-3400Ti t k t k IITietokonetekn. I

5 op (s1)Mikroprosess.

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Esitietoksi käy TKT-1202 tai TKT-1212

#14/43 Department of Computer Systems

TKT-9617ScientificPubl

6 op (s1)

suositeltavaTarkista eksaktit esitietovaatimukset opinto-oppaasta. TKT-2556

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1. Introduction1. Introduction


AcknowledgementsAcknowledgementsProf. Pong . P. Chu provided ”official” slides

for the book which is gratefully aknowledgedg y g See also: http://academic.csuohio.edu/chu_p/

Most slides were made by Ari Kulmalay and other previous lecturers (Teemu Pitkänen,

Konsta Punkka, Mikko Alho…)

#16/43 Department of Computer SystemsSpring 2010 - Erno Salminen TKT-1212 Dig.järj.tot., syksy 2008, A. Kulmala, TTY

Digital CircuitsDigital Circuits Nowadays found everywhere - From washing machines to

space shuttles Digital circuits are typically integrated circuits (IC)Digital circuits are typically integrated circuits (IC)

Minimize the number of discrete components Typical digital systems, such as cellular phones, contain

(Several) Processors and co processors (Several) Processors and co-processors Application-specific hardware An on-chip interconnection between the components Memory

RAM, FLASH, even hard disks

RF/Analog IC RF/Analog IC Out of the scope of this

course


How to implement a digital systemHow to implement a digital system No two applications are identical and every one

needs certain amount of customization B i th d f t i ti Basic methods for customization1. “General-purpose hardware” with custom software

General purpose processor (GPP): e.g., performance-p p p ( ) g , poriented processor (e.g., Pentium), cost-oriented processor (e.g., PIC micro-controller)

Special purpose processor: architecture with a specific set of functions: e.g., DSP processor (to do multiply-add), network processor (to do buffering and routing), “graphics engine” (to do 3D rendering)

C t ft t l tf (CPU th2. Custom software on a custom platform (CPU+other hardware) (known as hardware-software co-design)

3. Custom hardware (no software)


3. Custom hardware (no software)

How to implement a digital system (2)How to implement a digital system (2)

Trade-off between flexibility, programmability, design effort, cost, p g y gperformance, and power consumptionA complex application contains many p pp y

different tasks and use more than one customization methods


1a. Device Technologies1a. Device Technologies


Fabrication of an IC Fabrication of an IC Transistors and connections are made from many layers

(typical 10 to 15 in CMOS) built on top of one another Ever increasing number of layers (more layers, more cost,Ever increasing number of layers (more layers, more cost,

though) Each layer has a special pattern defined by a mask One important aspect of an IC is the length of a smallest One important aspect of an IC is the length of a smallest

feature that can be fabricated Feature may stands for channel legnth of the transistor or

the width of a wire (or something completerly different…)( g p y ) Unit is micrometer (m, 10-6 meter), or nanometer, 10-9m E.g., we may say an IC is built with 0.50 m process The process continues to improve (Moore’s law) The process continues to improve (Moore s law) The state-of-art process are currently moving to 0.28nm

(known as deep sub-micron area)


Fabrication of an IC (2) Fabrication of an IC (2) 1. Silicon wafer is coated with

photoresist2. Light shines through the mask3. Photoresist not hit by light is

wahed awaywahed away4. New layers (n-well, dielectric,

copper wire, via etc.) arecopper wire, via etc.) are created on top of the silicon

5. Finally, the rectangular dies (chips) are sawed from the wafer and packaged


What does an IC look like?What does an IC look like?..

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What does an IC look like? (2)What does an IC look like? (2)

Several metal layers Less congention

Hierarchical scaling Wires on top

levels are widerlevels are wider and taller than on lower levels

T l f Top layers for Power supply Clock

transistors

Clock

Global signals


[ITRS 2003]

What does an IC look like? (3)What does an IC look like? (3)

Intel Penryn dual core.

Th IC The IC

PackagePackage


http://www.intel.com/pressroom/kits/45nm/photos.htm

What does an IC look like? (4)What does an IC look like? (4)45 nm, quad-coreNote the symmetryNote the symmetryTwo dual-cores integrated

#26/43 Department of Computer SystemsSpring 2010 - Erno Salminen http://www.intel.com/pressroom/kits/45nm/photos.htm

What does an IC look like (5)What does an IC look like (5) Actel Fusion Mixed-signal FPGA

1. Integrated Analog-to-Digital g g gConverter (ADC)

2. Fusion Supports Low Power, synchronization

3 Embedded Flash Memory3. Embedded Flash Memory4. Advanced I/O Standards5. Charge Pumps6. Analog Quads6. Analog Quads7. Flash FPGA VersaTile8. SRAM and FIFOs9. Integrated Oscillators—Crystal g y

and RC10.Routing Structure11.JTAG


http://www.actel.com/documents/Fusion_PIB.pdf

Classification: Where HW customization Classification: Where HW customization is doneis donea) In a fabrication facility: ASIC Full-custom, Standard cell,

and Gate array ASIC (Application Specific IC)Specific IC)

b) In the “field”: non-ASIC Simple/Complex field Simple/Complex field

programmable logic device Off-the-shelf SSI/MSI

(S ll/M di S l d IC)(Small/Medium Scaled IC) components


FullFull--custom ASICcustom ASICAll aspects (e.g., size of a transistor) of a circuit

are tailored for a particular application.Circuit fully optimizedDesign extremely complexV ti i d i (T i ll lVery time consuming design (Typically only

feasible for small components)Masks needed for all layersMasks needed for all layers Very expensive Fabrication time up to months

Example: Intel and AMD processors are (partly) Fig. Silicon layout editor


full-custom

StandardStandard--Cell ASICCell ASIC Circuit made using a set of pre-defined logic

components , known as standard cells E.g., basic logic gates, 1-bit adder, D-FFg , g g , , Library cannot be altered albeit

some basic parameters can (e.g. fan-out) Height of a cell is pre-determined

SC-ASIC has rows std cells

g p Layout of the complete circuit is customized

1. The location and type of the standard cells2. Connections between cells

Layout created with special EDA tools

Masks needed for all layers Masks needed for all layers Same fabrication cost as

with full custom Eg Mobile phone digital ICs


Eg. Mobile phone digital ICsCloser look at 4 standard cell rows. Power can ground lines run horizontally inside the cells

Gate array ASICGate array ASIC Circuit is built from an array of a single type of cell

(known as base cell) B ll d d l d i fi d Base cells are pre-arranged and placed in fixed

positions, aligned as one- or two-dimensional array Connections customized by the designer

More sophisticated components (macro cells) can be constructed from base cells

Masks needed only for metal layers (connectionMasks needed only for metal layers (connection wires) Cheaper than full custom

t d d llor standard cell Aka. channelless array or

sea of gates array


sea of gates array

Complex Field Programmable Logic Complex Field Programmable Logic DeviceDevice Device consists of an array of generic logic

cells and general interconnect structure Logic cells and interconnect can be g

“programmed” by utilizing “semiconductor fuses” or “switches”

Customization is done “in the field” Two categories:1. CPLD (Complex Programmable Logic

Device) Sea-of-gates to implement logic

2. FPGA (Field Programmable Gate Array) Look-up tables to implement logic

No custom mask needed For example, Cisco 2600 series routers


Simple Field Programmable Logic Simple Field Programmable Logic Device (PLD)Device (PLD)( )( )Programmable device with simple

internal structure E.g., PROM (Programmable

Read Only Memory), PAL y y)(Programmable Array Logic) No custom mask neededOutdatedReplaced by CPLD/FPGAReplaced by CPLD/FPGA


Fig.1 Example PAL (AND-OR net)

SSI/MSI componentsSSI/MSI componentsSmall discrete parts with fixed,

limited functionalityE f AND t i P i t dE.g. few AND-ports in Printed Circuit Board (PCB)

E g 7400 TTL series hasE.g., 7400 TTL series has more than 100 partsResources (e.g., power, board

Fig.1 Example component

( g , p ,area, manufacturing cost etc.) is consumed by package but not siliconnot siliconNo longer a viable option!Hobby projects Fig 2 TTL clock with 7400s


Hobby projects Fig. 2 TTL clock with 7400s.Rather hackish, ehh.

Viable technologiesViable technologies

Standard Cell/Gate array ASICTKT 1400 ASIC suunnittelu I TKTTKT-1400 ASIC-suunnittelu I, TKT-1500 ASIC design II

FPGA (/CPLD)G (/C )This course


1b. Comparing the technologies1b. Comparing the technologies

Gizmotech

Kludgetech


Comparison criteriaComparison criteriaArea (Size, silicon real-estate): [mm2], [eq. gates][ ], [ q g ]

Speed (Performance): [MHz], operations/second [op/s][ ], p [ p ] Time required to perform a task, [s]

Power consumption, [mW]p , [ ]Cost, [€]Design effort [person-month]Design effort, [person month]


Std cell ASIC versus FPGAStd cell ASIC versus FPGA1. Area [1]

ASIC is smaller since the cells and interconnect are customizedcustomized

FPGA has overhead for programmability and capacity cannot be completely utilized

Roughly: FPGA area is approximately 35x using theRoughly: FPGA area is approximately 35x using the LUT-based logic elements However, that is not seen by FPGA end users – high

volume compensates some costs ($$)2 P f [1]2. Performance [1]

Roughly: ASIC has 3.4 - 4.6x frequency compared to FPGA

3 Power [2]3. Power [2] ASIC is bettter, the ratio ~10x

[1] I K d J R "M i th G b t FPGA d ASIC " i IEEE T ti C t Aid d


[1] I. Kuon and J. Rose, "Measuring the Gap between FPGAs and ASICs" in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, NO. 2, FEBRUARY 2007, pp. 203 - 215. [2] John Blyler, Navigating the Silicon Jungle: FPGA or ASIC?, June / July 2005 issue of Chip Design Magazine, [online]: http://chipdesignmag.com/display.php?articleId=115&issueId=11

Cost of Integrated CircuitsCost of Integrated Circuits Types of cost:1. Chip design costs NRE (Non-Recurring Engineering) cost: one-

time, per-design cost Part cost: per unit cost Part cost: per-unit cost

2. Indirect design costs Lead time: time to get the chip out of the factory Lead time: time to get the chip out of the factory Time-to-market “cost” loss of revenue

Standard cell: high NRE, small part cost and g plarge lead time

FPGA: low NRE, large part cost and small lead time


time

Cost of Integrated Circuits (2)Cost of Integrated Circuits (2) For ASIC, first-time-right necessary FPGA has lower NRE, but higher RE

S it bl f l l Suitable for low volumes Break even volume getting bigger all the time

ASIC cheaperFPGA cheaper

st [€

]

FPGA co

s

ASIC

d

faster growth rate than with ASIC

#chips

trend


#chips

break evenXilinx Inc.

Summary of technologiesSummary of technologies

Trade-off between optimal use of hardware resource and design effort/cost

No single best technology


No single best technology

ConclusionsConclusions


ConclusionsConclusionsTwo viable implementation technologies: ASIC

and FPGAASICs are smaller in area and faster than FPGAASICs have low unit cost but high NRE, FPGA

vice versavice versa ASICs used in high volume products, FPGAs in

tailorable productsFPGA is a ”programmable ASIC” (custom IC,

actually) i e someone has done an IC which application is i.e. someone has done an IC which application is

FPGA Extra resources needed to provide in-field


configuration

lecture 1lecture 1-- introductionintroduction · rtl hardware design using vhdl: coding for...

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