lecture 13 biasing and loading single stage fet amplifiers

1

ECE 315 – Spring 2007 – Farhan Rana – Cornell University

Lecture 13

Biasing and Loading Single Stage FET Amplifiers

The Building Blocks of Analog Circuits - III

In this lecture you will learn:

• Current biasing of circuits • Current sources and sinks for CS, CG, and CD circuits


A Poor Man’s Current Source

What if one wanted to bias a device with a current source?

BIASI

………but one only had a voltage source?

Solution: Use a large voltage source with a large resistor in series!

BIASVR

I

BIAS BIAS

D

V VI

R R R

DR

DRPoor man’s current source

2


DDV

R

SR

+

-

+

-

BIASV

sv

The Common Source Amplifier

Rrgv

Ri

v

vA om

in

d

in

outv ||

Open circuit voltage gain:

+

-

outOUT vV

DI


The Common Source Amplifier: Problems

Rrgv

vA om

in

outv ||


To achieve large gain one needs:1) A large DC current bias ID in order to get a large gm

2) A large value of the resistor R

In saturation:

DSnDnGS

Dm VIk

VI

g

12

Both the above requirements cannot be met easily simultaneously: Not easy to realize large resistors in micro-chips A large resistor R will limit the maximum value of the DC current bias ID (because

the potential drop IDR can become large enough to put the FET in the linear region where gm and the gain will be small)

3


The Digital Logic Inverter: Problems

To achieve fast switching one needs:1) A small resistor (because then the RCL charging time will be smaller when the

output switches from “0” to “1”)

00

OUTV

INVTNV

DDV TNIN VV

Cut-off

Saturation

Linear

But A small resistor will require a very large current (to achieve a large potential drop

across it) when the input is “1”, and the NFET is turned on, and the output need to be low or “0” – and this means more power dissipation

When the input is “1”, and the NFET is turned on, there is constant static power dissipation


The Common Source Amplifier with a Current SourceDDV

BIASI

SR

+

-sv

+

-

outOUT vV

DI

What is needed is an ideal current source in the drain that can supply a large DC current and at the same time has a large small signal resistance

The incremental (or differential or small signal) resistance looking into an ideal current source is infinite

+

-BIASV

omin

outv rg

v

vA

An ideal current source, of course, does not exist

But one can certainly do much better than using a resistor in the drain

4


The Common Source Amplifier with a Current Source: DC Biasing

BIASI

DSnTNGSoxnBIASD VVVCL

WII 1

22

00

DSV

DI

1OUTV 2OUTV

gmVBIAS

Suppose for VBIAS1 the output was VOUT1

Suppose VBIAS1 is changed to a smaller value VBIAS2

VBIAS = VBIAS2 – VBIAS1 < 0

The output VOUT2 can be obtained graphically, as shown


The Common Source Amplifier with a Current Source: DC Biasing

5


The CS Amplifier with a Current Source: Small Signal Analysis

Gate Drain

gsmvg

+gsv-

gi

Source

oroutv+

-inv+

-

di

bsmbvg

+bsv-

Base

0

omin

outv rg

v

vA


oout rR

Output resistance:

Large

Large


Large Signal Model of a Current SourceThe output resistance of the current sourceBIASI

Large signal circuit model

ocr

A large signal model of a current source roc is large for a good current source and infinite for an ideal current source

A current source

BIASI

Ideal current source

IOUT

VOUT

IBIAS

ocOUT

OUT

rdV

dI 1

Slope

ocr BIASIOUTV

OUTI+

-

One can have any voltage at the at the output terminals of a good current source and the current delivered will remain mostly constant

ocr

6


Small Signal Model of a Current Source

BIASISmall signal circuit model

ocr

A current source

IOUT

VOUT

IBIAS

ocOUT

OUT

rdVdI 1

Slope

ocr BIASIOUTV

OUTI+

-

The output resistance of the current source

ocr BIASI



ocr


Large Signal Model of a Current SinkThe output resistance of the current sinkBIASI


ocr

A large signal model of a current source roc is large for a good current source and infinite for an ideal current source

A current sink

BIASI


IOUT

VOUT

IBIAS

ocOUT

OUT

rdV

dI 1

Slope

ocr BIASIOUTV

OUTI+

-

One can have any voltage at the at the output terminals of a good current sink and the current dinked will remain mostly constant

ocr

7


Small Signal Model of a Current Sink

BIASISmall signal circuit model

ocr

A current sink

IOUT

VOUT

IBIAS

ocOUT

OUT

rdV

dI 1

Slope

ocr BIASIOUTV

OUTI+

-

The output resistance of the current source

ocr BIASI



ocr


PFET Loaded NFET Common Source Amplifier

DDV

BIASI

SR

+

-sv

+

-

outOUT vV

DI

+

-BIASV

An ideal current source, of course, does not exist

But one can certainly do much better than using a resistor in the drain

Use a PFET!

DDV

SR

+

-sv

+

-

outOUT vV

DI

+

-BIASV

A PFETload

BV

A PFET approximation to a current source

8


Current Sink:

I I roc

IOUT

VOUT

One can have any voltage at the at the output terminals of a good current sink and the current sinked will remain mostly constant

Current Sinks and NFET Transistors

OUTV

OUTI

DI

OUTI

OUTV

oo

OUT

OUT

rg

dV

dI 1

Slope

Characteristics in saturation resemble that of a non-ideal current source!

IOUT

VOUT

IBIAS

ocOUT

OUT

rdV

dI 1

Slope

+

-

+

-

roc

VB


Current Sources:

I I roc

IOUT

VOUT

One can have any voltage at the at the output terminals of a good current source and the current delivered will remain mostly constant

Current Sources and PFET Transistors

OUTV

OUTI

DI

Characteristics in saturation resemble that of a non-ideal current source!

IOUT

VOUT

IBIAS

ocOUT

OUT

rdV

dI 1

Slope

OUTI

OUTV

oo

OUT

OUT

rg

dV

dI 1

Slope

+

-

+

-roc

VB

9


PFET Loaded NFET: Large Signal Analysis

00

DDV

DI

OUTV

M2

M1

DDOUTDS

OUTDS

VVV

VV

2

1

21 DDD III

BIASVBV

DC value of the output voltage (Both FETs in saturation)

Instead of the resistive load line, we now have the full ID vs VDS curves of the PFET

The biasing voltages need to be selected carefully, otherwise one of the transistors can go into the linear region!!

PFET NFET


00

DDV

DI

OUTV

BIASV

BV

Instead of the resistive load line, we now have the full ID vs VDS curves of the PMOS

The biasing voltages need to be selected carefully, otherwise one of the transistors can go into the linear region!!

PFET NFET

DC value of the output voltage (PFET in the linear region)


DDOUTDS

OUTDS

VVV

VV

2

1

21 DDD III

M2

M1

1

ID2

ID =

10


OUTnTNBIASn

DSnTNGSn

D VVVk

VVVk

I 12

12

21

211

DDOUTpTPDDBp

DSpTPGSp

D VVVVVk

VVVk

I 12

12

22

222

NFET

PFET

Assuming the biasing is correct, both the FETs are in saturation

Equate the drain current magnitudes of the two FETs

Then the only unknown will be VOUT ; solve for it

Verify that the obtained value of VOUT does indeed result in both the transistors being in saturation

Equating:

OUTDDpTPDDBp

OUTnTNBIASn

DDD

VVVVVk

VVVk

III

12

12

22

21


M2

M1

1

ID2


PFET Loaded NFET: Transfer Curve

M2

M1

00

OUTV

INVTNV

DDV TNIN VV

I

II

IV

I: VIN < VTNM1 cut-off

II: VIN > VTN & VOUT > VIN - VTN & VOUT > VB - VTPM1 saturation, M2 Linear

III: VIN > VTN & VOUT > VIN - VTN & VOUT < VB - VTPM1 saturation, M2 saturation

IV: VIN > VTN & VOUT < VIN - VTN & VOUT < VB - VTPM1 linear, M2 saturation

TPB VV III Increasing VIN

I

II

IV

III

1

VB

11


Gate1 Drain1

11 gsm vg

+1gsv

-

1gi

Source1

1oroutv+

-inv+

-

1di

Gate2 Drain2

22 gsm vg

+2gsv

-

2gi

Source2

2or

2di

PFET

NFET

Looking into the drain end of the PFET, what does one see?

PFET Loaded NFET: Small Signal Analysis

SR+

-sv

M2

M1

1


Gate1 Drain1

11 gsm vg

+1gsv

-

1gi

Source1

1oroutv+

-inv+

-

1di

Drain2

2or

2di

NFET

Looking into the drain end of the PFET, what does one see?

PMOS Loaded NMOS: Small Signal Analysis

SR+

-sv

M2

M1

1

12


11 gsm vg

+1gsv

-

1gi

1oroutv+

-inv+

-

1di

2or

211 || oomin

outv rrg

v

vA


21 || ooout rrR

Output resistance:

PFET Loaded NFET: Small Signal Analysis

M2

M1

1


DDV

SR

+

-sv

+

-

outOUT vV

1DI

+

-BIASV

PFETload

2BV

3BV

M2

M1

M3

This load has a larger resistance looking into it

PFET Loaded NFET: The Cascode PFET Load

DDV

SR

+

-sv

+

-

outOUT vV

1DI

+

-BIASV

PFETload

2BVM2

M1

DRBetter

This topology is called the “Cascode” current load

13


Gate2 Drain2

22 gsm vg

+2gsv

-

2gi

Source2

2or

2di

PFET

Gate3 Drain3

33 gsm vg

+3gsv

-

3gi

Source3

3or

3di

PFET

Cascode PEFT Load: Small Signal Analysis

PFETload

1

ID2

ID3


Gate2 Drain2

22 gsm vg

+2gsv

-

2gi

Source2

2or

2di

PFET

Drain3

3or

3di

Cascode PFET Load: Small Signal Analysis

PFETload

1

ID2

ID3

14


Gate2 Drain2

22 gsm vg

+2gsv

-

2gi

Source2

2or

2di

3or

Resistance looking into the current source is:

322223232232 1 oomomoooomoo rrgrgrrrrgrr


PFETload

1

Typically a good approximation

ID2

ID3


2di

Resistance looking into the current source is:

322223232232 1 oomomoooomoo rrgrgrrrrgrr


PFETload

1


ID2

ID3

322

2232 1

oom

omoo

rrg

rgrr

15


11 gsm vg

+1gsv

-

1gi

1oroutv+

-inv+

-

1di

322 oom rrg

1132211 || omoomomin

outv rgrrgrg

v

vA


13221 || ooomoout rrrgrR

Output resistance:

NFET


PFETload




The Common Source Amplifier: General TopologyV

BIASI

OUTV

INVBIASI

OUTV

INV

V

V

V

NFET PFET

V + is the most positive voltage in the circuitV - is the most negative voltage in the circuit

Large input resistanceLarge output resistanceLarge voltage gainLarge current gain

16


The Common Gate Amplifier: General TopologyV

BIASI

OUTV

INV BIASI

OUTV

V

V

V

INV

Can have small input resistanceLarge output resistanceLarge voltage gainSmall (unity) current gain

GV

GV

NFET PFET


The Common Drain Amplifier: General TopologyV

BIASI

OUTV

INV

BIASI

OUTV

INV

V

V

V

Large input resistanceSmall output resistanceSmall (less than unity) voltage gain

NFET PFET

17


Chip-Based Current Sources and Voltage Sources

We have realized a decent load but ……

How does one generate voltage levels on a chip for biasing??

Current and voltage biasing of circuits require transistor based current and voltage sources on a chip!

What are the good figures of merit of chip-based voltage and current sources?

lecture 13 biasing and loading single stage fet amplifiers

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