lecture 11: risc-veecs151/sp20/files/lec11...computer science 61c spring 2018 wawrzynek and weaver...
TRANSCRIPT
EE141
EECS 151/251ASpring2020 DigitalDesignandIntegratedCircuitsInstructor:JohnWawrzynek
Lecture 11: RISC-V
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Project Introduction❑ You will design and optimize a RISC-V
processor ❑ Phase 1: Design and demonstrate a processor ❑ Phase 2: ▪ ASIC Lab – implement cache memory and generate
complete chip layout ▪ FPGA Lab – Add video display and graphics
accelerator
2
Today discuss how to design the processor
WhatisRISC-V?• FifthgenerationofRISCdesignfromUCBerkeley• Ahigh-quality,license-free,royalty-freeRISCISAspecification• Experiencingrapiduptakeinbothindustryandacademia• Supportedbygrowingsharedsoftwareecosystem• Appropriateforalllevelsofcomputingsystem,frommicro-
controllerstosupercomputers– 32-bit,64-bit,and128-bitvariants(we’reusing32-bitinclass,
textbookuses64-bit)• Standardmaintainedbynon-profitRISC-VFoundation
�3https://riscv.org/specifications/
FoundationMembers(60+)
4Rumble Development
Platinum:
Gold,Silver,Auditors:
InstructionSetArchitecture(ISA)• JobofaCPU(CentralProcessingUnit,akaCore):
executeinstructions• Instructions:CPU’sprimitivesoperations
– Instructionsperformedoneafteranotherinsequence– Eachinstructiondoesasmallamountofwork(atinypartofa
largerprogram).– Eachinstructionhasanoperationappliedtooperands,– andmightbeusedchangethesequenceofinstruction.
• CPUsbelongto“families,”eachimplementingitsownsetofinstructions
• CPU’sparticularsetofinstructionsimplementsanInstructionSetArchitecture(ISA)
– Examples:ARM,Intelx86,MIPS,RISC-V,IBM/MotorolaPowerPC(oldMac),IntelIA64,... �5
If you need more info on processor organization.
RISCProcessorInstructionsinBrief
• Compilersgeneratemachineinstructionstoexecuteyourprogramsinthefollowingway:• Load/Storeinstructionsmoveoperandsbetweenmainmemory(cachehierarchy)andcoreregisterfile.• Register/Registerinstructionsperformarithmeticandlogicaloperationsonregisterfilevaluesasoperandsandresultreturnedtoregisterfile.
• Register/Immediateinstructionsperformarithmeticandlogicaloperationsonregisterfilevalueandconstants.
• Branchinstructionsareusedforloopingandif-than-else(datadependentoperations).• Jumpsareusedforfunctioncallandreturn. �6
IMEM
+4
rs2rs1rd
Reg[]
ALU
DMEM
immPC
mux
CompleteRV32IISA
�7
NotinEECS151/251A **
* implemented in the ASIC project
Computer Science 61C Spring 2018 Wawrzynek and Weaver
Summary of RISC-V Instruction Formats
8
Binary encoding of machine instructions. Note the common fields.
“State”RequiredbyRV32IISAEachinstructionreadsandupdatesthisstateduringexecution:• Registers(x0..x31)−Registerfile(orregfile)Regholds32registersx32bits/register:Reg[0].. Reg[31]
−Firstregisterreadspecifiedbyrs1fieldininstruction−Secondregisterreadspecifiedbyrs2fieldininstruction−Writeregister(destination)specifiedbyrdfieldininstruction−x0isalways0(writestoReg[0]areignored)
• ProgramCounter(PC)−Holdsaddressofcurrentinstruction
•Memory(MEM)−Holdsbothinstructions&data,inone32-bitbyte-addressedmemoryspace
−We’lluseseparatememoriesforinstructions(IMEM)anddata(DMEM)▪ Laterwe’llreplacethesewithinstructionanddatacaches
−Instructionsareread(fetched)frominstructionmemory(assumeIMEMread-only)
−Load/storeinstructionsaccessdatamemory
�9
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RISC-V State Elements
10
❑ State encodes everything about the execution status of a processor: – PC register – 32 registers – Memory
Note: for these state elements, clock is used for write but not for read (asynchronous read, synchronous write).
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EECS150 - Lec07-MIPS
RISC-V Microarchitecture Oganization
11
Datapath + Controller + External Memory
Controller
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Microarchitecture
Multiple implementations for a single instruction set architecture:
– Single-cycle – Each instruction executes in a single clock cycle.
– Multicycle – Each instruction is broken up into a series of shorter steps with one step per clock
cycle. – Pipelined (variant on “multicycle”)
– Each instruction is broken up into a series of steps with one step per clock cycle – Multiple instructions execute at once by overlapping in time.
– Superscalar – Multiple functional units to execute multiple instructions at the same time
– Out of order... – Instructions are reordered by the hardware
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FirstDesign:One-Instruction-Per-CycleRISC-VMachine
1. Currentstateoutputsdrivetheinputstothecombinationallogic,whoseoutputssettlesatthevaluesofthestatebeforethenextclockedge
2. Attherisingclockedge,allthestateelementsareupdatedwiththecombinationallogicoutputs,andexecutionmovestothenextclockcycle(nextinstruction)�13
Reg[]
pc
IMEM
DMEM
CombinationalLogic
clock
Oneverytickoftheclock,thecomputerexecutesoneinstruction
BasicPhasesofInstructionExecution
1.InstructionFetch
2.Decode/Register
Read
3.Execute 4.Memory 5.RegisterWrite
�14
IMEM
+4
rs2rs1rd
Reg[]
ALU
DMEM
imm
PCmux
Clocktime
Implementingtheaddinstruction
add rd, rs1, rs2
• Instructionmakestwochangestomachine’sstate: Reg[rd] = Reg[rs1] + Reg[rs2] PC = PC + 4
�15
ControlLogic
Datapathforadd
�16
+4
pcpc+4
inst[11:7]
inst[19:15]
inst[24:20]
IMEM
inst[31:0]
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD Reg[rs1]
Reg[rs2]+ alu
(RegWriteEnable)RegWEn(1=write,0=nowrite)
TimingDiagramforadd
�17
1000 1004PC
1004 1008PC+4
add x1,x2,x3 add x6,x7,x9inst[31:0]
Clock
time
+4
pcpc+4 inst[11:7]
inst[19:15]inst[24:20]
IMEM
inst[31:0]
+RegWEn
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD Reg[rs1]
Reg[rs2]
clock
alu
Reg[2] Reg[7]Reg[rs1]
Reg[2]+Reg[3]alu Reg[7]+Reg[9]
Reg[3] Reg[9]Reg[rs2]
???Reg[1] Reg[2]+Reg[3]
Implementingthesubinstruction
sub rd, rs1, rs2
Reg[rd] = Reg[rs1] - Reg[rs2]
• Almostthesameasadd,exceptnowhavetosubtractoperandsinsteadofaddingthem
• inst[30]selectsbetweenaddandsubtract
�18
ControlLogic
Datapathforadd/sub
�19
+4
pcpc+4
inst[11:7]
inst[19:15]
inst[24:20]
IMEM
inst[31:0] RegWEn(1=write,0=nowrite)
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD Reg[rs1]
Reg[rs2]aluALU
ALUSel(Add=0/Sub=1)
ImplementingotherR-Formatinstructions
• Allimplementedbydecodingfunct3andfunct7fieldsandselectingappropriateALUfunction
�20
Implementingtheaddiinstruction• RISC-VAssemblyInstruction:addi rd, rs1, integer Reg[rd] = Reg[rs1] + sign_extend(immediate) example: addi x15,x1,-50
�21
111111001110 00001 000 01111 0010011
OP-Immrd=15ADDimm=-50 rs1=1
Uses the “I-type” instruction format
ControlLogic
Review:Datapathforadd/sub
�22
+4
pcpc+4
inst[11:7]
inst[19:15]
inst[24:20]
IMEM
inst[31:0] RegWEn(1=write,0=nowrite)
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD Reg[rs1]
Reg[rs2]alu
ALU
ALUSel(Add=0/Sub=1)
ControlLogic
Addingadditodatapath
�23
+4
pcpc+4
inst[11:7]
inst[19:15]
inst[24:20]
IMEM
inst[31:0]
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Reg[rs1]
Reg[rs2]
aluALU
ALUSel=Add
Imm.Gen
0
1
RegWEn=1
inst[31:20] imm[31:0]
ImmSel=I BSel=1
I-typeFormatimmediates
�24
inst[31:0]
------inst[31]-(sign-extension)------- inst[30:20]
imm[31:0]Imm.Gen
inst[31:20] imm[31:0]
ImmSel=I
• High12bitsofinstruction(inst[31:20])copiedtolow12bitsofimmediate(imm[11:0])
• Immediateissign-extendedbycopyingvalueofinst[31]tofilltheupper20bitsoftheimmediatevalue(imm[31:12])
ControlLogic
Addingadditodatapath
CS61c �25
+4
pcpc+4
inst[11:7]
inst[19:15]
inst[24:20]
IMEM
inst[31:0]
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Reg[rs1]
Reg[rs2]
aluALU
ALUSel=Add
Imm.Gen
0
1
RegWEn=1
inst[31:20] imm[31:0]
ImmSel=I BSel=1
AlsoworksforallotherI-formatarithmeticinstruction(slti,sltiu,andi,ori,xori,slli,srli,srai)justbychangingALUSel
ImplementingLoadWordinstruction• RISC-VAssemblyInstruction:lw rd, integer(rs1) Reg[rd] = DMEM[Reg[rs1] + sign_extend(immediate)] example: addi x14,8(x2)
�26
000000001000 00010 010 01110 0000011
LOADrd=14LWimm=+8 rs1=2
Also uses the “I-type” instruction format
ControlLogic
Review:Addingadditodatapath
�27
+4
pcpc+4
inst[11:7]
inst[19:15]
inst[24:20]
IMEM
inst[31:0]
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Reg[rs1]
Reg[rs2]
aluALU
ALUSel=Add
Imm.Gen
0
1
RegWEn=1
inst[31:20]imm[31:0]
ImmSel=I BSel=1
Addinglwtodatapath
�28
IMEM ALU
Imm.Gen
+4
DMEM
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr DataR 0
1pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:20]
alu
mem
wbpc+4
Reg[rs1]
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel RegWEn BSel ALUSel MemRW WBSel
wb
Addinglwtodatapath
CS61c �29
IMEM ALU
Imm.Gen
+4
DMEM
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr DataR 0
1pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:20]
alu
mem
wbpc+4
Reg[rs1]
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel=I RegWEn=1 BSel=1 ALUSel=add MemRW=Read WBSel=0
wb
AllRV32LoadInstructions
• Supportingthenarrowerloadsrequiresadditionalcircuitstoextractthecorrectbyte/halfwordfromthevalueloadedfrommemory,andsign-orzero-extendtheresultto32bitsbeforewritingbacktoregisterfile.
�30
funct3fieldencodessizeandsignednessofloaddata
ImplementingStoreWordinstruction• RISC-VAssemblyInstruction:sw rs2, integer(rs1) DMEM[Reg[rs1] + sign_extend(immediate)] = Reg[rs2] example: sw x14, 8(x2)
�31
0000000 01110 00010 010 01000 0100011
STOREoffset[4:0]=8
SWoffset[11:5]=0
rs2=14 rs1=2
combined12-bitoffset=80000000 01000
Uses the “S-type” instruction format
Review:Addinglwtodatapath
�32
IMEM ALU
Imm.Gen
+4
DMEM
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr DataR 0
1pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:20]
alu
mem
wbpc+4
Reg[rs1]
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel RegWEn BSel ALUSel MemRW WBSel
wb
Addingswtodatapath
�33
IMEMALU
Imm.Gen
+4
DMEM
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR 0
1pc0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
alu
mem
wbpc+4
Reg[rs1]
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel=S RegWEn=0 Bsel=1 ALUSel=Add MemRW=Write WBSel=*
wb
*=“Don’tCare”
CS61c �34
IMEM ALU
Imm.Gen
+4
DMEM
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr DataR 0
1pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
alu
mem
wbpc+4
Reg[rs1]
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel=S RegWEn BSel=1 ALUSel=Add MemRW=Write WBSel=*
wb
Addingswtodatapath
*=“Don’tCare”
Review:I-Formatimmediates
�35
inst[31:0]
------inst[31]-(sign-extension)------- inst[30:20]
imm[31:0]Imm.Gen
inst[31:20] imm[31:0]
ImmSel=I
• High12bitsofinstruction(inst[31:20])copiedtolow12bitsofimmediate(imm[11:0])
• Immediateissign-extendedbycopyingvalueofinst[31]tofilltheupper20bitsoftheimmediatevalue(imm[31:12])
I&S-typeImmediateGenerator
�36
imm[11:5] rs2 rs1 funct3 imm[4:0] S-opcode
imm[11:0] rs1 funct3 rd I-opcode
inst[31](sign-extension) inst[30:25]
imm[31:0]
inst[31:0]
inst[24:20]
SI
inst[31](sign-extension) inst[30:25] inst[11:7]
067111214151920242531
045101131
1 65
5
S
I
• Justneeda5-bitmuxtoselectbetweentwopositionswherelowfivebitsofimmediatecanresideininstruction
• Otherbitsinimmediatearewiredtofixedpositionsininstruction
ImplementingBranches
• B-formatismostlysameasS-Format,withtworegistersources(rs1/rs2)anda12-bitimmediate
• Butnowimmediaterepresentsvalues-4096to+4094in2-byteincrements
• The12immediatebitsencodeeven13-bitsignedbyteoffsets(lowestbitofoffsetisalwayszero,sononeedtostoreit) �37
Uses the “B-type” instruction format
• RISC-VAssemblyInstruction,example:beq rs1, rs2, label if rs1==rs2 pc ← pc + offset // offset computed by compiler/assembler and
stored in the immediate field(s)
example: beq x1, x2, L1
Review:Addingswtodatapath
�38
IMEMALU
Imm.Gen
+4
DMEM
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR 0
1pc0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
alu
mem
wbpc+4
Reg[rs1]
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel RegWEn Bsel ALUSel MemRW WBSel=
wb
Addingbranchestodatapath
�39
IMEMALU
Imm.Gen
+4
DMEMBranchComp.
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR
1
0
01
1
0pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
alu
mem
wb
alu
pc+4
Reg[rs1]
pc
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel RegWEn BrUn BrEq BrLT ASelBSel ALUSel MemRW WBSelPCSel
wb
Addingbranchestodatapath
�40
IMEMALU
Imm.Gen
+4
DMEMBranchComp.
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR
1
0
01
1
0pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
alu
mem
wb
alu
pc+4
pc
imm[31:0]
Reg[rs2]
wb
inst[31:0] ImmSel=B RegWEn=0 BrUn BrEq BrLT ASel=1Bsel=1
ALUSel=Add
MemRW=Read WBSel=*PCSel=taken/not-taken
Reg[rs1]
BranchComparator• BrEq=1,ifA=B• BrLT=1,ifA<B• BrUn=1selectsunsignedcomparisonforBrLT,0=signed
• BGEbranch:A>=B,if!(A<B)
�41
BranchComp.
A
B
BrUn BrEq BrLT
RISC-VBranchImmediates• 12-bitimmediateencodesPC-relativeoffsetof-4096to+4094bytesinmultiplesof2bytes• RISC-Vapproach:keep11immediatebitsinfixedpositioninoutputvalue,androtateLSBofS-
formattobebit12ofB-format
�42
sign=imm[11] imm[10:5] imm[4:0]
sign=imm[12] imm[10:5] imm[4:1] 0
S-Immediate
B-Immediate(shiftleftby1)
OnlyonebitchangespositionbetweenSandB,soonlyneedasingle-bit2-waymux
imm[11]
RISC-VImmediateEncoding
�43
InstructionEncodings,inst[31:0]
32-bitimmediatesproduced,imm[31:0]
Onlybit7ofinstructionchangesroleinimmediatebetweenSandBUpperbitssign-extendedfrominst[31]always
ImplementingJALRInstruction(I-Format)
• JALRrd,rs,immediate−WritesPC+4toReg[rd](returnaddress)− SetsPC=Reg[rs1]+offset− Usessameimmediatesasarithmeticandloads▪ nomultiplicationby2bytes
�44
Review:Addingbranchestodatapath
�45
IMEMALU
Imm.Gen
+4
DMEMBranchComp.
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR
1
0
01
1
0pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
alu
mem
wb
alu
pc+4
pc
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel RegWEn BrUn BrEq BrLT ASelBSel ALUSel MemRW WBSelPCSel
wbReg[rs1]
�46
IMEMALU
Imm.Gen
+4
DMEMBranchComp.
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR
1
01
0pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
alu
mem
wb
alu
pc+4
Reg[rs1]
pc
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel RegWEn BrUn BrEq BrLT ASelBSel ALUSel MemRW WBSelPCSel
wb
Addingjalrtodatapath
012
pc+4
Addingjalrtodatapath
�47
IMEMALU
Imm.Gen
+4
DMEM
BranchComp.
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR
1
0
0121
0pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
pc+4alu
mem
wb
alu
pc+4
Reg[rs1]
pc
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel=B RegWEn=1
BrUn=* BrEq=* BrLT=*
Asel=0Bsel=1
ALUSel=Add
MemRW=Read WBSel=2PCSel
wb
ImplementingjalInstruction
• JALsavesPC+4inReg[rd](thereturnaddress)• SetPC=PC+offset(PC-relativejump)• Targetsomewherewithin±219locations,2bytesapart− ±21832-bitinstructions
• Immediateencodingoptimizedsimilarlytobranchinstructiontoreducehardwarecost
�48
Uses the “J-type” instruction format
Addingjaltodatapath
�49
IMEMALU
Imm.Gen
+4
DMEMBranchComp.
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR
1
0
0121
0pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
pc+4alu
mem
wb
alu
pc+4
pc
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel RegWEn BrUn BrEq BrLT ASelBSel ALUSel MemRW WBSelPCSel
wbReg[rs1]
Addingjaltodatapath
�50
IMEMALU
Imm.Gen
+4
DMEMBranchComp.
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR
1
0
0121
0pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
pc+4alu
mem
wb
alu
pc+4
Reg[rs1]
pc
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel=J RegWEn=1
BrUn=* BrEq=* BrLT=*
Asel=1Bsel=1
ALUSel=Add
MemRW=Read WBSel=2PCSel
wb
Single-CycleRISC-VRV32IDatapath
�51
IMEMALU
Imm.Gen
+4
DMEMBranchComp.
Reg[]
AddrAAddrB
DataAAddrD
DataB
DataD
Addr
DataWDataR
1
0
0121
0pc
0
1
inst[11:7]
inst[19:15]
inst[24:20]
inst[31:7]
pc+4alu
mem
wb
alu
pc+4
pc
imm[31:0]
Reg[rs2]
inst[31:0] ImmSel RegWEn BrUn BrEq BrLT ASelBSel ALUSel MemRW WBSelPCSel
wbReg[rs1]
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Controller Implementation:❑ Control logic works really well as a case
statement...always @* begin op = instr[26:31]; imm = instr[15:0]; ... reg_dst = 1'bx; // Don't care reg_write = 1'b0; // By default don’t write ... case (op) 6'b000000: begin reg_write = 1; ... end ...
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COVID-19 Announcements (tentative)❑ Lectures: ❑ All lectures are recorded and available online. ❑ If you feel ill, please do not come to class. ❑ If you feel uncomfortable coming to class, or would simply like to do you
part to help stop the spread, please feel free not to come. ❑ Labs: ❑ Lab meetings will continue, however, … ❑ If you feel ill, please do not come to lab, but do let us know. ❑ All lab software is available remotely, so feel free to not work in 125 Cory. ❑ FPGA boards are available for check-out. ❑ Check-offs will be done in person as before, or now can be done with
Zoom/Skype (contact Tan). 53
EE141
COVID-19 Announcements (tentative)❑ Exam: ❑ To be held during previously scheduled time slot, 6-9PM Thursday. ❑ However, it will be take-at-home style. ❑ Exam will be posted at 6PM and your solution must be turned in using
gradescope by 9PM. ❑ You will be allowed to use lecture notes and other resources, but not
allowed to discuss exam questions or answers with other students during the exam time.
❑ Office hours: ❑ for meeting the GSIs or professor, in addition to in person meetings,
teleconference (Skype/Zoom) will be available ❑ Discussion Session: ❑ Will be held as usual, and Zoom will be used for remote participation.
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Processor Pipelining
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Review: Processor Performance
Program Execution Time
= (# instructions)(cycles/instruction)(seconds/cycle)
= # instructions x CPI x TC
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Single-Cycle Performance• TC is limited by the critical path (lw)
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Single-Cycle Performance
• Single-cycle critical path:
Tc = tq_PC + tmem + max(tRFread, tsext + tmux) + tALU + tmem + tmux + tRFsetup
• In most implementations, limiting paths are:
– memory, ALU, register file. – Tc = tq_PC + 2tmem + tRFread + tmux + tALU + tRFsetup
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Pipelined Processor
• Use temporal parallelism • Divide single-cycle processor into 5 stages: – Fetch – Decode – Execute – Memory –Writeback • Add pipeline registers between stages
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Single-Cycle vs. Pipelined Performance
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Single-Cycle and Pipelined Datapath
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Corrected Pipelined Datapath• WriteReg must arrive at the same time as Result
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Pipelined Control
Same control unit as single-cycle processor
Control delayed to proper pipeline stage 63
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Pipeline Hazards❑ Occurs when an instruction depends on results from
previous instruction that hasn’t completed. ❑ Types of hazards: –Data hazard: register value not written back to
register file yet –Control hazard: next instruction not decided yet
(caused by branches)
64
We need to design ways to avoid hazards, else we pay the price in CPI (cycles per instruction) and processor performance suffers.
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Processor Pipelining
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IF1 IF2 ID X1 X2 M1 M2 WBIF1 IF2 ID X1 X2 M1 M2 WB
Deeper pipelines => less logic per stage => high clock rate.
Deeper pipeline example.
Deeper pipelines* => more hazards => more cost and/or higher CPI.
Remember, Performance = # instructions X Frequencyclk / CPI
But
Cycles per instruction might go up because of unresolvable hazards.
How about shorter pipelines ... Less cost, less performance (but higher cost efficiency)
*Many designs included pipelines as long as 7, 10 and even 20 stages (like in the Intel Pentium 4). The later "Prescott" and "Cedar Mill" Pentium 4 cores (and their Pentium D derivatives) had a 31-stage pipeline.
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3-Stage Pipeline
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3-Stage Pipeline (used for FPGA/ASIC project)
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I X M
The blocks in the datapath with the greatest delay are: IMEM, ALU, and DMEM. Allocate one pipeline stage to each:
Use PC register as address to IMEM and retrieve next
instruction. Instruction gets stored in a pipeline register,
also called “instruction register”, in this case.
Most details you will need to work out for yourself. Some details to follow ... In particular, let’s look at hazards.
Access data memory or I/O device for load or store. Allow for setup time for register file write.
Use ALU to compute result, memory
address, or branch target address.
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3-stage Pipeline
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add x5, x3, x4 I X M add x7, x6, x5 I X M
reg 5 value updated herereg 5 value needed here!
Data Hazard
Selectively forward ALU result back to input of ALU.
The fix:
• Need to add mux at input to ALU, add control logic to sense when to activate. Check reference for details.
ALU
control
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3-stage Pipeline
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lw x5, offset(x4) I X MI X M
Memory value known here. It is written into the regfile on this edge.
value needed here!
Load Hazard
add x7, x6, x5
lw x5, offset(x4) I X MI nop nop
I X M add x7, x6, x5 add x7, x6, x5
The fix: Delay the dependent instruction by one cycle to allow the load to complete, send the result of load directly to the ALU (and to the regfile). No delay if not dependent!
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Control Hazard3-stage Pipeline
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beq x1, x2, L1 I X M add x5, x3, x4 I X M
add x6, x1, x2 I X ML1: sub x7, x6, x5 I X
branch address ready herebut needed here!
The fix:Several Possibilities:* 1. Always delay fetch of instruction after branch 2. Assume branch “not taken”, continue with instruction
at PC+4, and correct later if wrong. 3. Predict branch taken or not based on history (state)
and correct later if wrong.
1. Simple, but all branches now take 2 cycles (lowers performance) 2. Simple, only some branches take 2 cycles (better performance) 3. Complex, very few branches take 2 cycles (best performance)
* MIPS defines “branch delay slot”, RISC-V doesn’t
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Control HazardPredict “not taken”
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bneq x1, x1, L1 I X M add x5, x3, x4 I X M
add x6, x1, x2 I X ML1: sub x7, x6, x5 I X
beq x1, x1, L1 I X M add x5, x3, x4 I nop nopL1: sub x7, x6, x5 I X M
Branch address ready at end of X stage: • If branch “not taken”, do nothing. • If branch “taken”, then kill instruction in I stage (about to
enter X stage) and fetch at new target address (PC)
Not taken
Taken
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EECS151 Project CPU Pipelining Summary
❑ Pipeline rules: –Writes/reads to/from DMem are clocked on the leading
edge of the clock in the “M” stage –Writes to RegFile at the end of the “M” stage – Instruction Decode and Register File access is up to you.
❑ Branch: predict “not-taken”
❑ Load: 1 cycle delay/stall on dependent instruction
❑ Bypass ALU for data hazards
❑ More details in upcoming spec 72
I X Minstruction
fetchexecute access
data memory
3-stage pipeline