lecture 11 phase locked loop (pll): appendix...

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EE4900/EE6720 Digital Communications Suketu Naik

EE4900/EE6720: Digital Communications

Lecture 11

Phase Locked Loop

(PLL): Appendix C

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Block Diagrams of Communication System

Digital Communication System

Informatio

n (sound,

video, text,

data, …)

Transducer &

A/D ConverterModulator

Source

Encoder

Channel

Encoder

Tx RF

System

Output

Signal

D/A Converter

and/or output

transducer

DemodulatorSource

Decoder

Channel

Decoder

Rx RF

System

Channel

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PLL: Core Component for the Receiver

Example: AM Radio

Local

Oscillator

Received

Signal

Mixer

(Multiplier)

Low

Pass FilterRemove

DC

Demodulated

Signal

Same Frequency

As the Carrier Signal

Transmitter

Receiver

Phase Locked Loop (PLL)

is used to get the precise

frequency

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Super Heterodyne Receiver



frequency

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Zero IF or Direct Conversion Receiver



frequency

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Continuous-time PLL Basics

PLL a device that tracks phase and frequency of a

sinusoid signal and provides the stable reference signal

PLL has three main components: Phase Detector (PD),

Loop Filter (LF), and Voltage Controlled Oscillator (VCO)

Continuous-time PLL

Received Carrier Signal Loop FilterPD

VCO

Output of VCO=Reference Signal

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Stable Frequency: once the VCO phase is “locked” or

“synchronized” (i.e. phase difference is constant) to the

received signal, its frequency is said to be “locked”

Consider two sinusoids (points) around the unit circle

If the phase difference between the two is constant, then

they move around at the same rate (same frequency ω)

Unit Circle Time-Domain

Ref: Phase Locked Loop PLL Tutorial

ω

Phase

Difference

ω=2πf

https://www.youtube.com/watch?v=U2Tx0hg7y7c

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Continuous-time PLL Basics Stable Frequency: once the VCO phase is “locked” or “synchronized”

(phase difference is constant) to the received signal, its frequency is locked

Stable Phase: minimize the phase error between the received signal

phase 𝜽 𝒕 and the VCO signal phase 𝜽(𝒕) Phase Detector (PD): finds the phase difference (phase error) ,

𝜽𝒆 𝒕 = 𝜽 𝒕 − 𝜽(𝒕) Loop Filter (LF):filters out phase error and produces control voltage v(t)

Voltage Controlled Oscillator (VCO): generates the reference signal

Continuous-time PLL

Received Carrier

Signal

Loop FilterPD

VCO

Reference Signal

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Ideal OperationLoop adjusts the control voltage v(t) of VCO until phase error,

𝜽 𝒕 − 𝜽 𝒕 ~𝟎𝟏) 𝜽 𝒕 > 𝜽 𝒕 :VCO output lags the carrier signal

Loop filter will generate v(t) > 0 so that 𝜽 𝒕 increases

𝟐) 𝜽 𝒕 < 𝜽 𝒕 : VCO output leads the carrier signal

Loop filter will generate v(t) < 0 so that 𝜽 𝒕 decreases

Linear

Region

Phase Error

Function

Phase

Error

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Phase Equivalent Representation

Loop adjusts control voltage of VCO until phase error ~ 0

Phase Detector Loop Filter

VCO

Received

Signal

Phase

Reference

Signal

Phase

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Time and Frequency Domain Representation

Loop adjusts control voltage of VCO until phase error ~ 0

Loop Transfer Function:

𝑯𝒂 𝒔 =𝚯(𝒔)

𝚯(𝒔)=

𝒌𝟎𝒌𝒑𝑭(𝒔)

𝒔 + 𝒌𝟎𝒌𝒑𝑭(𝒔)

Phase Error Transfer Function:

𝑮𝒂 𝒔 =𝚯𝒆(𝒔)

𝚯(𝒔)=

𝒔

𝒔 + 𝒌𝟎𝒌𝒑𝑭(𝒔)Time-Domain Frequency-Domain (Laplace T.)

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Phase Error Transfer Function

Phase Error Transfer Function:

𝑮𝒂 𝒔 =𝚯𝒆(𝒔)

𝚯(𝒔)=

𝒔

𝒔 + 𝒌𝟎𝒌𝒑𝑭(𝒔)

We need to come up with F(s)

or the Loop Filter

Two cases:

Loop Filter is the key

component

Phase Offset (step input) Frequency Offset (ramp input)

Multipath

Delay

L.O.

Frequency

Instability

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Loop Filter, F(s)

Sections C.1.2, C.1.3, C.1.4

The best Loop Filter is Proportional-Plus-Integrator

Phase Lock Frequency Lock

Proportional-

Plus-Integrator

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Loop Filter, F(s)

Sections C.1.2, C.1.3, C.1.4

Loop Filter has p poles, the PLL has p+1 poles

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Loop Filter Characteristics

1) Acquisition Time or Locking Time: time required to make

phase error=0

𝑻𝑳𝑶𝑪𝑲 = 𝑻𝑭𝑳 + 𝑻𝑷𝑳;

𝑻𝑭𝑳 = 𝟒𝚫𝒇𝟐

𝑩𝒏𝟑

𝑻𝑭𝑳 =𝟏. 𝟑

𝑩𝒏

Pull-in Range: 𝚫𝒇𝐩𝐮𝐥𝐥−𝐢𝐧 = 𝟐𝝅 𝟐𝜻 𝑩𝒏

2) Tracking:

Q: How well can the PLL track the carrier signal?

A: Phase error variance

𝝈𝜽𝒆𝟐 =

𝑵𝑶𝑩𝒏

𝑷𝒊𝒏; Pin=Received sig. power with AWGN with noise = No/2

Trade-off: Fast Acquisition and Good Tracking

Frequency Offset

Noise Bandwidth

(or PLL Bandwidth)

Damping Factor

(Ringing)

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Continuous-time PLL with Proportional-Plus-Integrator LF

Time-Domain

Frequency-Domain (Laplace T.)

𝑯𝒂 𝒔 =𝟐𝜻𝝎𝒏𝒔 + 𝝎𝒏

𝟐

𝒔𝟐 + 𝟐𝜻𝝎𝒏𝒔 + 𝝎𝒏𝟐

𝒌𝟎𝒌𝒑𝒌𝟏 = 𝟐𝜻𝝎𝒏; 𝒌𝟎 𝒌𝒑𝒌𝟐 = 𝝎𝒏𝟐

Loop Transfer Function

Loop Constants

Selection of Damping Factor ζ

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Discrete-time PLL with Proportional-Plus-Integrator LF

Time-Domain

Frequency-Domain (Z-Transform)

Loop Transfer Function

Loop Constants

Eq. C.51

Eq. C.61

Direct Digital

Synthesizer (DDS)

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Discrete-time PLL Example (Fig. C.2.4)

Goal: Track Complex Exponential

Design first-order PLL and second-order PLL

Follow Dr. Rice’s PLL Exercise

Time-domain

Phase Error

Phase

http://ricesimulink.groups.et.byu.net/pll.phtml

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Assignment 7 [10]

Simulate 1st order and 2nd order discrete-time PLLs [10]

Submit the following:

1) Simulink Model

2) Phase error plots

3) Time-domain plots

lecture 11 phase locked loop (pll): appendix...

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