lecture 1: introduction - university of pittsburghkmram/1192-2192/lectures/introduction.pdflecture...
TRANSCRIPT
Introduction to
CMOS VLSI
Design
Lecture 1: Introduction
David Harris, Harvey Mudd College
Kartik Mohanram and Steven Levitan
University of Pittsburgh
CMOS VLSI Design0: Introduction Slide 2
Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): very many
Complementary Metal Oxide Semiconductor
– Fast, cheap, low power transistors
Today: How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
Steven Levitan 19-Nov-2007 3
0: Introduction 3
Deconstructing a Computer System
http://www.westchiltington.com/images/computer_dell.jpg
Steven Levitan 19-Nov-2007 4
0: Introduction 4
Deconstructing a Computer System
http://www.computerdust.com/images/cpu-clean-dell-computer.jpg
Steven Levitan 19-Nov-2007 5
0: Introduction 5
Deconstructing a Computer System
http://www.greenpeace.org.uk/files/images/migrated/MultimediaFiles/Live/Image/7781.jpg
Steven Levitan 19-Nov-2007 6
0: Introduction 6
Deconstructing a Computer System
http://freespace.virgin.net/george.gdingwall/images/Circuit-Board_06.jpg
Steven Levitan 19-Nov-2007 7
0: Introduction 7
Deconstructing a Computer System
http://members.tripod.com/~ComputerLab/chip.jpg
Steven Levitan 19-Nov-2007 8
0: Introduction 8
From Chips to DIPs
Single die
Wafer
From http://www.amd.com
Slicing and Dicing
Steven Levitan 19-Nov-2007 9
0: Introduction 9http://eazyvg.wordpress.com/2007/03/07/barcelona-first-native-quad-core-processor/
Quad Core Barcelona 2007
Going Back and Zooming In
Steven Levitan 19-Nov-2007 10
0: Introduction 10
Going Back and Zooming In
http://www-vlsi.stanford.edu/group/chips_micropro.html
2002 - 221M Transistors 421mm2
Steven Levitan 19-Nov-2007 11
0: Introduction 11
Going Back and Zooming In
http://www-vlsi.stanford.edu/group/chips_micropro.html
1998 Pentium(II) 7.5M Transistors 118mm2
Steven Levitan 19-Nov-2007 12
0: Introduction 12
Going Back and Zooming In
http://www-vlsi.stanford.edu/group/chips_micropro.html
1989 275K Transistors 80386 46mm2
Steven Levitan 19-Nov-2007 13
0: Introduction 13
Going Back and Zooming In
http://www-vlsi.stanford.edu/group/chips_micropro.html
1971 2K Transistor 4004 12mm2
Steven Levitan 19-Nov-2007 14
0: Introduction 14
Going Back and Zooming In
ECL 3-input Gate Motorola 1966
© Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed
Steven Levitan 19-Nov-2007 15
0: Introduction 15
Photomasks to Circuits
0: IntroductionWeste & Harris CMOS VLSI Design Copyright © 2005 Pearson Addison-Wesley. All
rights reserved.
© Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed
Steven Levitan 19-Nov-2007 16
0: Introduction 16
The “Y” Abstraction Spiral
Gajski & Kuhn
End Here
Start Here
Steven Levitan 19-Nov-2007 17
0: Introduction 17
MOS Technology
10umhttp://www.semiconductorblog.com
0.6 um
GATE
© Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed
Steven Levitan 19-Nov-2007 18
0: Introduction 18
Patterned Materials Create Circuits
Silicon Crystal
N type Doping P type Doping0: IntroductionWeste & Harris CMOS VLSI Design Copyright © 2005 Pearson Addison-Wesley. All
rights reserved.
CMOS VLSI Design0: Introduction Slide 19
Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
Si SiSi
Si SiSi
Si SiSi
CMOS VLSI Design0: Introduction Slide 20
Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
As SiSi
Si SiSi
Si SiSi
B SiSi
Si SiSi
Si SiSi
-
+
+
-
CMOS VLSI Design0: Introduction Slide 21
p-n Junctions
A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction
p-type n-type
anode cathode
CMOS VLSI Design0: Introduction Slide 22
nMOS Transistor
Four terminals: gate, source, drain, body
Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
– Even though gate is
no longer made of metal
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
CMOS VLSI Design0: Introduction Slide 23
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
0
S
CMOS VLSI Design0: Introduction Slide 24
nMOS Operation Cont.
When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
n+
p
GateSource Drain
bulk Si
SiO2
Polysilicon
n+
D
1
S
CMOS VLSI Design0: Introduction Slide 25
pMOS Transistor
Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
SiO2
n
GateSource Drain
bulk Si
Polysilicon
p+ p+
CMOS VLSI Design0: Introduction Slide 26
Power Supply Voltage
GND = 0 V
In 1980’s, VDD = 5V
VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
CMOS VLSI Design0: Introduction Slide 27
Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFFON
ONOFF
Steven Levitan 19-Nov-2007 28
0: Introduction 28
Transistors as Switches
Input voltage on the CMOS
gate controls the current
through the source/drain
path
This provides output
voltage to drive next
circuit.
Series / Parallel paths
provide “and” and “or”
logic functions
GS
D
N Switch
GS
D
N Switch
GS
D
GS
D
Steven Levitan 19-Nov-2007 29
0: Introduction 29
From Switches to Boolean Functions...
Use the switching functions to provide paths to Vdd or GND
Vdd is the source of all Truth (Vdd = = 1)
GND is the source of all Falsehood (GND == 0)
P-channel N-channel
0
0
1
1
Steven Levitan 19-Nov-2007 30
0: Introduction 30
The Inverter
True to False / False to True Converter
1/0 0/1
CMOS VLSI Design0: Introduction Slide 31
CMOS Inverter
A Y
0
1
VDD
A Y
GNDA Y
CMOS VLSI Design0: Introduction Slide 32
CMOS Inverter
A Y
0
1 0
VDD
A=1 Y=0
GND
ON
OFF
A Y
CMOS VLSI Design0: Introduction Slide 33
CMOS Inverter
A Y
0 1
1 0
VDD
A=0 Y=1
GND
OFF
ON
A Y
Steven Levitan 19-Nov-2007 34
0: Introduction 34
Series/Parallel Circuits => Logic
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
CMOS NAND (not AND) Gate
A
BY
Truth TableY = A•B = A + B
+Vdd
CMOS VLSI Design0: Introduction Slide 35
CMOS NAND Gate
A B Y
0 0
0 1
1 0
1 1
A
B
Y
CMOS VLSI Design0: Introduction Slide 36
CMOS NAND Gate
A B Y
0 0 1
0 1
1 0
1 1
A=0
B=0
Y=1
OFF
ON ON
OFF
CMOS VLSI Design0: Introduction Slide 37
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0
1 1
A=0
B=1
Y=1
OFF
OFF ON
ON
CMOS VLSI Design0: Introduction Slide 38
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1
A=1
B=0
Y=1
ON
ON OFF
OFF
CMOS VLSI Design0: Introduction Slide 39
CMOS NAND Gate
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
A=1
B=1
Y=0
ON
OFF OFF
ON
CMOS VLSI Design0: Introduction Slide 40
CMOS NOR Gate
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
A
BY
CMOS VLSI Design0: Introduction Slide 41
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
CMOS VLSI Design0: Introduction Slide 42
3-input NAND Gate
Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0
A
B
Y
C
Steven Levitan 19-Nov-2007 43
0: Introduction 43
From Logic to Binary Math
Truth tables for binary addition/subtraction etc.
A 0 1 0 1
B 0 0 1 1
Sum 0 1 1 0
Carry 0 0 0 1
Sum = A xor B
Carry = A and B
Are these Amino Acids?
A
B
Carry
SumXOR
AND
Steven Levitan 19-Nov-2007 44
0: Introduction 44
F = ^(AB + AC + BC) => Carry
10 1
+ 0 11 0
C =A =B =
Cout
Steven Levitan 19-Nov-2007 45
0: Introduction 45
Chip Photomask “Layout”
Steven Levitan 19-Nov-2007 46
0: Introduction 46
Latches for State
Cross coupled, charge storage, etc. Save logic values, change under temporal control
(clocks)
Set
Reset Q
QB
Are these (folded) proteins?
S R Q QB
0 0 Q QB
0 1 0 1
1 0 1 0
1 1 0 0
hold
Illegal
Inputs Outputs
Latch Control (Clock)
DATANDATAN+1
Steven Levitan 19-Nov-2007 47
0: Introduction 47
Finite State Machines
FSM’s capture processes
Inputs, outputs, state
Out = F((in), Staten)
Staten+1 = F(in, Staten)
Like a “Markov process”
S1
S2
S5
S3
If (state = 1) and (input = A) then state <= 4, output <= 15
Current State Latch
Next State
&
Output Calculation
Input
Output
Is this a
regulatory process?
Steven Levitan 19-Nov-2007 48
0: Introduction 48
(Re) Composing …
Steven Levitan 19-Nov-2007 49
0: Introduction 49
Computer Micro-Architecture
Basic operation on “triples”
A <= B + C;
R[2] <= R[1] op R[0]
1. Data from Register File
2. Operations done by Arithmetic
and Logic Unit
3. Data returned to Register File
Op ={add, sub, shift, and, or, etc}
CC = {zero, neg, overflow, etc}
Register File
ALU
SRC1SRC2DEST
Op
Instr
uction R
egis
ter
CC
Steven Levitan 19-Nov-2007 50
0: Introduction 50
Instruction Set
OP Code Src1 Src2 Destination
Op Code Memory Address
Three (four) types of instructions:1. Move Data – to / from Memory locations, I/O and temporary registers
2. Compute – Logical, fixed point, floating point, string, bits
3. Program Flow – Branch, Jump, Subroutines
4. Mode Control – Privileged modes, interrupts, memory mapping
Four addresses (explicit/implicit)Source1, Source2, Destination, Next (PC)
B+C => A (and do next instruction)
Instruction set and micro-architecture
define the complete computing system
Steven Levitan 19-Nov-2007 51
0: Introduction 51
von Neumann Architecture
Memory
Accumulator
PC IR
MBRMAR
Control
CPUI/O
Fetch/Execute Cycle MAR <- PC MBR <- MEM[MAR] Increment PC IR <- MBR Interpret instruction in IR
(now called “5-stage pipeline”)
Done as a FSM in “Control Unit” Is this just like EIS.. Is this a ribosome?
CMOS VLSI Design0: Introduction Slide 52
Summary
MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start
designing schematics and layout for a simple chip!