lecture 1
DESCRIPTION
Lecture 1TRANSCRIPT
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 1
ECE2072/TRC2300/TEC2172 Digital Systems:Combinational Logic Technologies
based on textbook
Contemporary Logic Design, 2nd Editionby R. H. Katz and G. Borriello
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IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 2
ECE2072/TRC2300: Combinational Logic Technologies Summary (Katz2e Ch4)
Standard gatesgate packagescell libraries
Regular logicmultiplexersdecoders
Two-level programmable logicPALsPLAsROMs
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 3
Fixed/Random logic (Sec4.2.1 Katz2e)
Transistors quickly integrated into logic gates (1960s)Catalog of common gates (1970s)
Texas Instruments Logic Data Book – the yellow bibleall common packages listed and characterized (delays, power)typical packages:
in 14-pin IC: 6-inverters, 4 NAND gates, 4 XOR gates
Today, very few parts are still in useHowever, parts libraries exist for chip design
designers reuse already characterized logic gates on chipssame reasons as beforedifference is that the parts don’t exist in physical inventory –created as needed
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 4
Fixed/Random logic
Too hard to figure out exactly what gates to usemap from logic to NAND/NOR networksdetermine minimum number of packages
slight changes to logic function could decrease cost
Changes difficult to realizeneed to rewire partsmay need new partsdesign with spares (few extra inverters and gates on every board)
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 5
Regular logic (eg. Multiplexers/decoders, ROMs, PLAs/PALs etc)
Need to make design fasterNeed to make engineering changes easier to makeSimpler for designers to understand and map to functionality
harder to think in terms of specific gatesbetter to think in terms of a large multi-purpose block
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 6
multiplexer demultiplexer 4x4 switch
control control
Making connections (Sec4.2.2 Katz Ed2)
Direct point-to-point connections between gateswires we've seen so far
Route one of many inputs to a single output --- multiplexerRoute a single input to one of many outputs --- demultiplexer
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 7
Mux and demux
Switch implementation of multiplexers and demultiplexers
can be composed to make arbitrary size switching networksused to implement multiple-source/multiple-destination interconnections
A
B
Y
Z
A
B
Y
Z
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 8
multiple input sources
multiple output destinations
MUX
A B
Sum
Ss
Sa Sb
B0
MUX
DEMUX
Mux and demux (cont'd)
Uses of multiplexers/demultiplexers in multi-point connections
B1A0 A1
S0 S1
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 9
two alternative formsfor a 2:1 Mux truth table
functional form
logical form
A Z0 I01 I1
I1 I0 A Z0 0 0 00 0 1 00 1 0 10 1 1 01 0 0 01 0 1 11 1 0 11 1 1 1
Z = A' I0 + A I1
Multiplexers/selectors: general concept2n data inputs, n control inputs (called "selects"), 1 outputused to connect 2n points to a single pointcontrol signal pattern forms binary index of input connected to output
Multiplexers/selectors
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 10
2 -1I0I1I2I3I4I5I6I7
A B C
8:1mux
Z
I0I1I2I3
A B
4:1mux
ZI0I1
A
2:1mux Z
k=0
n
2:1 mux: Z = A'I0 + AI14:1 mux: Z = A'B'I0 + A'BI1 + AB'I2 + ABI38:1 mux: Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +
AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
In general: Z = Σ (mkIk)
in minterm shorthand form for a 2n:1 Mux
Multiplexers/selectors (cont'd)
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 11
Gate level implementation of muxes
2:1 mux
4:1 mux
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 12
control signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7
control signal A chooses which of theupper or lower mux's output to gate to Z
alternativeimplementation
C
Z
A B
4:1mux
2:1mux
2:1mux
2:1mux
2:1mux
I4I5
I2I3
I0I1
I6I7
8:1mux
Large multiplexers can be made by cascading smaller ones
Z
I0I1I2I3
Cascading multiplexers
A
I4I5I6I7
B C
4:1mux
4:1mux
2:1mux
8:1mux
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 13
Multiplexers as general-purpose logic
A 2n:1 multiplexer can implement any function of n variableswith the variables used as control inputs andthe data inputs tied to 0 or 1in essence, a lookup table
Example:F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC= A'B'C'(1) + A'B'C(0)
+ A'BC'(1) + A'BC(0) + AB'C'(0) + AB'C(0) + ABC'(1) + ABC(1)
Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
CA B
01234567S2
8:1 MUX
S1 S0
Z
10100011
F
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A B C F0 0 0 10 0 1 00 1 0 10 1 1 01 0 0 01 0 1 01 1 0 11 1 1 1
C'
C'
0
1 A B
S1 S0
F0123
4:1 MUX
C'C'01
F
CA B
01234567
10100011
S2
8:1 MUX
S1 S0
Multiplexers as general-purpose logic (Ex4.1)
A 2n-1:1 multiplexer can implement any function of n variableswith n-1 variables used as control inputs andthe data inputs tied to the last variable or its complement
Example:F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC= A'B'(C') + A'B(C') + AB'(0) + AB(1)
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 15
n-1 mux control variables
single mux data variable
four possibleconfigurationsof truth tablerows can beexpressed asa function of In
I0 I1 . . . In-1 In F
. . . . 0 0 0 1 1
. . . . 1 0 1 0 1
0 In In' 1
Multiplexers as general-purpose logic (cont’d)(Ex4.2 Katz Ed2)
Generalization
Example: G(A,B,C,D)can be realizedby an 8:1 MUX
choose A,B,C as control variables
01234567
1D01D’DD’D’
S2
8:1 MUX
S1 S0
CA B
A B C D G0 0 0 0 10 0 0 1 10 0 1 0 00 0 1 1 10 1 0 0 00 1 0 1 00 1 1 0 10 1 1 1 11 0 0 0 11 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 11 1 0 1 0
1
D
0
1
D'
D
D’
1 1 1 0 11 1 1 1 0
D’
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 16
Activity
Realize F = B’CD’ + ABC’ with a 4:1 multiplexer and a minimum of other gates:
A B C D Z0 0 0 0 00 0 0 1 00 0 1 0 10 0 1 1 00 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 01 1 0 0 11 1 0 1 11 1 1 0 01 1 1 1 0
0 when B’C’
D’ when B’C
A when BC’
0 when BC
Z = B’C’(0) + B’C(D’) + BC’(A) + BC(0)
B C
S1 S0
F0123
4:1 MUX
0D’A0
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1:2 Decoder:O0 = G • S’O1 = G • S
2:4 Decoder: O0 = G • S1’ • S0’O1 = G • S1’ • S0O2 = G • S1 • S0’O3 = G • S1 • S0
3:8 Decoder: O0 = G • S2’ • S1’ • S0’O1 = G • S2’ • S1’ • S0O2 = G • S2’ • S1 • S0’O3 = G • S2’ • S1 • S0O4 = G • S2 • S1’ • S0’O5 = G • S2 • S1’ • S0O6 = G • S2 • S1 • S0’O7 = G • S2 • S1 • S0
Demultiplexers/decoders (Sec4.2.3 Katz Ed2)
Decoders/demultiplexers: general conceptsingle data input, n control inputs, 2n outputscontrol inputs (called “selects” (S)) represent binary index of output to which the input is connecteddata input usually called “enable” (G)
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 18
active-high enable
active-low enable
active-high enable
active-low enable
O0G
S
O1
O0\G
S
O1
S1
O2
O3
O0G
O1
S0 S1
O2
O3
O0\G
O1
S0
Gate level implementation of demultiplexers
1:2 decoders
2:4 decoders
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 19
demultiplexer generates appropriateminterm based on control signals
(it "decodes" control signals)
Demultiplexers as general-purpose logic
A n:2n decoder can implement any function of n variableswith the variables used as control inputsthe enable inputs tied to 1 andthe appropriate minterms summed to form the function
A'B'C'A'B'CA'BC'A'BCAB'C'AB'CABC'ABC
CA B
01234567
S2
3:8 DEC
S1 S0
“1”
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 20
F1
F2
F3
F1 = A'BC'D + A'B'CD + ABCDF2 = ABC'D' + ABCF3 = (A' + B' + C' + D')
A B
0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD12 ABC'D'13 ABC'D14 ABCD'15 ABCD
4:16DECEnable
Demultiplexers as general-purpose logic (cont’d)(Ex4.6 Katz Ed2)
C D
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 21
0 A'B'C'D'E'1234567
S2
3:8 DEC
S1 S0
A B
0123S1
2:4 DEC
S0
F
012 A'BC'DE'34567
S2
3:8 DEC
S1 S0
EC D
0 AB'C'D'E'1234567 AB'CDE
Cascading decoders
5:32 decoder1x2:4 decoder4x3:8 decoders
3:8 DEC
01234567 ABCDE
EC D
S2 S1 S0 S2
3:8 DEC
S1 S0
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 22
• • •
inputs
ANDarray
• • •
outputs
ORarrayproduct
terms
Programmable logic arrays (Sec4.2.3 Katz Ed2)
Pre-fabricated building block of many AND/OR gatesactually NOR or NAND"personalized" by making/breaking connections among the gatesprogrammable array block diagram for sum of products form
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 23
example:F0 = A + B' C'F1 = A C' + A BF2 = B' C' + A BF3 = B' C + A
personality matrix 1 = uncomplemented in term0 = complemented in term– = does not participate
1 = term connected to output0 = no connection to output
input side:
output side:
product inputs outputsterm A B C F0 F1 F2 F3
AB 1 1 – 0 1 1 0B'C – 0 1 0 0 0 1AC' 1 – 0 0 1 0 0B'C' – 0 0 1 0 1 0A 1 – – 1 0 0 1
reuse of terms
Enabling concept (Ex4.7 Katz Ed2)
Shared product terms among outputs
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 24
Before programming
All possible connections are available before "programming"in reality, all AND and OR gates are NANDs
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 25
A B C
F1 F2 F3F0
AB
B'C
AC'
B'C'
A
Unwanted connections are "blown"fuse (normally connected, break unwanted ones)anti-fuse (normally disconnected, make wanted connections)
After programming
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 26
notation for implementingF0 = A B + A' B'F1 = C D' + C' D
AB+A'B'CD'+C'D
AB
A'B'
CD'
C'D
A B C D
Short-hand notation so we don't have to draw all the wiressignifies a connection is present and perpendicular signal is an
input to gate
Alternate representation for high fan-in structures
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 27
A B C F1 F2 F3 F4 F5 F60 0 0 0 0 1 1 0 00 0 1 0 1 0 1 1 10 1 0 0 1 0 1 1 10 1 1 0 1 0 1 0 01 0 0 0 1 0 1 1 11 0 1 0 1 0 1 0 01 1 0 0 1 0 1 0 01 1 1 1 1 0 0 1 1
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC
A B C
F1 F2 F3 F4 F5F6
full decoder as for memory address
bits stored in memory
Programmable logic array example (Ex4.8 Katz Ed2)
Multiple functions of A, B, CF1 = A B CF2 = A + B + CF3 = A' B' C'F4 = A' + B' + C'F5 = A xor B xor CF6 = A xnor B xnor C
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 28
a given column of the OR array has access to only a subset of
the possible product terms
PALs and PLAs
Programmable logic array (PLA)what we've seen so farunconstrained fully-general AND and OR arrays
Programmable array logic (PAL)constrained topology of the OR arrayinnovation by Monolithic Memoriesfaster and smaller OR plane
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 29
minimized functions:
W = A + BD + BCX = BC'Y = B + CZ = A'B'C'D + BCD + AD' + B'CD'
A B C D W X Y Z0 0 0 0 0 0 0 00 0 0 1 0 0 0 10 0 1 0 0 0 1 10 0 1 1 0 0 1 00 1 0 0 0 1 1 00 1 0 1 1 1 1 00 1 1 0 1 0 1 00 1 1 1 1 0 1 11 0 0 0 1 0 0 11 0 0 1 1 0 0 01 0 1 – – – – –1 1 – – – – – –
PALs and PLAs: design example
BCD to Gray code converter
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 30
not a particularly goodcandidate for PAL/PLA
implementation since no terms are shared among outputs
however, much more compact and regular implementation
when compared with discrete AND and OR gates
A B C D
minimized functions:
W = A + BD + BCX = B C'Y = B + CZ = A'B'C'D + BCD + AD' + B'CD'
Code converter: programmed PLA
A
BD
BC
BC'
B
C
A'B'C'D
BCD
AD'
BCD'
PALs and PLAs: design example (cont’d)
W X Y Z
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4 product terms per each OR gate
A
BD
BC
0
BC'
0
0
0
B
C
0
0
A'B'C'D
BCD
AD'
B'CD'
W X Y Z
A B C D
PALs and PLAs: design example (cont’d)
Code converter: programmed PAL
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 32
W
X
Y
Z
B
B
B
B
B
B
\BC
C
C
C
CA
AA
D
D
D
\D
\D
PALs and PLAs: design example (cont’d)
Code converter: NAND gate implementationloss or regularity, harder to understandharder to make changes
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 33
EQ NE LT GT
A'B'C'D'
A'BC'D
ABCD
AB'CD'
AC'
A'C
B'D
BD'
A'B'D
B'CD
ABC
BC'D'
A B C D
Magnitude comparatorA B C D EQ NE LT GT0 0 0 0 1 0 0 00 0 0 1 0 1 1 00 0 1 0 0 1 1 00 0 1 1 0 1 1 00 1 0 0 0 1 0 10 1 0 1 1 0 0 00 1 1 0 0 1 1 00 1 1 1 0 1 1 01 0 0 0 0 1 0 11 0 0 1 0 1 0 11 0 1 0 1 0 0 01 0 1 1 0 1 1 01 1 0 0 0 1 0 11 1 0 1 0 1 0 11 1 1 0 0 1 0 11 1 1 1 1 0 0 0
PALs and PLAs: another design example (Ex4.10 Katz Ed2)
minimized functions:EQ = A’B’C’D’ + A’BC’D + ABCD + AB’CD’ NE = AC’ + A’C + B’D + BD’LT = A’C + A’B’D + B’CD GT = AC’ + ABC + BC’D’
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 34
Activity
Map the following functions to the PLA below:W = AB + A’C’ + BC’X = ABC + AB’ + A’BY = ABC’ + BC + B’C’
A B C
W X Y
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 35
Activity (cont’d)
9 terms won’t fit in a 7 term PLAcan apply concensus theoremto W to simplify to:W = AB + A’C’
8 terms wont’ fit in a 7 term PLAobserve that AB = ABC + ABC’can rewrite W to reuse terms:W = ABC + ABC’ + A’C’
Now it fitsW = ABC + ABC’ + A’C’X = ABC + AB’ + A’BY = ABC’ + BC + B’C’
This is called technology mappingmanipulating logic functionsso that they can use available resources
ABC
ABC’
A’C’
AB’
A’B
BC
B’C’
A B C
W X Y
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 36
decoder
0 n-1
Address
2 -1n
0
1 1 1 1
word[i] = 0011
word[j] = 1010
bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches)
j
i
internal organization
word lines (only one is active – decoder is just right for this)
Read-only memories (Sec4.2.2 Katz Ed2)
Two dimensional array of 1s and 0sentry (row) is called a "word"width of row = word-sizeindex is called an "address"address is inputselected word is output
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 37
F0 = A' B' C + A B' C' + A B' C
F1 = A' B' C + A' B C' + A B C
F2 = A' B' C' + A' B' C + A B' C'
F3 = A' B C + A B' C' + A B C'
truth table
A B C F0 F1 F2 F30 0 0 0 0 1 00 0 1 1 1 1 00 1 0 0 1 0 00 1 1 0 0 0 11 0 0 1 0 1 11 0 1 1 0 0 01 1 0 0 0 0 11 1 1 0 1 0 0
block diagram
ROM8 words x 4 bits/word
address outputsA B C F0F1F2F3
ROMs and combinational logic
Combinational logic implementation (two-level canonical form) using a ROM
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 38
ROM structure
Similar to a PLA structure but with a fully decoded AND arraycompletely flexible OR array (unlike PAL)
n address lines
• • •
inputs
decoder 2n wordlines
• • •
outputs
memoryarray
(2n wordsby m bits)
m data lines
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 39
ROM vs. PLA
ROM approach advantageous whendesign time is short (no need to minimize output functions)most input combinations are needed (e.g., code converters)little sharing of product terms among output functions
ROM problemssize doubles for each additional inputcan't exploit don't cares
PLA approach advantageous whendesign tools are available for multi-output minimizationthere are relatively few unique minterm combinationsmany minterms are shared among the output functions
PAL problemsconstrained fan-ins on OR plane
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 40
Regular logic structures for two-level logic
ROM – full AND plane, general OR planecheap (high-volume component)can implement any function of n inputsmedium speed
PAL – programmable AND plane, fixed OR planeintermediate costcan implement functions limited by number of termshigh speed (only one programmable plane that is much smaller than ROM's decoder)
PLA – programmable AND and OR planesmost expensive (most complex in design, need more sophisticated tools)can implement any function up to a product term limitslow (two programmable planes)
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Multi-level logic:Field-Programmable Gate Array (FPGA)
Combines density advantage of gate array with rapid programmability of PAL/PLABasic components:
Logic Cell - can be programmed to implement any function of up to five inputs (Xilinx)Wiring channels - programmable connections between cellsIO Cells - interface to external signals at edge of array
Usually programmed using CAD (eg. Verilog) synthesizer for optimal layout on target platformModern FPGA may contain over 10,000 logic cells, equivalent to several million simple logic gatesDue to high flexibility, FPGAs are now one of the most popular logic technologies
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 42
Actel FPGA ArchitectureOnce-programmable using anti-fuse technologyLogic cell can implement all 1, 2-input functions, 223 3-input functions and many other 4 to 8 input functions
horizontalwiring tracks
row of logic cells
IO buffers,programmingand test logic
2:1MUX
2:1MUX
2:1MUX
D0
D1
D2
D3
Y
S0 S1S0A
S0B
Logic Cell structure
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 43
Xilinx FPGA ArchitectureMust be reprogrammed on each power-upEach CFB implements a 5-input function, or two 4-input functions
wiring channels
logiccell
IO Buffers
D QMUX
S
Y4-inputLUT
Combinational Function Block (CFB) structure
(simplified)
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 44
Xilinx FPGA
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 45
A
OE
F
100
Tri-State Outputs (Sec4.4.1 Katz Ed2)Logic States: "0", "1"Don't Care/Don't Know State: "X" (must be some value in real circuit!)
Third State: "Z" — high impedance — infinite resistance, no connectionTri-state gates: output values are "0", "1", and "Z"
additional input: output enable (OE)
The Third State
When OE is high, this gate is a non-inverting "buffer"
When OE is low, it is as though the gate was disconnected from the output!
This allows more than one gate to be connected to thesame output wire, as long as only one has itsoutput enabled at the same time
Non-inverting buffer'stiming waveform
"Z" "Z"
AX01
OE011
FZ01
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Tri-state OutputsUsing tri-state gates to implement an economical multiplexer:
When SelectInput is asserted highInput1 is connected to F
When SelectInput is driven lowInput0 is connected to F
This is essentially a 2:1 Mux
OE
OE
Input 0
Input 1
SelectInput
F
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 47
Tri-state OutputsAlternative Tri-state Fragment
Active low tri-state enablesplus inverting tri-state buffers
Switch Level Implementationof tri-state gate
Input 0
Input 1
SelectInput
OE
OE
F
F I
OE
1
0
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Tri-State Outputs4:1 Multiplexer, Revisited
Decoder + 4 tri-state Gates
1G
1B1A
1Y11Y0
1Y31Y2139
2G
2B2A 2Y1
2Y0
2Y32Y2
S1 S0
\EN
D3
D2
D1
D0
1
32
15
1314
76549
101112
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 49
+5 V
F
A B
0 V
Open-collector NAND gate
Pull-up resistor
Open Collector Outputs (Sec4.4.2 Katz Ed2)Open Collector
another way to connect multiple gates to the same output wire
gate only has the ability to pull its output low; it cannot activelydrive the wire high
this is done by pulling the wire up to a logic 1 voltage through a resistor
Wired AND:If A and B are "1", output is actively pulled lowif C and D are "1", output is actively pulled lowif one gate is low, the other high, then low winsif both gates are "1", the output floats, pulled
high by resistorHence, the two NAND functions are AND'd
together! (by O/C outputs and wire)
OC NAND gates
ABCD
F
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Open Collector Outputs4:1 Multiplexer
+5VG
BA
Y1Y0
Y3Y2139
\I3
6
\I2
5
\I1
4
\I0
F
7
2S03S1
1\EN
OR
OR
OR
OR
Decoder + 4 Open Collector Gates
IV - Combinational Logic Technologies © Copyright 2004, Gaetano Borriello and Randy H. Katz 51
Combinational logic technology summaryRandom logic
Single gates or in groupsconversion to NAND-NAND and NOR-NOR networkstransition from simple gates to more complex gate building blocksreduced gate count, fan-ins, potentially fastermore levels, harder to design
Time response in combinational networksgate delays and timing waveformshazards/glitches (what they are and why they happen)
Regular logicmultiplexers/decodersROMsPLAs/PALsFPGAs
Non-gate logicTri-state outputsOpen-collector outputs