lect4-p-t-logic

8/7/2019 Lect4-P-T-Logic

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Dynamic andDynamic and

PassPass--TransistorTransistorLogicLogic

Prof. Vojin G. OklobdzijaProf. Vojin G. Oklobdzija

ReferencesReferences (used for creation of the presentation material):(used for creation of the presentation material):1.1. Masaki,Masaki, DeepDeep--SubmicronCMOSWarmsUptoHighSubmicronCMOSWarmsUptoHigh--SpeedLogicSpeedLogic ,, IEEEIEEE

CircuitsandDevicesMagazine, November1992.CircuitsandDevicesMagazine, November1992.2.2. Krambeck, C.M. Lee, H.S. Law,Krambeck, C.M. Lee, H.S. Law,HighHigh--SpeedCompact CircuitswithCMOSSpeedCompact CircuitswithCMOS ,,

IEEE Journal of SolidIEEE Journal of Solid--StateCircuits, Vol. SCStateCircuits, Vol. SC--13, No3, June1982.13, No3, June1982.3.3. V.G. Oklobdzija, R.K. Montoye,V.G. Oklobdzija, R.K. Montoye,DesignDesign--PerformanceTradePerformanceTrade--OffsinCMOSOffsinCMOS--DominoLogicDominoLogic ,IEEE Journal of Solid,IEEE Journal of Solid--StateCircuits, Vol. SCStateCircuits, Vol. SC--21, No2, April21, No2, April1986.1986.


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Fall 2004 Prof. V. G. Oklobdzija: High-Performance System Design 2

References:References:

4. Goncalves, H.J. DeMan, NORA: A Racefree Dynamic CMOSTechnique for PipelinedLogic Structures , IEEE Journal of Solid-StateCircuits, Vol. SC-18, No3, June1983.

5. L.G. H eller, et al, Cascode Voltage Switch Logic: A DifferentialCMOS Logic Family, in 1984 Digest of Technical Papers, IEEE

International Solid-StateCircuitsConference, February 1984.6. L.C.M.G. Pfennings, etal, Differential Split-LevelCMOSLogic for

Subnanosecond Speeds , IEEE Journal of Solid-State Circuits,Vol. SC-20, No5, October1985.

7. K.M. C hu, D.L. Pulfrey, "A Comparison ofCMOSCircuit Techniques:Differential Cascode Voltage Switch Logic Versus Conventional

Logic", IEEE Jouirnal of Solid-State Circuits, Vol. SC-22, No.4,August 1987.


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References:References:Pass-Transistor Logic:

8. S. Whitaker, Pass-transistor ne tworks optimize n-MOSlogic , Electronics, September1983.

9. K. Yano, et al, A 3.8-ns CMOS 16x16-b Multiplier UsingComplementary Pass-Transistor Logic , IEEE Journal of Solid-StateCircuits, Vol. 25, No2, April1990.

10. K. Yano, etal, Lean Integration: Achieving a Quantum Leap inPerformance and Cost of Logic LSIs", Proceedings of theCustom Integrated Circuits Conference, San Diego, California,May 1-4, 1994.

11. M. Suzuki, et al, A 1.5ns 32b C MOS ALU in Double Pass-Transistor Logic , Journal of Solid-State Circuits, Vol. 28. No11, November1993.

12. N. Ohkubo, et al, A 4.4-ns CMOS 54x54-b Multiplier UsingPass-transistor Multiplexer , Proceedings of the CustomIntegrated Circuits Conference, San Diego, California, May 1-4, 1994.


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References:References:

13. V. G. Oklobdzija and B. Duchne, Pass-Transistor Dual ValueLogic For Low-Power CMOS, Proceedings of the 1995International Symposium on VLSI Technology, Taipei, Taiwan,May 31-June 2nd, 1995.

14. F.S. Lai, W. Hwang, Differential Cascode Voltage Switch with

the Pass-Gate (DCVSPG) Logic Tree for High PerformanceCMOS Digital Systems, Proceedings of the 1993 InternationalSymposium on VLSI Technology, Taipei, Taiwan, June 2-4, 1995

15. A. Parameswar, H. Hara, T. Sakurai, A Swing Restored Pass-Transistor Logic Based Multiply and Accumulate Circuit forMultimedia Applications, Proceedings of the Custom IntegratedCircuits Conference, San Diego, California, May 1-4, 1994.

16. T. Fuse, et al, 0.5V SOI CMOS Pass-Gate Logic, Digest ofTechnical Papers, 1996 IEEEInternational Solid-State CircuitsConference, San Francisco February 8, 1996.


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PassPass--Transistor LogicTransistor Logic


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(a) XOR function implemented with pass-transistor circuit(b) Karnaough map showing derivation of the XOR function

(a) (b)


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B

B

B

B

B

A

BA

BA

BA

BA

BA

BA

BA

BA

General topology of pass-

transistor function generator

Karnaough map of 16 possiblefunctions that can be realized


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Function generator

implemented with pass-transistor logic


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Voltage drop does notexceed Vth when thereare multiple transistors inthe path

Threshold voltage drop atthe output of the pass-transistor gate


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Elimination of the threshold voltage drop by:(a) pairing nMOS transistor with a pMOS(b) using a swing-restoring inverter


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Complementary PassComplementary Pass--TransistorTransistorLogic (CPL)Logic (CPL)


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Basic logic functions in CPLBasic logic functions in CPLA ABB

B

B

A ABB

B

B

A B

A B

A A

B

B

A A

A ABB

C

C

A B

A C B C


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CPL LogicCPL Logic

AA

S S

A A

B

B

C

C

SS(a) (b)

B

B

Q Qb

n1 n2

n4n3

CPL provides an efficient implementation of XOR function

XOR gateSum circuit


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CPL InverterCPL Inverter


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Double PassDouble Pass--Transistor Logic (DPL):Transistor Logic (DPL):

A

B

A B B A

VDD

B

A

OO

A B

A

B

A B BA

B

A

OO

B

A

B A B A

B

A

A B

XOR/XNOR

AND/NAND


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XOR

One bit full-adder:Sum circuit


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The critical path traverses twotransistors only(not counting the buffer)

DPL Full Adder


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Formal Method for CPL LogicFormal Method for CPL Logic

DerivationDerivationMarkovic et al. 2000Markovic et al. 2000

(a)Cover the Karnaugh-map with largest possible cubes

(overlapping allowed)(b)Express the value of the function in each cube in

terms of input signals

(c) Assign one branch of transistor(s)to each of the

cubes and connect all the branches to one commonnode, which is the output of NMOS pass-transistornetwork


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Formal Method for PFormal Method for P--T LogicT LogicDerivationDerivation

Complementary function can be implemented from the samecircuit structure by applying complementarity principle:

Complementarity Principle: Using the same circuittopology, with pass signals inverted, complementary logicfunction is constructed in CPL.

By applying duality principle, a dual function is synthesized:

Duality Principle: Using the same circuittopology, with

gate signals inverted, dual logic function is constructed.Following pairs of basic functions are dual:

AND-OR (and vice-versa)NAND-NOR (and vice-versa)

XOR and XNOR are self-dual (dual to itself)


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Derivation of PDerivation of P--T LogicT Logic

0 0

0 1

0 1

0

1A

B

L1

L2

B

B

AND

A B

L2

L1

1 1

1 0

0 1

0

1A

B

L1

L2

1 1

1 0

0 1

0

1

A

B

L1

L2

B

B

NAND (OR)

A B

L2

L1

B

B

OR

A B

L1

L2

B

A A

B

A

B

A

B

AND NAND

OR OR

Copmplementarity: AND>

NAND; Duality: AND>

OR


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Derivation of CPL LogicDerivation of CPL Logic

Duality: AND > ORNAND > NOR

0 0

0 1

BA 0 1

0

1A

B

L1

L2

a

B

B

AND

A A

B

B

N

A A

c

NAND

b

B B BB

L2

L1

Complementarity: AND > NAND


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TwoTwo--InputFunction with balancedInputFunction with balancedinput loadinput load

Each input A, B, or A, B has FO=2

B

B

AND

A B

A

A

NAND

B A

B

B

OR

B A

A

A

NOR

A B

(a) (b)

gatedraininCCC !


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Derivation of CPL LogicDerivation of CPL Logic

(a) XOR function Karnaugh map, (b) XOR/XNOR circuit

0 1

1 0

BA 0 1

0

1A

B

L1

L2

( )

B

B

XOR

A A

XNOR

( )

A A

L2

L1


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Synthesis of threeSynthesis of three--inputCPL logicinputCPL logic

0 0

0 0

BC

A 00 01

0

1A

C

L 3

L 2

(a)

A

B

AND

C

(b)

11 10

0 0

1 0

L 1

NAND

C

A

B

B

A B A B

L 3L 2L 1

(a) AND function Karnaugh map, (b) AND/NAND circuit


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Circuit realization of 3Circuit realization of 3--inputinputAND/NAND functionAND/NAND function

0 0

0 0

BC

A 00 01

0

1A

C

( )

A

B

AND

C

( )

11 10

0 0

1 0

NAND

C

A

B

B

A B A B

C3

C2

C1

C1

C2

C3


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Double PassDouble Pass--Transistor Logic (DPL):Transistor Logic (DPL):Synthesis RulesSynthesis Rules

1. Two NMOS branches can not be overlapped coveringlogic 1s. Similarly, two PMOS branches can not beoverlapped covering logic 0s.

2. Pass signals are expressed in terms of input signals orsupply. Every inputvector has to be covered with exactlytwo branches.

At anytime, excluding transitions, exactlytwotransistor branches are active (any of the pairsNMOS/PMOS, NMOS/NMOS and PMOS/PMOS arepossible), i.e. they both provide output current.


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Double PassDouble Pass--Transistor Logic (DPL):Transistor Logic (DPL):Synthesis RulesSynthesis Rules

Complementarity Principle: Complementary logicfunction in DPL is generated after the followingmodifications:

Exchange PMOS and NMOS devices. Invert all passand gate signals

Duality Principle: Dual logic function in DPL is

generated when: PMOS and NMOS devices are exchanged, and VDDand GND signals are exchanged.


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DPL Synthesis:DPL Synthesis:

0 0

0 1

BA 0 1

0

1A

B

L1

L2

( )

A B

B A

( )

L

L

3

4

BA

GND GND

AND

A B

B A

BA

NAND

+V DD +V DD

L2

L4

L1

L3

(a) AND function Karnaugh map (b) AND/NAND circuit


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DPL Synthesis:DPL Synthesis: OR/NOR circuitOR/NOR circuit

A B

BA

B A

OR

A B

B A

BA

GND GND

NOR

+V DD +V DD


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XOR/XNOR in DPLXOR/XNOR in DPL

Circuit realization of 2-input XOR/XNORfunction in DPL, with balanced input load

0 1

1 0

BA 0 1

0

1A

B

( )

B B

A A

( )

AA

B B

XNOR

B B

A A

AA

B B

XOR

(PMO )

(NMO )

(PMO )

(NMO )

C4

C3

C1

C2

C1 C2

C3

C4


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DVL LogicDVL LogicAdvantage of CPL and DPL were recognized in DVL which

attempts to generalize pass-transistor networks andminimize the number of transistors and input loads.

Rules:

1. Cover all inputvectors that produce 0 atthe output,with

largest possible cubes (overlapping allowed) and representthose cubes with NMOS devices,with sources connected toGND

2.Repeat step 1 for inputvectors that produce 1 atthe outputand representthose cubes with PMOS devices,with sources

connected to Vdd3.Finish with mapping inputvectors, not mapped in steps 1 and 2(overlapping with cubes from steps 1 and 2 allowed)thatproduce0 or 1 atthe output. Representthose cubes withparallel NMOS (good pull-down) and PMOS (good pull-up)branches,with sources connected to one of the input signals


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Two input AND/NAND in DVL LogicTwo input AND/NAND in DVL Logic

Circuit realization of 2-input AND/NAND function in DVL

0 0

0 1

BA 0 1

0

1A

B

C1

( )

B

A

( )

C

BA

AND

A

B

BA

NAND

Vdd Vdd

(A*)

(B*)

C2

C3

C1

C2


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Two input OR/NOR in DVL LogicTwo input OR/NOR in DVL Logic

Circuit realization of 2-input OR/NOR circuit in DVLXOR/XNOR realization is identical to that of DPL.

B

A

A

NOR

A

B

BA

OR

Vdd Vdd

B


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Three input AND function in DVLThree input AND function in DVLLogicLogic

0 0

0 0

BC

A 00 01

0

1A

C

( )

AND

( )

11 10

0 0

1 0 A B B B

A A

C

B

C3

C2

C1

C2

C1

C3

C3


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Three input OR/NOR in DVLThree input OR/NOR in DVL

Circuit realization of 3-input OR/NORfunctions in DVL

NOR

A B B B

A A

C

OR

A B B B

A A

CV dd


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ComparisonComparison

Realization# ofinput

signals

Signaltermination

Trans.Count

Outputload

CMOS 9 10G 10 4S

DVL (b) 9 8G + 6S 8 6S

DVL (c) 9 7G + 3S 7 4S

TABLEI. Realizations of 3-input functionF=BC+ABC


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ComparisonComparison

Realizations of 3-input function F=BC+ABC(a) Standard CMOS, (b) DVL, (c) DVL

0 1

0 1

BC

A 00 01

0

1A

C

F

11 10

0 0

0 1

B C

C

C

B

B

B

A

A B C

Vdd

0 1

0 1

BC

A 00 01

0

1A

C

11 10

0 0

0 1

B

0 1

0 1

BC

A 00 01

0

1A

C

11 10

0 0

0 1

B

C

B

C

C

B C B

F

BCC

A

B

B

A

B B

C

F

C

B

C

B

C

A

(a) (b) ( )

B C A B CF = +

C2 C

1

C2

C1

C1

C1

C2

C2

C3

C3

C3

C2

C1

C1

C2

C3

C2

C3

C3


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ConclusionConclusion

General rules for synthesizing logic gates in threerepresentative pass-transistor techniques wereshown.

An algorithmic way for generation of various circuittopologies (complementary and dual circuits) is

discussed.Generation of circuits with balanced input loads is

suitable for library based designs is possible ifcomplementarity and commutative principles areapplied.

This lays the foundation for development of computeraided design (CAD)tools capable of generating fastand power-efficient pass-transistor logic.

lect4-p-t-logic

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