lect07 interrupts

7/30/2019 Lect07 Interrupts

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Chapter 7PIC Interrupts

TAB4333 Embedded Systems


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Interrupt Mechanism

Interrupts are mechanisms which enable instant response to

events such as counter overflow, pin change, ADC data

conversion completed, data received, etc, i.e. in general

interrupts in embedded systems are meant to handle those

asynchronous events.

In normal mode, PIC executes the main program as long as there

are no event causes an interrupt.

Upon interrupt, microcontroller stops the execution of main

program and commences the special part of the program which

will analyze and handle the interrupt. This part of program is

known as the interrupt service routine(ISR). Whatever code stored in ISR will be executed upon interrupt.

First, we need to determine which event caused the interrupt,

after that comes the interrupt handling, which is executing the

appropriate code for the triggered event.


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18F452 Interrupts

It has 10 regs to control interrupts: RCON, INTCON, INTCON2,

INTCON3, PIR1, PIR2, PIE1, PIE2, IPR1, IPR2 (ref: datasheet) The PIC18F452 has two priority levels (high and low).

High priority interrupts cause a jump to program address 0x0008

(the high-priority interrupt vector).

Low priority interrupts cause a jump to program address 0x0018 (the

low-priority interrupt vector).

The entry point for ISR is therefore either at 0x0008 or 0x0018

i.e. goto xxxisr

Both the low-priority and high-priority interrupts can potentiallyhave multiple sources. If either does, the ISR must poll the

interrupt sources to determine which need service.


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Typical Polling Routine

:loop {

rcall isr1bra loop } {

rcall isr2bra loop }

{

rcall isr3bra loop }::

The polling routine jumps back to the loop after running each

interrupt service routine in case other interrupts become activewhile running the ISR.

Note: Allowing the ISR to exit and immediately re-interrupt in

this case may wastes machine cycles.


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Interrupt Latency

The worst-case time between the occurrence of an interrupt

source and the start of its handler is called interrupt latency.

Interrupt latency actually includes hardware overhead for

interrupt processing and instructions in the polling routine.

Mainline program

ISR

I/latencyTi

Tp

Tp time interval between interupts

Ti time to execute ISR

Note: Ti < Tp What about if there are many Ti?


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Low-Priority ISR If any registers are altered by any of the handler routines, they

should be saved to temporary locations before ISR is executed and

later restored when the ISR returns

context saving and restoring. Register saving/restoring is much easier if:

1) BSR (Bank Select Register) always contains 0x00 in program.

2) FSR0 and FSR1 used only by main program and FSR2 used only

by interrupts. (FSR File Select Register)

3) PCL never used as an operand in interrupts.

The low-priority ISR needs to at least save/restore W and STATUS.

STATUS should always be the first to be saved and the last register

to be restored in the ISR since mov instructions can alter STATUS.

movff status,status_temp ;save status reg

movwf wreg_temp ;save working reg

:

movf wreg_temp,w ;restore working reg

movff status_temp,status ;restore status reg


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Typical Low-Priority ISR

org 0x0018

goto LPISR

LPISR org 0x0030 ;starting addrs of isr

movff STATUS, S_TEMP ;save the status

movwf W_TEMP ;save wreg contents

;perform polling

movf W_TEMP, W ;restore wreg contents

movff S_TEMP, STATUS ;restore status

retfie ;return from interrupt enabled


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Enabling Interrupt Priority At power-up the PIC18F452 starts with a single interrupt level the high

priority interrupt only.

To enable use of both high and low priority interrupts set the interrupt priority

enablebit (IPEN) in the RCON (Reset Control) register

bsf RCON, IPEN ;reset control register setting

Before any interrupts can occur (high priority or low priority) the global interrupt

enable highbit (GIEH) in the interrupt controlregister (INTCON) must be set on:

bsf INTCON, GIEH

Enabling Any Interrupt


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Enabling Low-Priority Interrupts

Before any low-priority interrupts can occur both the GIEH and the globally interrupt enable

low(GIEL) bits of the INTCON register must be set:

bsf INTCON, GIEH

bsf INTCON, GIEL

Changing to Low Priority

On power-up all PIC18F452 interrupt sources generate high-priority interrupts by default (1

level only).

To change a source to low priority reset the priority bit for the source. For example, to make

Timer1 a low-priority source reset the TMR1IP bit of the IPR1 register:

bcf IPR1, TMR1IP


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Enabling an Interrupt Source Even if a source has been set to low priority and low-priority interrupts are enabled (GIEH=1,

GIEL=1), the source cannot generate an interrupt until it has also been enabled (by default all

sources are disabled at power-up).

Example: to enable the A/D converter to generate interrupts the ADIE bit of the PIE1 registermust be set:

bsf PIE1, ADIE

Interrupt Source Events When some event occurs which causes an interrupt for a source, the interrupt flag for that

source is automatically set.

Example: if the A/D converter has a new sample value available the A/D converter sets the

ADIF bit of the PIR1 register.


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Triggering Low-Priority Interrupt A source will trigger a low-priority interrupt ifall of the following

are true:

1) GIEH = 1

2) GIEL = 1

3) Sources priority bit = 0

4) Sources enable bit = 1

5) Sources event flag = 1

6) No low or high priority interrupts are in progress.

Triggering High-Priority Interrupt A source will trigger a high-priority interrupt ifall of the following

are true:1) GIEH = 1

2) Sources priority bit = 1

3) Sources enable bit = 1

4) Sources event flag = 1

5) No high priority interrupts are in progress.


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17 Interrupt Sources External interrupts: INT0 (RB0 pin), INT1 (RB1 pin), INT2 (RB2 pin).

PORTB change: Any change on RB4, RB5, RB6, or RB7 (this is a

single source). Timer overflow (increment from 0xFFFF to 0x0000): Timer0, Timer1,

or Timer2.

Timer value match: Timer2 value matches contents of PR2 register.

Capture, compare, pulse-width-modulation unit (CCP) events:CCP1 and CCP2.

A/D converter value ready

USART has received a new value (RC).

USART is ready to send a new value (TX).

Synchronous serial port (SSP) is ready. Parallel slave port (PSP) is ready. Low voltage condition detected.

Abus collision has been detected.


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1. High-Priority Interrupts

High-priority interrupts automatically save three registers to

shadow(fast saving) copies of the registers: STATUS, W, andBSR. To restore the shadow registers value into the actualregisters use:

retfie FAST

2. External Interrupts

PORTB pins 0, 1, and 2 can be used (independently) as interruptssources.

The interrupts can be either positive-edge-triggered or negative-edge

triggered (positive on power up by default) The INTEDG0 bit of the INTCON2 register is set to make INT0 (RB0

pin) positive-edge triggered and reset to make it negative-edgetriggered.

The INTEDG1 and INTEDG2 bits of INTCON2 control INT1 (RB1) and

INT2 (RB2) respectively.

Other Notes:


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Example 1 - External Interrupts

For a pin to be used as an external interrupt, it must configured

as an input pin.

To use the INT0 source (RB0), set bit 0 of the TRISB so that

RB0 will be an input:

bsf TRISB, 0

Example: A magnet on the wheel of a bicycle passes a sensor onthe frame of the bicycle once per revolution. The sensor is

connected to the RB1 pin of the PIC.

If the RB1 pin is set up as input and the INT1 source is enabled,

the interrupt handler routine for INT1 can increment a variable forevery wheel rotation what are the possible applications?


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Example 2 - Port B Change Interrupts

If any of the pins RB7, RB6, RB5, or RB4 which are set up as

inputs changes value, the port B change source will have aninterrupt event.

If any of the above port B pins are set up as outputs (associated

TRISB entry is 0), then they are ignored for determining a port

B change event.

Example: Make RB7-RB4 inputs which read the rows of a 4X4

keypad matrix.

If all of the columns of the keypad are enabled (using 4 other

port bits set up as outputs), then pressing any key will cause aport B change event what is the effect and application?

Refer to text book pg 449 to see another example


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Lab Exercise:

LEDs at RB3 to RB7 is always on until S1 is pressed thenLED at RC0 is toggled while LEDs at RB3 to RB7 are off forapprox 2 sec.

INT0

RC0

Vdd

Gnd

Gnd

S1 RB7

RB3

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