lect 1 - system design.pdf

8/14/2019 Lect 1 - System design.pdf

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ELEC 2002

Design using MSI Components


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Digital system design

Requirement analysis

Extensive requirement analysis leads to a detailed specification ofthe product.

Functional design

Partitioning of logic into physical units such as chips, boards etc.This process simplifies testing, component placement and wirerouting.

Logic design

Each functional unit is designed. That is, the integrated circuit ofeach unit is designed and interconnection of the units are specified.


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Digital system design

Physical design

During this phase the physical positioning of the components andthe routing of wires to connect them are specified.

Physical positioning assignment of circuits to specific areas of the

board.Routing physical connection of the parts after they have beenplaced.

Implementation

Sample units

Mass production of individual system implementation.


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Logic Design

Requirements:

Minimum or Zero errors

Hardware efficient Knowledge of different types of

components (ICs) is compulsory

Cost efficient Technical details as well as cost

Energy efficient power requirements of ICs


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Classification of ICs

Small Scale Integration or (SSI)- Contain up to 10 transistors or a few gates withina single package such as AND, OR, NOT gates.

Medium Scale Integration or (MSI)- between 10 and 100 transistors or tens ofgates within a single package and perform digital operations such as adders,decoders, counters, flip-flops and multiplexers.

Large Scale Integration or (LSI)- between 100 and 1,000 transistors or hundreds ofgates and perform specific digital operations such as I/O chips, memory

Very-Large Scale Integration or (VLSI)- between 1,000 and 10,000 transistors orthousands of gates and perform computational operations such as processors, largememory arrays andprogrammable logic devices.

Super-Large Scale Integration or (SLSI)- between 10,000 and 100,000 transistorswithin a single package and perform computational operations such asmicroprocessor chips, micro-controllers, basic PICs and calculators.

Ultra-Large Scale Integration or (ULSI)- more than 1 million transistors - used incomputers CPUs, video processors, micro-controllers, FPGAs and complex PICs.


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Logic Families

TTL (Transistor-Transistor Logic)

Standard TTL (74)

Low-power TTL (74L)

Schottky TTL (74S)

Low-power Schottky (74LS)

Advanced Schottky (74AS)

Advanced low-power Schottky (74ALS)

Fast TTL (74F)

Speed

Power

dissipation

H/W characteristics of each TTL family


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Typical TTL series

characteristics

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Input and Output logic

designation


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Digital IC Terminology

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Digital IC Terminology Fan

Out

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A logic-circuit output is generally required to drive several logic inputs.

Sometimes all ICs are from the same logic family.

But many systems have a mix of various logic families.

The fan-outloading factoris the maximum number of logic inputs an

output can drive reliably.

FA (high) = IOH(max) / IIH(max)

FA (low) = IOL(max) / IIL (max)


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Digital IC Terminology Power

Requirements

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The amount of power an IC requires is determined by the current, ICC(or IDD) it

draws from the supply.

Actual power is the product ICCx VCC (IDDx VDD ).

In some logic circuits, average

current is computed based

on the assumption that gate

outputs are LOW half the

time and HIGH half the time.


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Propogation Delay

A logic signal always experiences a delay going through a circuit. Propagation

delay time after which output is assigned after any change in the input.

The two propagation delay times are defined as:

Propagationdelays.


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Digital IC Terminology Noise

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Stray electric/magnetic fields can induce voltages on the

connecting wires between logic circuits called noise , these

unwanted, spurious signals can sometimes cause

unpredictable operation.

Noise immunity refers to the circuits ability to tolerate noise

without changes in output voltage. A quantitative measure is

called noise margin.


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Digital IC Terminology Noise

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High-state noise margin: Low-state noise margin:


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TTL NAND gate

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Basic TTL

NANDgate.

Diode equivalent

for Q1 .

1. Totem pole is made of 2 transistors Q3 and Q4.

2. The job of Q3 is to connect Vcc to the output, making a

logic High.

3. The job of Q4 is to connect the output to ground making a

low.


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TTL NAND gate

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TTL NAND gate

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8-1 Digital IC Terminology IC

Packages

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Package of IC

Dual inline package with

14 pins

Also available in 16 pins

The DIP (dual-in-line package)

has pins (leads) down the

two long sides of the

rectangular package.

The notch on one end,

is used to locate pin 1.Some DIPs use a small

dot to locate pin 1.


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Data sheet for the 74ALS00

NAND gate IC

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74ALS series

voltage levels.


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Examples - 74ALS00A

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1. Calculate input and output fanout and determine the number of similar

components that can be connected to the output of the 74ALS00A

2. Calculate the low and high noise margins of the component

3. Calculate the average power dissipation of the component


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Package of IC

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Current manufacturing methods use surface-mount technology (SMT), which

places an IC onto conductive pads on the surface of the board.

Held in place by a solder paste,and the entire board is heated to

create a soldered connection.

Precision machine placement

allows for very tight lead spacing.

Leads are bent out from the plastic case,providing adequate surface

area for the solder joint.


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Package of IC

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The PLCC has J-shaped

leads that curl under the IC.These devices can be surface-

mounted to a circuit boardbut can

also be placed in a special socket.

Commonly used for components

likely to need to be replacedfor repair or upgrade.

PLCC - Plastic Leaded Chip Carrier


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Package of IC

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The Pin Grid Grray (PGA) is a

similar package, used when

components must be in a socket

to allow easy removal.

The PGA has a long pin instead

of a contact ball (BGA) at each

position in the grid.


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Package of IC

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The land grid array (LGA)package is essentially a

BGA package without the

solder balls attached.


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Active HIGH and LOW outputs

and Enable

An enable/disable input controls

the operation of a chip.

1. Active HIGH Enable - Logic

level 1 enables the system

2. Active LOW Enable - Logic

level 0 enables the systemOutputs as well can be active

HIGH or active LOW.

Active low

output

Active LOW

enable

active HIGH input


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Logic Design process

Specifications

State table or Truth table

Inputs and Outputs, state variables

Assignment of variables

State minimisation or minimisation of Boolean expression K-map, implication chart method

State equations or Boolean expressions

Choice of ICs

Design of hardware/energy efficient system

Testing and modification

Implementation

lect 1 - system design.pdf

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