lec9.2 array sub systems 2

8/7/2019 lec9.2 Array Sub Systems 2

1/23

Lec9.2A RA R RR A Y S U B S Y S T E M SA Y S U B S Y S T E M S -- IIII

Engr. Anees ul Husnain ( [email protected])

Department of Electronics & Computer Systems Engineering,College of Engineering & Technology, IUB

[sources: Weste/Addison Wesley Rabaey/Pearson]


2/23

Lecture outline

Last time

Memory periphery (row/column circuitry)

Core cell: SRAM cells

Decoders Pre Decoders

This time (different core cells)

DRAM cells

PLA


3/23

3T DRAM cell

X Vdd-Vt

BL1

Vdd

WWL write

RWL read

BL2 Vdd-Vt (V

No constraints on device sizes (ratioless)

Reads are non-destructive

Value storedat nodeXwhen writing a 1is VWWL - Vtn

M1 M2

M3

X

BL1 BL2

WWL

RWL

Cs


4/23

1T DRAM Cell

M1 X

BL

WL

CsCBL

X Vdd-Vt

WL write1

BL Vdd

read1

Vdd/2 sensing

Write: Cs is charged (ordischarged) by asserting WLandBL

Read: Chargeredistribution occurs between CBL andCs

Readis destructive, so mustrefreshafterread

Leakage cause storedvalues to disappear refresh

periodically


5/23

The bit line is precharged to VDD/2


6/23

How DRAM cells are manufactured?

Trench

capacitor


7/23

DRAM subarray architectures

sensitiveto noise

rejects common mode noise


8/23

PLAs & FPGAs


9/23

ROMs

Read-Only Memories are nonvolatile

Retain their contents when power is removed

Mask-programmed ROMs use one transistor per bit

Presence or absence determines 1 or 0


10/23

NOR ROMs

ROM Array

2:4

DEC

A0A1

Y0Y1Y2Y3Y4Y5

weak

pseudo-nMOS

pullups

4-word x 6-bit ROM

Represented with dot diagram

Dots indicate 1s in ROM

Word 0: 010101

Word 1: 011001

Word 2: 100101

Word 3: 101010

Looks like 6 4-inputpseudo-nMOS NORsDotdiagram


11/23

NAND ROM

All word lines high by defaultwithexception ofselectedrow

No transistorwiththe selectedword-> bitlinepulleddown

Transistorwiththe selectedword-> bitlineremain high

WL [0]

WL [1]

WL [2]

WL [3]

VDD

Pull-updevices

BL [3]BL [2]BL [1]BL [0]


12/23

Using ROMs to implement logic

ROM

(truthtable)

Inputs Outputs

In mostdesigns,using ROMs can beextremely inefficientin terms ofarea


13/23

Programmable logic arrays

A Programmable Logic Arrayperforms any function in

sum-of-products form.

Literals: inputs & complements

Products / Minterms: AND of literals

Outputs: OR of Minterms

Example: Full Adder

out

s abc abc abc abc

c ab bc ac

!

!

AND Plane OR Plane

abc

abc

abc

abc

ab

bc

ac

sa b cout

c

Minterms

Inputs Outputs


14/23

NOR-NOR PLAs

ANDs and ORs are not very efficient in CMOS Dynamic or Pseudo-nMOS NORs are very efficient

Use DeMorgans Law to convert to all NORs

AND

la

e OR

la

e

abc

abc

abc

abc

ab

bc

ac

s

a b c

outc

AND

la

e OR

la

e

abc

abc

abc

abc

ab

bc

ac

s

a b c

outc


15/23

PLA schematic and layoutAND la e OR la e

abc

abc

abc

abc

ab

bc

ac

s

a b c

outc


16/23

PLAs vs. ROMS

PLAs are more flexible than ROMs

No need to have 2n rows for n inputs

Only generate the minterms that are needed

Take advantage of logic simplification

PLAs are popular for small-scale circuits that have2-level implementations

PLAs are not scalable to implement large designs


17/23

Programmable logic blocks (lookup tables)

Programming information could be storedin SRAM orFLASH

4-inputLUTis thetypical size


18/23

FPGA architecture

Switch

box


19/23

To implement in FPGAs, designs need to be

decomposed and mapped to LBs

Mapto aLUTin aLB

[Figureform Cong FPGA01]


20/23

Programmable interconnects (global)

Switch

box


21/23

Example


22/23

Programming the FPGA


23/23

FPGAs versus custom chips

Offer flexibility FPGAs can be reprogrammed to perform

different logic functions

No layouts, no masks, no custom fabrication huge savings

for low, med-volume production Larger overhead in area, performance, and power

lec9.2 array sub systems 2

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