lec3 (substrate etc).ppt · why an 8-form coil?? p. andreani – system-on-chip n. itoh et al.,...

Noise coupling in SoC/SiP

System-on-Chip

Pietro AndreaniDept. of Electrical and Information Technology

Lund University, Sweden

• “Switching” noise generation

• Noise injection and reception

• Substrate coupling in CMOS

• Noise propagation

Overview

P. Andreani – System-on-Chip

• Biasing strategies

2Noise coupling

Vdd

Types of noise coupling

• Crosstalk • dV/dt, dI/dt

• Power line noise coupling (dI/dt)

ThicknessSpacing

Crosstalk

Vss

Cir.1 Cir.2dI/dtVdrop


• Substrate noise coupling (dV/dt)

• Radiation noise coupling

λ1GHz2 =1.25cm

Substrate

3Noise coupling

Reducing crosstalk through metal wires

• No parallel lines (difficult to realize)

• Large space between lines (area penalty)

• Reduce Cm/C and Lm/L with a ground plane close to lines (speed and power penalties)

In nm CMOS technologies wire spacing is small large crosstalk must be reduced:


• Place ground lines between active lines (area penalty, as well as speed)

• CAD tools to estimate the crosstalk and to limit the crosstalk within an acceptable level

• Special coding to cancel the crosstalk from two or more active “digital” lines, e.g. differential in the case of 2 active lines

• Innovative CMOS process steps are needed in general!

4Noise coupling

General power supply distribution model


ChipBoard

• Internal power/ground distribution can be seen as resistive except bond wires

• Noise may be transmitted from one chip to another chip the small sensitive analog signals may easily become corrupted

• At the board level, large decoupling components can be used – more difficult to do so at the chip level

5Noise coupling

Noise due to wire resistance

Average/peak voltage drops in wires with full current densities

Wire type

Sheet resistanceCurrent density100 μm long1000 μm long

Metal-1

0.08 Ω1 mA/μm

7mV/70mV70mV/0.7V

Metal-top

0.04 Ω1 mA/μm

4mV/40mV40mV/0.4V


1000 μm long10 mm long

70mV/0.7V0.7V/7V

40mV/0.4V0.4V/4V

Note: In synchronous circuits, Ipeak ≈ 10 × Iaverage

Peak voltage drop (noise) is a fundamental source of noise in SoC

6Noise coupling

Inductance is even more critical than resistance

dI/dt noise via power supply

Inductance of power lines and bonding wires often crucial

I

L

V


V = L

7Noise coupling

dΙdt

Chip interface

(a) Wire bonding.


(a) Wire bonding.

(b) Flip-chip bonding.

8Noise coupling

Pad circuit (with bond wire)

Pin

Bond wire inductance

large protectivediodes

I/OLb≈1-5nH

Pad50x50 μm2

Vdd


Cpin > 1pF Cn+Cn > 1pFCpad≈0.25pF

Out/In In/OutL>1nH

C1>1pF C2>1pF

9Noise coupling

dI/dt noise in CMOS

• Simultaneous switching noise (SSN), also called ground bounce

• Output buffers drive large loads especially important multiple pins may be needed

• Millions of gates switching simultaneously very large current spikes


spikes

• Logic families with almost constant power consumption have been proposed, similar to BJT ECL logic (i.e. enhanced source-coupled logic, folded source-coupled logic) large quiescent power consumption not popular

• On-chip or on-package decoupling capacitors are always needed

10Noise coupling

Design criteria for reducing dI/dt noise

L1R1

C1

R2

C2

VDD+-

LR

<< RC1.

2.dIdt

<< VDDL

I

L2

L= L1+L2

Inductivetime constant

Capacitivetime constant


• Simultaneously switching large dI/dt

• High speed RC must be small harder to meet L << R2C

• Large designs small R harder to meet L << R2C

• During switching, power fluctuation must be kept to a small part of VDD, not only for analog but also for digital circuits.

11Noise coupling

dt

Decoupling capacitor CD reduces fluctuation

CD

C

VDD+-

L1

L2

ΔV


CDVDD = (VDD + ΔV)(CD +C) ΔV =C

CD + CVDD

• If a max. 10% voltage drop is allowed CD > 10C required

• If total chip capacitance of a microprocessor is 1nF CD should be larger than 10nF (!)

• In reality, the unswitched fraction of C acts as a decoupling capacitance

12Noise coupling

Assuming all current is supplied by CD (worst case)

Technological differences of P-/P+ substrates

Wafer thickness

Epitaxial layer:4-15 μm1-50 Ωcm

p-

P. Andreani – System-on-Chip 13Noise coupling

Wafer thickness50-500 μm1-50 Ωcm

p-1-50 mΩcmp+

Low-conductive lightly-doped wafer

High-conductive heavily-doped wafer with an epitaxial layer

Substrate noise coupling in CMOS

Digital GND Analog GND

Biasing contact

Sensitive Node

Cj

Voltage transient

Biasing contact

V V I

Cj

p-

Wires & pads

12 3


1. Noise injection through reverse-biased junction capacitance

2. Noise injection through contacts

3. Noise injection through wire-to-substrate capacitance

Also others: through forward-biased junction and hot carriers

VBS VT IDSp-

Noise injection via substrate contacts

Digital GND

Biasing contact

p-

Digital POWER

Biasing contactn-well

200-500 mV 200-500mV


p-

• Due to simultaneous switching, noise amplitudes on power and ground wires may reach 500mV

• This noise directly affects the substrate through bias contacts

• Contacts are spread all over the substrate large impact, even more significant than that of junction capacitances

Noise injection via parasitic capacitance

PadsPower/Ground wires

RF inductor


Pads RF inductor

• Lowest level of wire parasitic capacitance to substrate is another source of noise injection

• Pads, power/ground wires and RF inductors are particularly significant in producing substrate noise through their large parasitic capacitance

Why an 8-form coil??


N. Itoh et al., “5.8 GHz RF Transceiver LSI Including On-Chip Matching Circuits”, 2006 IEEE BCTM, paper 14.1

1717Noise coupling

Noise injection via forward biased junction

Reverse-bias

Forward-bias

Noise on digital ground wire

Protective diodes

Negative pulses may

n-well

Digital ground wire

Source diodes


Negative pulses maybe directly injected into substrate

• The pad protective diodes and the nMOS source diodes can be forward-biased by the negative noise pulses on the digital ground wires inject large noise into the substrate

• This noise is similar to that through substrate contacts

Substrate Substrate

Noise reception via Cj, Cd, and contacts

Analog GNDSensitive node

Biasing contact

Cj Cd


• The substrate noise can be received by the sensitive node through Cj and Cd, where Cd is the capacitance between the channel and substrate (which are separated by the depletion layer)

• The noise can also be received by the analog ground through the substrate contact. For an analog circuit with a low PSRR, this would be a major noise source

Noise reception via body effect

Analog GNDSensitive node

Bulk (substrate)

Source

VBS

Noise at drain (V)0.0200.0180.0160.0140.0120.0100.0080.0060.0040.002

VDS = 2.5VVBS = 10mV


0.0022E16 4E16 6E16 8E16 1E17

Substrate doping (cm-3)

VT = Vto+γ( 2φb-VBS - 2φb )γ =

2qεsiNA

Cox

φb = lnKTq

NAni

VBS VT IDS ( VDS )

Effect of a guard ring (P-)

No backplane contact

(less important in P-)


Without a guard-ring With a guard-ring

Constant voltage contour lines simulated with the RAPHAEL

Replacing guard ring with contacts (P-)


continuous trench (100μm) 5 contacts (each 10 μm)

3 contacts (each 10 μm) 2 contacts (each 10 μm)

Noise reduction techniques (ideal supply lines)

500μm

10μmNoisy NMOS NMOS

1) No measure

P-

SiO22μm

2μm

2) An oxide trench

P-


3) An N-ring to Vdd

P-

+5V

N+

4) An N-ring inside an N-well

P-

+5V

N+

N-well

Noise reduction techniques – II

5) An N-ring to ground

P-

0V

N+

6) A P-ring to ground

P-

0V

P+


7) A buried layer to ground

P-

0V

N+

4μm

8μm

0μm

Comparison between the different techniques

No measure (1)

Oxide trench (2)

N-ring to Vdd (3)

N-ring inside N-well (4)


0 25 50 75 100 125 150 175

N-ring inside N-well (4)

N-ring to ground (5)

P-ring to ground (6)

Buried layer (7)

Peak-to-peak noise level (mV)

However, these results may be process dependent!

Noise reduction in SOI technology

P substrate

SiO2

Analog part Digital part


• Silicon on Insulator (SOI) technology isolates analog and digital parts into separate substrate islands better for noise reduction.

• At high frequency, however, the two islands are still coupled through the capacitance to the p-substrate limited noise reduction, high cost SOI not very attractive in general

Conclusions

Noise vs. distance with an ideally grounded backplane

Backside contacts

Type of guard-ring

Contacts instead of ring

Length of guard ring

Position of guard ring

P- substrate

Noise attenuation increases with distance

Almost useless

P+ in P- and N+ in N- substrate

Yes, easy for wire crossing

Less important

Across the path, close to source


Position of guard ring

Width of guard ring

Low impedance to ground

Across the path, close to source

Less important

Important

In general, the effectiveness of decoupling depends on the impedance of the return path guard ring contacts should have a very low impedance

Backplane contact not important in P-

Fundamental questions

• What is better for biasing the substrate, digital ground or analog ground?

• Is it better to use an exclusively dedicated substrate biasing line?What will be the consequences?

• Is a guard ring really effective? Where should the guard ring be connected?

P. Andreani – System-on-Chip Noise coupling 28

connected?

• For a given biasing strategy, is it better to use many or just a few contacts?

• Will the pad ring affect the biasing strategy?

Test circuit arrangement

• Technology: 2M N-well 1.2μm CMOS (old!!)

• Digital part: 256 noisy inverters in 16 groups, 16 inverters each group, driven by a combinational tree

• Analog part: a simple sense amplifier with short-circuited input and output at a DC voltage of Vdd/2, i.e. 2.5 V in this case, loaded by another identical sense amplifier

• Power supply: independent lines for the analog part, the digital


• Power supply: independent lines for the analog part, the digital part, and the digital pads

• Pads: 30 digital and 10 analog pads

• Parasitic capacitance: extracted from the layout

• Substrate resistance: extracted by device simulator MEDICI

Preliminary floor plan of the test circuitAnalog signals

Power/ground

Power/ground


Digital signals

Digital signals

Digital signals

Power/ground rings

Illustration of the test circuit

256 inverters in 16 groups

50/1.2

.

(VEP-D) (VEP-A)

(VAP)(VDP)


16 groups 30/1.2

(VEG-A)(VEG-D)

(VAG)(VDG)

All biasing strategies will be evaluated

Other conditions and terminology

(3) Terminology for lines:

A: the line feeds analog section

D: the line feeds digital section

E: the line used for biasing without feeding current to any transistor

(4) Terminology for biasing:

(1) Equivalent circuit of a package pin:


Figures for a large chip

X/Y: a biasing combination

X indicates the line to which digital contacts are connected

Y indicates the line to which analog contacts are connected

X/G/Y: G is the line to which the guard ring contacts are connected

(2) Clock frequency: 20 MHz

Mutual inductance between different pins is disregarded!

Biasing strategies (1)

VDP

VDG

VAP

VAG

D/D

D

D

A

A

D/A

VDP

VDG

VAP

VAG

D

D

A

A


D/E

VDP

VDG

VAP

VAG

D

D

A

A

VEP

VEG

A/A

VDP

VDG

VAP

VAG

D

D

A

A

Biasing strategies (2)

E/A

VDP

VDG

VAP

VAG

D

D

A

A

VEG

VEP

E/E

VDP

VDG

VAP

VAG

D

D

A

A

VEP

VEG


No SSN

VDP

VDG

VAP

VAG

D

D

A

A

SSN – Simultaneous Switching Noise

Noise level in P- substrate

D/D

D/A

D/E

A/A

E/A

E/E

No SSNNormalized noise level

66.5mV


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

• A/A is the worst strategy, while D/E or E/A are the best

• D/A and E/A minimize body effects, but noise propagates through substrate, then couples to supplies through contacts/capacitances

• Notice however that D/A is even (slightly) better than E/E great, no need of dedicated lines

• With ideal pins (no SSN), noise only through substrate insignificant compared to that through power/ground contacts

Normalized noise level

A/A - the worst biasing strategy

VAPVDP


Noise goes first to nearby contacts and then directly through wires to the analog section

VAGVDG

D/D - the second worst biasing strategy

VAPVDP


Noise can directly go to the contacts of analogsection and reach the source node in close distance

VAGVDG

D/A - a good biasing strategy without E-line

VAPVDP


The only path for noise going to analog section is the P- substrate, which will attenuate the noise due to its large resistance. D/A is better than D/D or even E/E

VAGVDG

D/E - one of the best biasing strategies

VAPVDP

VEP


Compared with D/A, supply noise is decoupled with analog power supply lines

VAGVDG

VEG

E/A - one of the best biasing strategies

VAPVDP

VEP


Compared to D/A, noise is decoupled from the digital power supply lines

VAGVDG

VEG

E/E - worse than D/E or E/A

VAPVDP

VEP


The noise coupled to nearby digital contacts directly goes to analog section via wires and makes things worse

VAGVDG

VEG

E1/E2 - the best biasing?

VAPVDP

VEP1 VEP2


It should be the best biasing at the cost of two dedicated supplies. There are no internal wires between digital and analog sections.

VAGVDG

VEG1VEG2

No SSN - attractive but practically unfeasible

VAPVDP


Without inductance, the substrate is ideally biased, only device noise remains. The two power supplies may be merged. However, it is unfeasible practically.

VAGVDG

What if fewer contacts?

VD

G

VAP

VAG

VDP

10×

10× 10×

10×Unchanged


Fewer contacts contact-related resistance increases less noise drained coupling between devices increases, but noise on supply lines decreases

p-

10×

10×

10×

The fewer the contacts, the higher the noise (P-)

40%

10%

8%

21%

37%

35%

D/D

D/A

D/E

A/A

E/A

E/E

No SSN

Reference circuit1/10 contact number


• The “no SSN” case has the largest relative increase – this is because device coupling is maximized in this case

• The other results are less straightforward to interpret

122%No SSN

0 10 20 30 40 50 60 70 80 90 100Root-mean-square voltage over a 10ns period (mV)

The effect of guard ring biasing (p-)

D/AD/A/AD/E/A

D/ED/E/E

E/AE/A/AE/E/A

E/EE/E/E


0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Normalized noise level No SSN

• Little change, since the large parasitic capacitances on the supply lines are the dominating mechanism

• D/A/A and E/A/A bias the rings with analog supply, and the reason for the limited effect is that the original analog ground is already a guard ring

• E/E/A biases the ring with the same line biasing the digital section, it introduces noise (D/D/A or D/D/E are similar to D/D (i.e., bad))

The effect of pin inductance (p-)

D/D

D/A

D/E

A/A

E/A

E/E

10 nH1 nH

66.5mV


E/E

No SSN

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Normalized noise level

• With small terminal inductance (almost no SSN), there is little differencebetween different biasing strategies

• For a chip with large terminal inductance, the selection of biasing strategy becomes important

• Inductance “large” or “small” depends on the noise level we can tolerate

Conclusions (P- substrate)

• Minimize impedance on supply lines

• Separate supply domains for analog/digital – use D/A or D/E for biasing (E/A ok, but may cause latch up)

• Distance between analog and digital helps always

• Guard rings help, too best if biased with dedicated


• Guard rings help, too best if biased with dedicated lines

• And, implement all analog functions as differential circuits whenever possible

Buried layers with deep contacts

digital GND noisy noisy

digital Vdd

analog GND sensitive sensitive

analog Vdd

(2) Only under the sensitive devices with deep contacts:

digital GND noisy

NMOSnoisy PMOS

digital Vdd

analog GND sensitive

NMOSsensitive PMOS

analog Vdd

P-BL 50 mΩ⋅cm N-BL 25 mΩ⋅cm

(1) Only under the noisy section with deep contacts:

N-well 10 Ω⋅cm N-well 10 Ω⋅cm


GND noisy NMOS

noisy PMOS

Vdd GND sensitive NMOS

sensitive PMOS

Vdd



digital GND noisy

NMOSnoisy PMOS

digital Vdd


NMOSsensitive PMOS

analog Vdd

P-BL 50 mΩ⋅cm N-BL 25 mΩ⋅cmP-BL 50 mΩ⋅cm N-BL 25 mΩ⋅cm

(3) Under all the circuitry with deep contacts:


49Noise coupling

Buried layers without deep contacts

digital GND noisy noisy

digital Vdd

analog GND sensitive sensitive

analog Vdd

(5) Only under the sensitive devices without deep contacts:

digital GND noisy

NMOSnoisy PMOS

digital Vdd


NMOSsensitive PMOS

analog Vdd


(4) Only under the noisy section without deep contacts:



digital GND noisy

NMOSnoisy PMOS

digital Vdd


NMOSsensitive PMOS

analog Vdd


(6) Under all the circuitry without deep contacts:


GND noisy NMOS

noisy PMOS

Vdd GND sensitive NMOS

sensitive PMOS

Vdd


N-well 10 Ω⋅cmN-well 10 Ω⋅cm

50Noise coupling

Three possible arrangements of buried layers

(1)

(2)

(3)

(4)

(5)

(6)


• As expected, buried layers reduce substrate noise significantly

• The deep bias contacts are essential, particularly for buried layers under the analog section – otherwise, basically same situation as P+

without backplane contacts (N/P buried layers are connected by a relatively large junction capacitance)

• The best arrangement is case (3), i.e. to place buried layers under all the circuitry with deep contacts, although case (2) already gives substantial noise reduction

51Noise coupling

How to bias buried layers

VG


(1) D/D, A/A and E/E are bad biasing strategies for buried layers


VP


VDG or VEG


(2) D/A and E/A are good biasing strategies for buried layers


VAPVDP or VEP VAG

52Noise coupling

Design criterion for buried layers

Allow only capacitive junctions betweenburied layers under different sections

Never allow low-resistive paths betweenanalog and digital

Digital P-well & P-BL

Digital N-well & N-BL

Analog N-well & N-BL

Analog P-well & P-BL





or








or

53Noise coupling

Available buried layers in BiCMOS

NPN bipolar transistorEmitter Base CollectorPMOSNMOS

N-well contact

P-well contact

Add buried layers in CMOS process needs at least 3 extra masks (much) more expensive – also, the density of digital cells would be lower

Buried layers are available in high performance BiCMOS process (N-BL is always needed to decrease the parasitic collector resistance in npn BJTs) – the only extra mask is for the deep contact of P-BL


P-well N-well P-well N-well

P-BL N-BL N-BLP-BL

N+-con-tact

P+N+

Emitter Base Collector

P- substrate

N+P+P+

PMOSNMOS

N+N+N+P+

contactcontact

Used for insulation in high performance BiCMOS, without biasing

54Noise coupling

Triple-well nMOS in CMOS processes

N-well P-well

State-of-the-art CMOS processes provide triple-well nMOS devices for improved isolation

Deep contacts usually not available

Isolation is very good at low frequencies – decreases after a few GHz because of capacitive coupling


P-well

N-well

P- substrate

NMOS

N+N+N+P+

N-well contact

P-well contact

55Noise coupling

lec3 (substrate etc).ppt · why an 8-form coil?? p. andreani – system-on-chip n. itoh et al.,...

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