lec21 1slide per page 26nov

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Adv. Digital Design By Dr. Shoab A. Khan

The art of algorithm to architecture mapping

Adv D igital DesignBy D r. S hoab Ahmed Khan

[email protected] 2002

Sequencing and Control

Engineering Education Trust

Center for Advanced S tudies in Engineering

5-A Constitution Avenue, Software Technology Park. Islamabad, Pakistan.


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Register-based Controller with Nested Subroutine Capability

SYSCLK

N. A

NEXTADDRESSSELECT

BRANCHADDRESS

OTHER

DATA out

ADDRESS

MICROPROGRAM MEMORY2 words

n

10

3

2

10

CONDMUX

0

1cond1

BRANCHCOND

SELECT

2

NEXT ADDRESS

LOGIC

To Architecture

u P C R E G I S T E R

FULL ADDERIncrementer

n bits

S U B R

O U T I N E

R E T U R N

A D D R E S S

R E G I S T E R

Second AddressRegister

3

POLARITY

POLARITY

cond0

TOP OF STACKPOINTER up En


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Subroutine return address stack

4 levels of nesting

1 stack

Stack Pointer Reg.

Stack Pointer

clkreset

PushSP2

PopSP2

\ 10

Decoder

From PC

/

Return Address

Stack/10

2

Enable

To Next Address

Generation Unit

Incremented

Current

Incremented

Current


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Hardware Loop Machine

Stack Pointer

clkreset

PushSP1

Down Counter

\

NOR

\

10

Decoder

FromMicrocode

/

End Address

Stack/10

2

Enable

\

PC

XOR

\

10

NOR

\ 10Comparator

10

Decoder

FromPC

/

Start Address

Stack/10

2

Enable

PushSP1

\

ARn Down Counter 10 \ 10

Decoder

/

Loop CountStack/10

2

Enable

clkDec

ZeroCheck

Logic

10

10

AND

To Next AddressGeneration Unit

Push SP1

load

Current

incremented

Current

incrementedincrementedor Current

Current

//

Current

Incremented

/10

ARn

\

PushSP1

PushSP1 or load SA

reset

2

2

To Next AddressGeneration Unit

&To Loop Count

Stack

load Start Address

PopSP1 or Loop End

Flag

AND

To Stack

Pointer

Loop EndFlag

PushSP1 OLoop End

Flag

clkreset

clkreset

To DownCounter

4 levels of nesting

3 stacks

Counter, 10 bit

Stack Pointer Reg.


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Rise Delay

Gate output transition to a 1 from another value

t_rise0, x or z


6/25Adv. Digital Design By Dr. Shoab A. Khan

Fall Delay

Gate output transition to a 0 from another value

t_fall

1, x or z



Turnoff Delay

Gate output transition to the high impedancevalue (z) from another value



$setup and $hold check

Setup

time

hold

time

clock

data

The setup time is the minimum time the data must arrivebefore the active clock edge. The hold time is the minimumtime the data cannot change after active clock edge



Mix/Typ/Max Values

The delay values ranges between min and maxbecause of the IC process fabrication variation

Min valThe min value is the minimum delay value that the

designer expects the gate to haveTyp val

The typical delay value the desingner expects the gate

to have.Max value

The max delay value the designer expects the gate tohave.



Types of Delays: Distributed Delay

Delays are specified on a per element basismodule M(out, a, b, c, d);output out;input a, b, c, d;assign #5 e = a & b;assign #7 f = c & d;assign #4 out = e & f;

endmodule

ab

cd

f

e

out

M#5

#4

#7



Lumped Delay

Delay is specified on per module basis

module M(out, a, b, c, d);output out;input a, b, c, d;

assign e = a & b;assign f = c & d;assign #11 out = e & f;endmodule

a

b

c

d

f

e

out



Pin-to-pin Delays

ab

cd

f

e

out

M

Path a-e-out, delay = 9Path b-e-out, delay = 9Path c-f-out, delay = 11Path d-f-out, delay = 11

Delay are assigned individually from each input to each output



Pin-to-pin Delays- Path Delays

Delay are assigned individually from each input to each output A delay between a source pin and a destination pin of a module is calleda module path delayKeyword specify and endspecify is used for assigning path delays

module M(out, a, b, c, d);output out;input a, b, c, d;specify

(a => out) = 9;(b => out) = 9;(c => out) = 11;(d => out) = 11;

endspcifyassign e = a & b;assign f = c & d;assign #11 out = e & f;endmodule



Inside specify block: Parallel Connection

( => ) =;

bit to bit connection, a and out are single-bit(a => out) = 9

Vector connection, a[3:0], out[3:0](a => out) = 9the above statement is the shorthand notation for

(a[0] => out) = 9

(a[1] => out) = 9 (a[2] => out) = 9 (a[3] => out) = 9 Source

Field

Destination

Field

0 01 1

2 2



( *> ) = ;Each bit in the source filed connects to every bit in the destinationfield

module M(out, a, b, c, d);output out;input a, b, c, d;specify

(a, b *> out) = 9;(c, d *> out) = 11;

endspcifyassign e = a & b;assign f = c & d;assign out = e & f;endmodule

Inside specify block: Full Connection

SourceField

DestinationField

0 0

1 1

2 2



specparam statement

Special parameters is used inside a specifyblock

specifyspecparam d_to_q = 9;specparam clk_to_q = 11;

(d => q) = d_to_q



Rise, fall and turn-off delays

Pin-to-pin timing can be expressed in moredetail by specifying rise, fall and turn-off delay values.

specparam t_rise = 9, t_fall=13;

(clk => q) = (t_rise, t_fall);

specparam t_rise = 9, t_fall=13, t_turnoff=11;(clk => q) = (t_rise, t_fall, t_turnoff);



Min, max and typical delays

Min, max and typical values can also bespecified for pin-to-pin delays.

Specparam t_rise=8:9:10, t_fall=12:13:14,t_turnoff=10:11:12;

(Clk => q) = (t_rise, t_fall, t_turnoff);



An example of Min, max and typical delays

Module VAND(out, in0, in1);input in0;input in1;

output out;//timing informationSpecify(in0 => out) = (0.26:0.513:0.955,0.255:0.503:0.936);(in1 => out) = (0.26:0.513:0.955,0.255:0.503:0.936);

endspecifyand(out,in0,in1);endmodule



FPGA

Most common is a lookup table (LUT) containingstorage cells used to implement a small logicfunction

Each storage cell holds a 0 or 1LUT size is determined by the number of inputsLUT with n inputs can implement any logicfunction of n variables



Structure of an FPGA

Logic block Interconnection switches

I/O block

I/O block

I / O b l o

c k I /

O b

l o c

k


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(a) Circuit for a two-input LUT

x1

x2

f

0/1

0/1

0/1

0/1

0011

0101

1001

x1 x2

(b) f 1 x1 x2 x1 x2+=

(c) Storage cell contents in the LUT

x1

x2

1

0

0

1

f 1

f 1


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Adv. Digital Design By Dr. Shoab A. KhanFigure 3.37 A three-input LUT

f

0/1

0/10/1

0/1

0/1

0/1

0/1

0/1

x2

x3

x1


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Example

How would you implement f = abc + ac in a LUT

a b c f 0 0 0 00 0 1 0

0 1 0 10 1 1 01 0 0 01 0 1 11 1 0 01 1 1 1

f

0

01

0

0

1

0

1

b

c

a


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Inclusion of a flip-flop with a LUT

Out

D Q

Clock

Select

Flip-flopIn1

In2In3

LUT

Often a DFF is included in the logic block to store thevalue of the D Input

lec21 1slide per page 26nov

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