lc7940yc,7941yc dot-matrix lcd drivers

SANYO Electric TOKYO OFFICE Tokyo Bldg., 1

Ordering number: EN 6157

Any and all SANYO products descapplications that require extremecontrol systems, or other applicatphysical and/or material damage. any SANYO products described or

SANYO assumes no responsibilityexceed, even momentarily, rated vaparameters) listed in products speherein.

CMOS IC

LC7940YC,7941YC

Dot-matrix LCD Drivers

Overview

The LC7940YC and LC7941YC are segment driver ICsfor driving large, dot–matrix LCD displays. They read 4–

bit parallel or serial input, display data from a controllerinto an 80–bit latch, and then generate LCD drive signalscorresponding to that data.

The LC7940YC and LC7941YC feature mirror–image pinassignments, allowing them to be used together to increasecomponent density. They are designed to be used with theLC7942YC common driver to drive large LCD panels.

Features

• 80 built–in LCD display drive circuits • 1/8 to l/128 display duty cycle • Serial or 4–bit parallel data input • Chip disable for low power dissipation for large–sized

panels • Bias supply voltags can be supplied externally • Operating supply voltage and ambient temperature

- 2.7 to 5.5 V logic supply ( VDD) at Ta = –20 to +85°C- 8 to 20V LCD supply (VDD – VEE ) at Ta = –20 to

+85 °C • CMOS process

Specifications

The following electrical characteristics apply when sealed in a Sanyo standard QIC-100 package.

Absolute Maximum Ratings at Ta = 25 ± 2°C, VSS = 0 V

Parameter Symbol Ratings Unit

Logic supply voltge VDD max –0.3 to +7.0 V

LCD supply voltage, See Note below. VDD – VEE max 0 to 22 V

Input voltage VI max –0.3 to VDD + 03 °C

Co., Ltd. Semiconductor Company-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN

63099RM (ID) No. 6157—1/13

ribed or contained herein do not have specifications that can handlely high levels of reliability, such as life-support systems, aircraft’sions whose failure can be reasonably expected to result in seriousConsult with your SANYO representative nearest you before using contained herein in such applications.

for equipment failures that result from using products at values thatlues (such as maximum ratings, operating condition ranges, or othercifications of any and all SANYO products described or contained

LC7940YC, LC7941YC

NoteVDD ≥ V1 > V3 > V4 > VEE

Recommended Operating Condltions at Ta = –20 to + 85°C, VSS = 0V

Notes

1. VDD ≥ Vl > V3 > V4 > VEE

2. At turn ON, the LCD supply should be energized after or simultaneously with the logic supply. At turn OFF, the logic supplyshould be cut after or simultaneously with the LCD supply.

Electrlcai Characterfstlcs at Ta = 25 ± 2°C,VSS = 0V, VDD = 2.7 to 5.5 V

Operating temperature range Topr –20 to +85 °C

Storage temperature range Tstg –40 to +125 °C

Parameter Symbol ConditionsRatings

Unitmin typ max

Logic supply voltage VDD 2.7 – 5.5 V

LCD supply voltage VDD – VEE See Notes 1 and 2. 8 – 20 V

HIGH–level input voltage VIH

CP, CDl, DI1 to DI3, M, SDl, P/S, DISPOFF and LOAD

0.8VDD – – V

LOW–level inpvt voltage VIL

CP, CDI, Dl1 to DI3, M, SDl, P/S,DISPOFF and LOAD

– – 0.2VDD V

CP shift clock frequency fCP – 3.3 MHz

CP pulsewidth tWC 100 – – ns

LOAD pulsewidth tWL 100 – – ns

DIn and SDI to CP setup time tSETUP 80 – – ns

DIn and SDI to CP hold time tHOLD 80 – – ns

CP to LOAD timetCL1 0 – – ns

tCL2 100 – – ns

LOAD to CP time tLC 100 – – ns

CP rise time tR – – 50 ns

CP fall time tF – – 50 ns

LOAD rise time tRL – – 50 ns

LOAD fall time tFL – – 50 ns


Unitmin typ max

HIGH–level input current IIHVIN =VDD; LOAD, CP, CDI, P/S, DI1 to DI3, SDl, M, and DISPOFF

– – 1 µA

LOW–level input current IILVIN = VSS; LOAD, CP, CDl, P/S, DI1 to DI3, SDI, M, and DISPOFF

– – –1 µA

CDO HIGH–level output voltage VOH IOH = –400 µA VDD – 0.4 – – V

CDO LOW–levef output voltage VOL IOL = 400 µA – – 0.4 V

O1 to O80 driver ON resistance RON VDD – VEE = 18 V, |VDE – VO|= 0.25 V. See note

– 2 4 kΩ

Parameter Symbol Ratings Unit

No. 6157—2/13

LC7940YC, LC7941YC

NoteVDE = V1 or V3, or V4 or VEE, V1 = VDD, V3 = 9/11 × (VDD – VEE), V4 = 2/11 × (VDD – VEE)

Switching Characteristics at Ta = 25 ± 2°C,VSS = 0V, VDD = 2.7 to 5.5 V

Switching Characteristics Waveform

VDD to VSS standby supply current IST

CDI = VDD,VDD – VEE = 18 V, fCP = 3.3 MHz, no output load ; VSS

– – 200 µA

VDD to Vss operating supply current ISS

VDD – VEE = 18 V, fCP = 3.3 MHz, ILOAD= 5.156 kHz, fM = 52 Hz ;VSS

– – 1.0 mA

VDD to VEE operating supply current IEE

VDD – VEE = 18V, fCP = 3.3 MHz,fLOAD = 5,156 kHz,fM = 52 Hz ; VEE

– – 0.1 mA

CP input capacitance CI fCP = 3.3 MHz ; CP – 5 – pF


Unitmin typ max

CDO output delay time tD CL = 30 pF – – 200 ns


Unitmin typ max

SDIDI1 to 3

CP

tR tFtWC

tSETUP tHOLD

tCL (1) tCL (2) tFL

tLC

tD

tWL

tD

tRL

tWC

0.8VDD

0.2VDD

LOAD

CDO

No. 6157—3/13

LC7940YC, LC7941YC

Pad Layout (Top view)

O1O2O3O4O5O6O7O8O9

O10O11O12O13O14O15O16O17O18O19O20O21O22O23O24O25O26O27O28O29O30

O80O79O78O77O76O75O74O73O72O71O70O69O68O67O66O65O64O63O62O61O60O59O58O57O56O55O54O53O52O51

O31

O32

O33

O34

O35

O36

O37

O38

O39

O40

O41

O42

O43

O44

O45

O46

O47

O48

O49

O50

CP

CD

ILO

AD

SD

ID

I3D

I2D

I1M P

/SD

ISP

OF

FC

DO

V1

VD

D

V3

V4

VE

E

VS

S

LC7940YC



O50

O49

O48

O47

O46

O45

O44

O43

O42

O41

O40

O39

O38

O37

O36

O35

O34

O33

O32

O31

CD

OD

ISP

OF

FP

/S

M DI1

DI2

DI3

SD

ILO

AD

CD

IC

P

VS

S

VE

E

V4

V3

VD

D

V1

LC7941YC

No. 6157—4/13

LC7940YC, LC7941YC

LC7940YC Pad Locationchip size : 4.830 mm x 3.550 mm

Pin_No. Name X Y Pin_No. Name X Y

1 O1 -1600 2240 51 O51 1600 -2240

2 O2 -1600 2072 52 O52 1600 -2072

3 O3 -1600 1906 53 O53 1600 -1906

4 O4 -1600 1742 54 O54 1600 -1742

5 O5 -1600 1580 55 O55 1600 -1580

6 O6 -1600 1420 56 O56 1600 -1420

7 O7 -1600 1262 57 O57 1600 -1262

8 O8 -1600 1106 58 O58 1600 -1106

9 O9 -1600 952 59 O59 1600 -952

10 O10 -1600 800 60 O60 1600 -800

11 O11 -1600 650 61 O61 1600 -650

12 O12 -1600 502 62 O62 1600 -502

13 O13 -1600 356 63 O63 1600 -356

14 O14 -1600 212 64 O64 1600 -212

15 O15 -1600 70 65 O65 1600 -70

16 O16 -1600 -70 66 O66 1600 70

17 O17 -1600 -212 67 O67 1600 212

18 O18 -1600 -356 68 O68 1600 356

19 O19 -1600 -502 69 O69 1600 502

20 O20 -1600 -650 70 O70 1600 650

21 O21 -1600 -800 71 071 1600 800

22 O22 -1600 -952 72 O72 1600 952

23 O23 -1600 -1106 73 O73 1600 1106

24 O24 -1600 -1262 74 O74 1600 1262

25 O25 -1600 -1420 75 O75 1600 1420

26 O26 -1600 -1580 76 O76 1600 1580

27 O27 -1600 -1742 77 O77 1600 1742

28 O28 -1600 -1906 78 O78 1600 1906

29 O29 -1600 -2072 79 O79 1600 2072

30 O30 -1600 -2240 80 O80 1600 2240

31 O31 -1420 -2240 81 --- --- ---

32 O32 -1262 -2240 82 CDO 1415 2240

33 O33 -1106 -2240 83 --- --- ---

34 O34 -952 -2240 84 DISPOFF 1252 2240

35 O35 -800 -2240 85 P/S 1091 2240

36 O36 -650 -2240 86 VSS 825 2179

37 O37 -502 -2240 87 VEE 629 2179

38 O38 -356 -2240 88 V4 464 2179

39 O39 -212 -2240 89 V3 299 2179

40 O40 -70 -2240 90 --- --- ---

41 O41 70 -2240 91 VDD 123 2179

42 O42 212 -2240 92 V1 -42 2179

43 O43 356 -2240 93 M -316 2240

44 O44 502 -2240 94 DI1 -467 2240

45 O45 650 -2240 95 DI2 -620 2240

46 O46 800 -2240 96 DI3 -775 2240

47 O47 952 -2240 97 SDI -932 2240

48 O48 1106 -2240 98 LOAD -1091 2240

49 O49 1262 -2240 99 CDI -1252 2240

50 O50 1420 -2240 100 CP -1415 2240

No. 6157—5/13

LC7940YC, LC7941YC

LC7941C Pad Locationchip size : 4.830 mm x 3.550 mm

Pin No. Name X Y Pin No. Name X Y

1 O80 -1600 2240 51 O30 1600 -2240

2 O79 -1600 2072 52 O29 1600 -2072

3 O78 -1600 1906 53 O28 1600 -1906

4 O77 -1600 1742 54 O27 1600 -1742

5 O76 -1600 1580 55 O26 1600 -1580

6 O75 -1600 1420 56 O25 1600 -1420

7 O74 -1600 1262 57 O24 1600 -1262

8 O73 -1600 1106 58 O23 1600 -1106

9 O72 -1600 952 59 O22 1600 -952

10 O71 -1600 800 60 O21 1600 -800

11 O70 -1600 650 61 O20 1600 -650

12 O69 -1600 502 62 O19 1600 -502

13 O68 -1600 356 63 O18 1600 -356

14 O67 -1600 212 64 O17 1600 -212

15 O66 -1600 70 65 O16 1600 -70

16 O65 -1600 -70 66 O15 1600 70

17 O64 -1600 -212 67 O14 1600 212

18 O63 -1600 -356 68 O13 1600 356

19 O62 -1600 -502 69 O12 1600 502

20 O61 -1600 -650 70 O11 1600 650

21 O60 -1600 -800 71 O10 1600 800

22 O59 -1600 -952 72 O9 1600 952

23 O58 -1600 -1106 73 O8 1600 1106

24 O57 -1600 -1262 74 O7 1600 1262

25 O56 -1600 -1420 75 O6 1600 1420

26 O55 -1600 -1580 76 O5 1600 1580

27 O54 -1600 -1742 77 O4 1600 1742

28 O53 -1600 -1906 78 O3 1600 1906

29 O52 -1600 -2072 79 O2 1600 2072

30 O51 -1600 -2240 80 O1 1600 2240

31 O50 -1420 -2240 81 CP 1415 2240

32 O49 -1262 -2240 82 CDI 1252 2240

33 O48 -1106 -2240 83 LOAD 1091 2240

34 O47 -952 -2240 84 SDI 932 2240

35 O46 -800 -2240 85 DI3 775 2240

36 O45 -650 -2240 86 DI2 620 2240

37 O44 -502 -2240 87 DI1 467 2240

38 O43 -356 -2240 88 M 316 2240

39 O42 -212 -2240 89 V1 42 2179

40 O41 -70 -2240 90 VDD -123 2179

41 O40 70 -2240 91 --- --- ---

42 O39 212 -2240 92 V3 -299 2179

43 O38 356 -2240 93 V4 -464 2179

44 O37 502 -2240 94 VEE -629 2179

45 O36 650 -2240 95 VSS -825 2179

46 O35 800 -2240 96 P/S -1091 2240

47 O34 952 -2240 97 DISPOFF -1252 2240

48 O33 1106 -2240 98 --- --- ---

49 O32 1262 -2240 99 CDO -1415 2240

50 O31 1420 -2240 100 --- --- ---

No. 6157—6/13

LC7940YC, LC7941YC

Block Diagram

Pin Functions

Pin No.Symbol I/O Function

LC7940YC LC7941YC

91 90 VDD

SupplyVDD – VSS is the logic supply.VDD – VEE is the LCD supply.

86 95 VSS

87 94 VEE

92 89 V1

SupplyLCD panel drive voltage supplies V1 and VEE are selected levels. V3 and V4 are not–selected levels.

89 92 V3

88 93 V4

l00 81 CP I Display data Input clock (falling–edge trigger).

99 82 CDI IChip disable. Data is read in when LOW, and not road in when HIGH.

98 83 LOAD IDisplay data latch clock (falling–edge trigger). On the falling edge, the LCD drive signals set by the display data are output.

97 84 SDI I Serial data input.

96 85 DI3

I

4–bit parallel data input pins.

In serial data input mode, DI1 to DI3 should all be tied HIGH or LOW.

95 86 DI2

94 87 D11

4 Level LCD Drive Circuit

(80 bits)

Level Shifter (80 bits)

2nd Latch (80 bits)

1st Latch (80 bits)

Address Decoder4 bits

Data Bus

Interface Address Counter(7 bits)

Chip Disable &Latch Control

SER/PARControl

CLK

80

80

80

204

V1

01 02 03 079 080

V3

V4

M

SDI

DI3

DI2

DI1

P/S CDO

DISP OFF

VSS

VDD

CDI

CP

LOAD

VEE

Data input LCD driver outputs

SDI O4 O8

O80

DI3 O3 O7 O79

DI2 O2 O6 O78

DI1 O1 O5 O77

No. 6157—7/13

LC7940YC, LC7941YC

93 88 M I LCD panel drive voltage output alternation control signal.

85 96 P/S I Data input mode select. 4–bit parallel input when HIGH, and serial input when LOW

82 99 CDO OCascade connection pin for extension segment drivers. Data is read out when HIGH.Goes LOW after data is read out. Connected to the CDI input of the next chip.

1 to 80 80 to 1 Ol to O80 O

LCD drive outputs.The output drive level is determined by the display data, M signal and DISP OFF input as shown below.

Note

x = don’t care (tied HIGH or LOW)

84 97 DISPOFF IO1 to O80 output control input pin.When LOW, V1 is output on the O1 to 080 outputs, See the truth table.

81 91 NC

– No connection.83 98 NC

90 100 NC

Pin No.Symbol I/O Function

LC7940YC LC7941YC

M Q DISP OFF Output

LOW LOW HIGH V3

LOW HIGH HIGH V1

HIGH LOW HIGH V4

HIGH HIGH HIGH VEE

× × LOW V1

No. 6157—8/13

LC7940YC, LC7941YC

Application Notes

LCD Panel 1

+–

2O

D1

ED

1

CD

I

CP

SD

ILO

AD

CP

SD

ILO

AD

V3

V1

M

M

CD

OC

DI

V1

V4

(LC

7940

YC

)LC

7941

YCV

3

V4

VE

E

VE

E

CP

SD

ILO

AD

V3

V1

M

M

CD

OC

DI

V1

V4

(LC

7940

YC

)LC

7941

YCV

3

V4

VE

E

VE

E

CP

SD

ILO

AD

V3

V1

M

M

CD

OC

DI

V1

V4

(LC

7940

YC

)LC

7941

YCV

3

V4

VE

E

VE

E

CP

SD

ILO

AD

V3

V1

M

MV

1

V4

(LC

7940

YC

)LC

7941

YCV

3

V4

VE

E

VE

E

CP

LOA

D4

640

639

482

481

480

479

322

321

320

319

162

161

160

159

2

1

1280

1279

1122

1121

1120

1119

962

961

960

959

802

801

800

799

642

641

M

V1

V4

LC79

40Y

C

(LC

7941

YC

)

LC79

41Y

CV

3V

EE

M

V1

V4

LC79

40Y

C

(LC

7941

YC

)

LC79

41Y

CV

3V

EE

M

V1

V4

LC79

40Y

C

(LC

7941

YC

)

LC79

41Y

CV

3V

EE

M

V1

V1

V3

V4

LC79

40Y

C

(LC

7941

YC

)

LC79

41Y

CV

3V

EE

VE

E

–11

to –

13V

V4

VE

E

V1

V1

46

V2

R R R

7R

R

V3

V4

V5

4

4

V2

V5

LA53

11M

VE

E

VD

D

OD

2 E

D2

CP

LOA

DM

4

V1

DI0

1

DI0

64

LC79

42Y

C 064

CP

M01

DI0

1

LC79

42Y

C 036

CP

M01

V2

V5

VE

E10

0

4

OD

1

ED

1

FLM M

cont

rolle

r

CL1

CL2

OD

2

ED

2

LCD

pan

el (

640

× 20

0 pi

xels

)

+– +– +–

No. 6157—9/13

LC7940YC, LC7941YC

LCD Panel 2

CD

I

CD

OLC

7941

YC

-#8

LC79

41Y

C-#

2LC

7941

YC

-#1

24

M2

4V

1V

4

LC79

41Y

C-#

1

080

01

080

01

CD

IC

DO

CP

LO

AD

CP

LO

AD

4bit

Dat

a

4bit

Dat

a

V3

VE

E

LC79

41Y

C-#

2

V1

V3

LC79

41Y

C-#

8

VE

E

–11

to –

13V

V4

VE

E

V1

V1

46

V2

R R R R

V3

V4

V5

4

4

V2

V5

LA53

11M

VE

E

VD

D

4

42

DI0

1

LC79

42Y

C-#

1064

CP

M01

DI0

1

LC79

42Y

C-#

2036

CP

M01

100

100

4bit

Dat

a

FLM M

cont

rolle

r

LOA

D

CP

4bit

Dat

aLC

D p

anel

(64

0 ×

200

pixe

ls)

7R

22

42

44

4 4

24

24

MV

1 V

3V

4 V

EE

– + – + – + – +

No. 6157—10/13

LC7940YC, LC7941YC

100 x 240-pixel LCD Panel Application

A 100 × 240–pixel LCD panel requires the following drivers.

• 3 x LC7940YC (or LC7941YC) drivers• 2 x LC7942YC drivers

An example using l/l00 duty cycle is shown below.

1. The LC7942YC chips are cascaded by connectingDIO64 on chip I to DIO1 on chip 2. For a 100–bit shiftregister, O37 to O64 on chip 2 are left open.

2. The LC7940YC (or LC7941YC) chips are cascaded byconnecting CDO on chip I to CDI on chip 2, and CDOon chip 2 to CDI on chip 3. CDI on chip I is tied toGND, and CDO on chip 3 is not used. Thisconfiguration allows the input of 240–bit serial data.

Frame Signal

1,1

2,1

63,1

64,1

65,1

66,1

100,1

DI01 01RS/LS 02LC7942YC

#1

063

DI064 064

DI01 01RS/LS 02

LC7942YC

#2

036

DI064

1,2

2,2

63,2

64,2

65,2

66,2

100,2

1,79

100,79

1,80

64,80

65,80

100,80

1,81

64,81

65,81

100,81

1,82

100,82

1,160

64,160

65,160

100,160

1,161

64,161

65,161

100,161

1,240

2,240

64,240

65,240

100,240

CPM

CPM

01

O37 to O64 are open.

Dat

a la

tch

cloc

k

Alte

rnat

ing

sign

al

Ser

ial D

ata

Dat

a S

hift

cloc

k

02

LC7940YC(LC7941YC)

079

#1

080

CDOCDI

---

---

---

---

--- ---

LCD Panel (100 × 240 pixels)

1,79 (m,n) : pixel address

Segment line (n)Common line (m)

P/S

DI1

DI2

DI3

SD

I

CP

LOAD

M

01 02

LC7940YC(LC7941YC)

#2

080

CDOCDI

P/S

DI1

DI2

DI3

SD

I

CP

LOAD

M

01

LC7940YC(LC7941YC)

#2

080

CDOCDI

P/S

DI1

DI2

DI3

SD

IC

PLO

ADM

---

---

---

---

---

---

---

---

--- ---

--- ---

--- ---

No. 6157—11/13

LC7940YC, LC7941YC

100 x 240-pixel LCD Panel Timing Diagram

M

LOAD

CP

M

LOAD

SDI

CP

M

#1 DIO1

#1

#2

#3

01

01

080

01

080

02

080

LOAD

1,1

#1

Chip 1 data read

1st line data read 2nd line data read

1frame (100 × 240 bits)

1 frame (240 bits)

Chip 2 data read Chip 3 data read

#2

#3

1,2 1,79 1,80 1,81 ------

1,1

1,1 2,1

1,2 1,239

98,1 99,1 99,1100,1 100,11,1

1,240 2,240 3,1 100,2402,1---

--- ---

1,2 2,2 98,2 99,2 99,2100,2 100,21,2--- ---

1,80 2,80 98,80 99,80 99,80100,80 100,801,80--- ---

1,81 2,81 98,81 99,81 99,81100,81 100,811,81--- ---

1,160 2,160 98,160 99,160 99,160100,160 100,1601,160--- ---

1,161 2,161 98,161 99,161 99,161100,161 100,1611,161--- ---

1,240 2,240 98,240 99,240 99,240100,240 100,2401,240--- ---

--- ---

---1,160 1,161 1,240SDI

SDO

------

LCD

driv

er o

utpu

t dat

a

No. 6157—12/13

LC7940YC, LC7941YC

Segment Data Not Multiples of 4 Example.

If this timing data is sent, data elements (m, 229), (m,230), (m+1, 229), (m+1. 230)... will not appear in theoutput (O69 and O70 on chip 3). This is because theLC7940YC (or LC7941YC) converts serial/parallel data

in 4–bit units, which also decreases power dissipation . Fordata that is not a multiple of 4, like 230, the followingscheme is used.

In this case, (m, 231) is output on O71 on chip 3, and (m,232) on O72 on chip 3. However, these outputs are notconnected to the panel and are, therefore, invalid.

LCD panel (100 × 230 pixels)

01 080

---

LC7940YC#1

01 080

LC7940YC#2

---

01 070

LC7940YC#3

LOAD

SDI m,1 m,2 ,228 m,229 m,230 m+1,1 m+1,2 m+1,229 m+1,230,228---

LOAD

SDI m,1 m,2 ,228 m,229 m,230 m,231 m,232

Dummy dataValid display data

Multiple of 4

---

No. 6157—13/13

This catalog provides information as of June, 1999. Specifications and information herein are subject tochange without notice.

Specifications of any and all SANYO products described or contained herein stipulate the performance,characteristics, and functions of the described products in the independent state, and are not guaranteesof the performance, characteristics, and functions of the described products as mounted in the customer’sproducts or equipment. To verify symptoms and states that cannot be evaluated in an independent device,the customer should always evaluate and test devices mounted in the customer’s products or equipment.

SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and allsemiconductor products fail with some probability. It is possible that these probabilistic failures could giverise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or thatcould cause damage to other property. When designing equipment, adopt safety measures so that thesekinds of accidents or events cannot occur. Such measures include but are not limited to protective circuitsand error prevention circuits for safe design, redundant design, and structural design.

In the event that any or all SANYO products(including technical data,services) described or containedherein are controlled under any of applicable local export control laws and regulations, such productsmust not be exported without obtaining the export license from the authorities concerned in accordancewith the above law.

No part of this publication may be reproduced or transmitted in any form or by any means, electronic ormechanical, including photocopying and recording, or any information storage or retrieval system, orotherwise, without the prior written permission of SANYO Electric Co. , Ltd.

Any and all information described or contained herein are subject to change without notice due toproduct/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" forthe SANYO product that you intend to use.

Information (including circuit diagrams and circuit parameters) herein is for example only ; it is notguaranteed for volume production. SANYO believes information herein is accurate and reliable, but noguarantees are made or implied regarding its use or any infringements of intellectual property rights orother rights of third parties.

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