layout using virtuoso

8/11/2019 Layout Using Virtuoso

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Lab 3 Layout Using Virtuoso Layout

XL (VXL)This Lab will go over:

1. Creating layout with Virtuoso layout XL (VXL).

2.

Transistor Chaining.

3. Creating Standard cell.

4.

Manual Routing

5. Providing Substrate or Bulk Connection.

1. Creating layout with Virtuoso layout XL (VXL)

We will be using PCELLs developed by NCSU to layout a 2 inputs nand gate, denoted as nand2.

If you are not running CDS tools, do so according to Lab 1.

First we need to create a layout view of our nand2. Go to the library manager and execute(LM)File>New>Cell View. A pop-up like Figure 1 should appear. Fill out the pop-upexactly as in Figure 1, then click OK. The Virtuoso layout editor (VLE) will open as shown inFigure 2.

Figure 1: Creating layout view of nand2


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Figure 2: Virtuoso Layout Editor (VLE)


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Figure 3: LSW

The Layer Select Window (LSW) will also open as shown in Figure 3. This window shows all theavailable layers that you can use in creating your layout in the AMI06 process. If you dont see it, itmay be hidden under another window. Re-size each window and re-arrange so that window willbe visible.


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To make sure that all layers will appear in LSW, execute (VLE) Options>Display. A pop-upwill display as in Figure 4, make sure in theArray Display area that the Full radio button isselected. Note that X snap spacing and Y snap spacing should indicate lambda (* 0.3)=.15for AMI06 process. Set the pop-up according to Figure 4 and click OK.

Figure 4: Setting Display Options

We will be using the Virtuoso Layout XL (VXL), to help us in creating the layout. This is aschematic driven layout. To invoke VXL, in the layout editor execute (VLE)Launch>LayoutXL. A schematic window showing nand2 schematic will display as shown inFigure 5.


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Figure 5: Nand2 schematic

To put the components shown in the schematic window into the layout editor, execute (VXL)connectivity>Generate> All from Schematic. A pop-up will display as in Figure 6. Note allsignal I/O pins must be on metal2 layer, power rails (mygnd and myvdd) must be on metal1 layer,and default layer on metal2. In addition, the Create button for mygnd and myvdd must be de-selected. This means that we will do our own placement of mygnd and myvdd. Metal2 is neededfor signal I/O pins, to enable the downstream automatic layout generator to successfully layout ofa 2-input exclusive or gate (xor2), which consists of inverters and nand2 gates to be discussed inlab 5. Complete the pop-up exactly as shown in Figure 6, then click OK.


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Figure 6: Display Pin Name Option pop-up


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The initial component and pin placement is displayed in Figure 7. The components and pins areshown outside a bounding box. This bounding box is an estimate of the optimum size of the finallayout. Automatic router to be discussed in Lab 5 will use the bounding box to constraint allrouting to occur within the box. The bounding box may need to be re-sized to satisfy our goal ofcreating standard cells. Standard cells are cells that are created to have the same height, so that

when abutting two standard cells both power rails will connect.

Figure 7: Initial component and pin placement


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Place the component and pin within the bounding box in their relative position as in theschematic, execute. For that execute the (VXL) connectivity->Generate->Place as inSchematic. Figure 8 shows the resulting placement within the bounding box. The bounding boxsize was estimated based on 4 individual transistors. In this lab, we will introduce transistorchaining, a process of combining two transistors of the same type to share a common substrate.

Figure 8 shows the components in level 0 (outline only). To display all levels, press(Shift) f

key.To go back to level 0, press (Ctrl) fkey.


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Figure 8: Component and pin placement within the bounding box

2. Transistor Chaining

Figure 9 shows the two pmos transistors with all layers prior to chaining. To determine howchaining should be done, we must first determine how the transistors are interconnected. This isachieved by selecting a transistor (by clicking on it), then put and click the cursor on the selectedtransistor until the cursor change to four arrow icon, move the transistor. As you move thetransistor, flight line in bright yellow will appear indicating its interconnection. For chaining thetwo parallel pmos transistors, we want to combine the drain of transistor M0 and M1 as shown inthe schematic. The drain of M0 and M1 are both connected to output pin Y. Most likely theinitial transistor configuration will be as follows: M1=|S1|G1|D1| and M0=|S0|G0|D0|. Inchaining we like to combine D1and D0. To achieve this, we need to flip transistor M0, so that itsnew configuration becomes M0=|D0|G0|S0|. So that after transistor chaining, the combinetransistor configuration of M1M0 is |S1|G1|D1/ D0|G0|S0. To flip transistor M0, first selectM0 then execute (VXL)Edit>Move. A move pop-up will open with three buttons: Rotate(Rotate 90 CCW), Sideways (Flip horizontally), and Upside Down (Flip Vertivally). Select

Sideways to flip horizontally. Figure 10 shows the result of flipping M0 and chaining M0 and M1.The chaining is achieved by aligning the contacts. To make sure that the chaining process isproperly done perform a DRC check by executing (VXL)Verify>DRC. A pop-up will display,accept the default setting by clicking OK. Check the CIW window for no error message. If thereare errors, they will be highlighted in the VXL window. Correct them before proceeding.


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Figure 9: The two parallel pmos cells prior to chaining


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Figure 10: Two pmos cells after chaining


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Similarly chain the two series connected nmos transistors, M3 and M2. In the schematic, it showsthat we need to combine or chain the source of M3 (S3) and the drain of M2(D2). The initialtransistor configuration is most likely will be M2=|S2|G2|D2|and M3=|S3|G3|D3|. The desiredfinal configuration of the combined transistor M2M3 is |S2|G2|D2/ S3|G3|D3|. That is, notransistor flipping is required, but must make sure that M3 is to the right of M2. Figure 11 shows

the results of chaining the transistors and approximate placement of pins.

2. Creating Standard Cell

Figure 11 also shows the placement of power rails mygnd, myvdd, and nwell. To aid in thecreation of standard cells, the placement of power rails should always be in the same height. Thisis achieved by a macro name pr. This macro is executed in the CIW window by typingprin theCIW command line. The created power rail pins can be verified. Click on the upper metal1, toverify that it corresponds to myvdd pin, as display on the CIW window. Similarly, the lowermetal1 corresponds to mygnd pin. The bounding box is re-sized to match the height of thepower rails, by executing (VXL)Edit>Stretch, click once on the top edge of the bounding box,the edge will be highlighted, move the edge to match the top of the power rail myvdd, then click

once to end the stretch operation. Similarly, move the right edge of the bonding box to match theright edge of the power rails. The macro pr was created with nand2 cell layout in mind. In otherstandard cell layout (say inverter), the right edge of the power rails may need to be moved also.Figure 11 shows a ruler drawn to the left off the bounding box. The ruler is created by executing(VXL) Tools>Create Ruler. Click once on the horizontal axis, and then move vertically towardthe top edge of the bounding box. The unit of ruler is in micron (u). Place the pins (B, A, Y) atabout 15u. The ruler marker is not part of the layout and is not saved when saving the layout. Themarker can be cleared by executing (VXL) Tools>Clear Ruler.


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Figure 11: Power rails placement and re-sizing of bounding box


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4. Manual Routing

Select the chained nmos transistors together, and move it to show the flight lines. The flightlines will indicate that both corresponding gates of nmos and pmos need to be connectedtogether. Press p key to initiate the path command. In the LSW window select the poly layer.

Initiate the poly path by clicking once at the bottom end of the poly gate of the pmos transistorand double click at the top end of the poly gate of the nmos transistor. Repeat the operation forthe right pmos/nmos gate pair. If the pmos/nmos gate pair dont lign-up, select the chainednmos pair together, move them to lign-up as shown in Figure 12.

Figure 12.: Creating poly path


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To connect the input pin (on metal2 layer) to the gate (on poly layer), we need to establish acommon layer to provide the connection. The poly layer can connect to metal1 layer by creating am1_poly contact, and metal2 layer can connect to metal1 layer by creating a m2_m1 contact (via).Then the two contacts can be connected using metal1 path. Create the m1_poly contact byexecuting (VXL)Create>via. A pop-up will display, in contact type select M1_POLY as shown

in Figure 13.

Figure 13: Creating metal1 to poly contact.

Place the two contacts at around 18u as shown in Figure 14. This figure also shows that each pinhas been moved right on top of each corresponding poly gate layer. Create metal1 path bypressing p key and selecting metal1 in LSW. To start the metal1 path, click once on them1_poly contact and double click on the M2 pin. Note each pin will be covered by M2_M1contact (via) to complete the connection. Repeat for the other m1_poly contact and M2 pin. Forthe output pin Y connection, it has to be connected to the drain of the chained pmos transistorpair (at the middle) and the drain of the chained nmos transistor pair ( at the right). Create themetal1 path, and connect the path for pin Y as shown in Figure 15.


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Figure 14: Creating m1_poly contacts


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Figure 15: Metal1 path connections


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Create M2_M1 contact (via) as in Figure 13 by selecting contact type to be M2_M1. Click once toplace the contact on top of each pin. Press ESC key when done. Figure 16 shows the finalplacement of contact on pin.

Figure 16: Adding M2_M1 contact on each pin


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5. Providing Substrate or Bulk Connection

To provide a low ohmic contact to the nwell substrate, where pmos transistor resides, NCSU hasprovided ntap to achieve this. Press i to enter the add instance mode. A pop-up appears as inFigure 17. Click Browseand select the NCSU_TechLib_ami06library, then select ntapin the

cell column. Stamp the ntap between the myvdd and nwell, place two-ntap as shown in Figure 18.

Figure 17. Retrieving ntap


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Figure 18. Stamping ntap

Similarly, retrieve ptap from the NCSU_TechLib_ami06 to provide low ohmic contact to thepwell substrate. In the ami06 technology, the pwell is not drawn because the entire area isassumed to be the pwell substrate. Stamp the ptap between mygnd and pwell substrate (notdrawn), place two-ptap as shown in Figure 19.


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Figure 19. Stamping ptap

There are three remaining connections. The two sources of the pmos chained pair (M0,M1) needto be connected to myvdd. The source of transistor M2 needs to be connected to mygnd. Figure20 shows the completed nand2 layout.


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Figure 20: Complete nand2 layout


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Assignment:

Create the layout of the inverter (inv) as in Figure 21.

Figure 21: Completed Inv Layout


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layout using virtuoso

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