layout of the power distribution on support tube for phase i 29. 08. 2012 lutz feld, waclaw...

Layout of the Power Distribution on Support Tube

for Phase I

29. 08. 2012

Lutz Feld, Waclaw Karpinski, Katja Klein,

Jan Sammet, Michael Wlochal

Pixel Phase-I Powering System

2Waclaw Karpinski Grindelwald

Support Tube

3

• two half shells of each side of the pixel detector• 8 slots/half shell equipped with power distribution and readout and control

electronics• up to 26 DCDC converters per slot located in segment A

• CO2 cooling pipes pass through slots and are used to cool DCDC converters and optohybrids

• the middle slot is equipped with BPIX cooling pipes and auxiliary power cables

26 DC-DC Converters

14 x POH

DOHs+TPLLs+Delays25

Connector Boards

Pixel modul cables

Adapter Boards

CCUM

Waclaw Karpinski Grindelwald

Power distribution in a slot

4

Segment A

Segment B

Segment CSegment B

Bus Board with DCDC Converters

Connector Board L4Extensions Boards

Connector Board L3

Connector Board L1&L2

Module Cables

Multiservice Cables

• “Bus-Board” equipped with up to 26 DCDC-converters in segment A • segment B equipped with 2 x Extension Boards• segment C equipped with 2 x „adapter boards“, 3 x „connector boards“• copper cladded aluminium wires Ø 360 µm across segment D• Long distance of 2.2m from flange to detector modules


5

Converter Bus Board

layer 1

layer 4

layer 2

layer 3

slow control connector (DF20F-30DP-1H)

digital converter

analogue converter

served by cable 1

served by cable 2

cable 2

cable 1

• Bus Board distributes power and controls to

DCDC converters

• transmits bias voltages

• converters organized in 13 pairs (analog and digital)

• two MSC power the DCDC converters of one slot

60

Rigid part of

the cable


6

Converter Bus Board

• power dissipation ~ 35W per slot

• anodized aluminium cooling bridges screwed around CO2 cooling pipes used to cool

the converters

• the cooling bridges are electrically insulated from the converters

• 8-layer PCB

• Cu thickness: 70 µm per layer

• size: 488mm x 40mm x 1.6mm


Tests of the Bus-Board Prototype

7

a prototype board for 16-facette version under test, using dummy loads

- Temperature checked with infrared camera, looks ok

- Voltage drops across board agree reasonably well with calculations


Accelerated aging studies

8

• Cycles with bus board and converter dummies under nominal load

• 4 cycles per day, -10°C to +40°C (coolant temperature)

• Test duration: 30 days


Accelerated aging studies

9

L1C1D

1

L1C1D

2

L4C1D

4

L4C1D

5

L4C1D

6

L2C2D

1

L2C2D

2

L2C2D

3

L3C2D

4

L3C2D

5

L3C2D

6

L1C1A

1

L1C1A

2

L4C1A

3

L4C1A

4

L4C1A

5

L2C2A

1

L2C2A

2

L2C2A

3

L3C2A

4

L3C2A

5

L3C2A

60.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

40.0

45.0

50.0Callculated

Measured before TC

Measured after TC

DC-DC converter position

V_

dro

p o

n b

us

bo

ard

po

we

r lin

es

[m

V]

Voltage drop on bus board is as expected

No change in quality of connections after 120 thermal cycles within 30 days


Segment B

10

Extension Board L1&L2753mm x 40mm x 05mm

Crossover A-BCrossover B-C

• Extension boards are flexible two-metal-layer kapton pcbs• Contain in total 26 power rails+2 Power_Return_Rails+15 HV lines+ 4HV_GND lines• Cu thickness = 100 µm• Isolation made by two layers of Vacrel-Soldermask


Extension Board L3&L4746.5mm x 40mm x 0.5mm

Supply Currents and Voltages at the ROCs

11

Expected max. Digital Supply Current [A

]

[A]

Expected max. Analog Supply Current

L1C1D

0

L1C1D

1

L1C1D

2

L4C1D

3

L4C1D

4

L4C1D

5

L4C1D

6

L2C2D

7

L2C2D

8

L2C2D

9

L3C2D

10

L3C2D

11

L3C2D

120

0.5

1

1.5

2

2.5

3

L1C1A

0

L1C1A

1

L1C1A

2

L4C1A

3

L4C1A

4

L4C1A

5

L4C1A

6

L2C2A

7

L2C2A

8

L2C2A

9

L3C2A

10

L3C2A

11

L3C2A

120

0.4

0.8

1.2

1.6

2

Expected Analog Supply Voltage

[V]

Expected Digital Supply Voltage

[V]

Calculations made for converter input voltage =10V, analogue c. output =2.5V, digital c. output = 3.0V, efficiency = 80%, Luminosity = 2x 1034

L1C1D

0

L1C1D

1

L1C1D

2

L4C1D

3

L4C1D

4

L4C1D

5

L4C1D

6

L2C2D

7

L2C2D

8

L2C2D

9

L3C2D

10

L3C2D

11

L3C2D

122.200

2.300

2.400

2.500

2.600

L1C1A

0

L1C1A

1

L1C1A

2

L4C1A

3

L4C1A

4

L4C1A

5

L4C1A

6

L2C2A

7

L2C2A

8

L2C2A

9

L3C2A

10

L3C2A

11

L3C2A

121.600

1.700

1.800

1.900

2.000

2.100


absolute minimum absolute minimum

• voltage margin ~160 mV for digital supply and ~ 300 mV for analog supply

Calculated max. Voltage Drop on Power Lines

12

Digital Lines

Analog Lines

[V]

[V]

L1C1D

0

L1C1D

1

L1C1D

2

L4C1D

3

L4C1D

4

L4C1D

5

L4C1D

6

L2C2D

7

L2C2D

8

L2C2D

9

L3C2D

10

L3C2D

11

L3C2D

120.000

0.050

0.100

0.150

0.200

0.250

0.300

0.350

Segment A

Segment B

Segment C

Segment D

L1C1A

0

L1C1A

1

L1C1A

2

L4C1A

3

L4C1A

4

L4C1A

5

L4C1A

6

L2C2A

7

L2C2A

8

L2C2A

9

L3C2A

10

L3C2A

11

L3C2A

12-0.050

0.000

0.050

0.100

0.150

0.200

0.250

0.300

0.350

Segment A

Segment B

Segment C

Segment D


Control of DCDC Converters

13

• each converter has one power good output and one enable input

• control will be made via the parallel IOs of CCU

• converters will be controlled by pairs: an analogue and a digital converter feeding power to the same pixel modules

• one CCU controls 13 converter pairs and 2x mDOH + 2xTPLL + 2 x Delay25 ASICs located in one slot

• the control-ring will be a flexible kapton pcb equipped with 2 x DOHs, 9 x CCUs and 9 x LVDSMUX

13location of the CCU-rings in a slot

46 mm


Grounding

14

• The dcdc conveters of one slot are powered from one PS A4603

• One A4603 houses two ”Power Supply Units” PSU0 and PSU1, delivering two HV channels with common floating return and two LV channels (analog and digital supply ) also with common floating return each

• The LV-returns of the two PSU are short circuited on the Bus Board→There is only one LV-Return in a slot

• One floating auxiliary power channel powers the control components corresponding to one slot

• The control ring is powered by one floating power channel

• the electronics installed in a slot should be grounded at one point

• the grounding points of all slots should be interconnected

• the grounds of both half shells should be interconnected


Grounding schema

15

Vdrop 60mV 90mV 60mV 100mV

• Common Ground should be located as close as possible to the detector

• the voltage difference between CCU_GND and Converter_GND should be <0.2V

→ two options: Common Ground at the transition between segments B and C

or alternatively at the transition between segments A and B

• The pixels modules must be isolated from the support structure


46A

HV - Isolation

16

• all HV lines (15) are arranged in 4 groups : L1 & L2 (1000V) and L3 &L4 (600V)

• the isolation distance between groups = 0.5 mm in min. safe up to 600V according to IPC 2221

• the clearance between HV-lines in a group = 0.25 mm safe up to 500V according to IPC 2221

• clearance between the connectors HV-Pins = 0.63mm → safe up to 150V according to IPC 2221

0.63


HV-Isolation

17

600V 0.5mm 1.0mm 1.0mm 1.8mm1000V 1.5mm 2.2mm 2.2mm 3.0mm

Inner layer surface of pcbunder a solder mask

components leads coated

components leads uncoated

• IPC 2221 defined clearances:

• Need to define HV-insulation rules with reduced clearances which will still guarantee safe functionality of pixel electronics

• On Pixel-HDI the clearances amount to 0.6mm in air and 0.37 mm under the solder mask.

• In the cable connector in PP1/PP0 the clearance amounts to 1.76mm


Proposal with improved HV - insulation

18

Additional flexible board containing all HV Lines and HV - Returns

Connector BoardLayer 1 & 2

Connector Board Layer 3

Connector Board Layer 4

Size: ~1330mm x 35mm x 0.3 mm

New HV-Board

New HV-Board

Bus-Board


• integration of power system on support tube is in progress

• prototype of Bus-Board has been build and tested

- measured voltage drops across board agree reasonably well with calculations

- accelerated aging study show no changes in quality of connections after 120 thermal cycles within 30 days

• calculated voltage drops on power rails can be tolerated

– expected safety margin ~160 mV for digital and 300 mV for analog supply at the ROCs

• New design with improved HV – Isolation performance is proposed

• There is a need to define HV-isolation rules with reduced clearances which will guarantee safe operation of the electronics in Pixel-Detector environment

Summary

Waclaw Karpinski Grindelwald 19

Grindelwald 20

Buck-Up Slides

Waclaw Karpinski

21

DCDC-Converter (present version)

PCB:2 copper layers a 35µm0.3mm thickLarge ground area on backside for cooling

Toroidal Inductor:L = 450nHRDC = 40m

Shield/heat sinkcopper-plated plastic capsoldered to pcb

AC_PIX_V8 A2.8cm x 1.6cm; ~ 2.0g

Pi-filters at in- and output

ASIC : AMIS4 by CERNIout < 3AVin < 10VVout configurable; (here: 2.4V & 3.0V)fs configurable, e.g. 1.5MHz


AMIS4 ASIC

22

Features:• Bandgap and 4 linear regulators integrated• Dead time handling with adaptive logic• Triplication and logic against SEU• Improved power transistor design wrt TID• Over-current protection• Over-temperature protection• Input under-voltage protection• State machine for soft start-up procedure, handling of protection• Power Good output• Enable input


HV Lines


24

Power distribution crossover B-C

Print A(Layer 1 & 2)

Print B (Layer 3)

Print C (Layer 4)

Power Bus Layer 1 & 2

Power Bus Layer 3 & 4

mDOH & PLL & Delay25


25

Calculated Voltage Drop on Power Lines for Layer 1 & 4

Calculations are made for converter input voltage =10V, analogue c. output =2.5V, digital c. output = 3.0V, efficiency = 80%at the ROC input nominal analogue voltage = 1.6V and nominal digital voltage = 2.2VLuminosity = 2 x 1034

Pos. Converter Net Name

Converter Output Current

Voltage Drop Sector A 8 Layers

(70 µm Cu )

Voltage Drop Sector B 2 Layers

(100 µm Cu )

Voltage Drop Sector C 4 Layers

(35 µm Cu )

Voltage Drop Sector D AL-Draht Ø

350 µm

Voltage Drop Total in

Sectors A-D

Voltage at the ROC

[A] [V] [V] [V] [V] [V] [V]0 L1C1D0 D0C1 1.32 0.034 0.167 0.055 0.328 0.584 2.416 1 L1C1D1 D1C1 1.32 0.041 0.167 0.055 0.328 0.591 2.409 2 L1C1D2 D2C1 1.32 0.048 0.167 0.055 0.328 0.597 2.403 3 L4C1D3 D3C1 2.461 0.067 0.208 0.132 0.175 0.581 2.419 4 L4C1D4 D4C1 2.461 0.073 0.209 0.132 0.175 0.589 2.411 5 L4C1D5 D5C1 2.461 0.083 0.209 0.132 0.175 0.598 2.402 6 L4C1D6 D6C1 2.461 0.087 0.209 0.132 0.175 0.603 2.397

0 L1C1A0 A0C1 0.48 0.024 0.170 0.041 0.281 0.516 1.984 1 L1C1A1 A1C1 0.48 0.030 0.170 0.041 0.281 0.522 1.978 2 L1C1A2 A2C1 0.48 0.036 0.169 0.041 0.281 0.527 1.973 3 L4C1A3 A3C1 1.92 0.063 0.170 0.093 0.220 0.546 1.954 4 L4C1A4 A4C1 1.92 0.070 0.170 0.093 0.220 0.553 1.947 5 L4C1A5 A5C1 1.92 0.073 0.170 0.093 0.220 0.556 1.944 6 L4C1A6 A6C1 1.92 0.076 0.170 0.093 0.220 0.559 1.941


26

Calculated Voltage Drop on Power Lines for Layer 2 & 3

Calculations are made for converter input voltage =10V, analogue c. output =2.5V, digital c. output = 3.0V, efficiency = 80%at the ROC input nominal analogue voltage = 1.6V and nominal digital voltage = 2.2VLuminosity = 2 x 1034

Pos. Converter Net Name

Converter Output Current

Voltage Drop Sector A 8 Layers (70

µm Cu )

Voltage Drop Sector B 2 Layers

(100 µm Cu )

Voltage Drop Sector C

4 Layers (35 µm Cu )

Voltage Drop Sector D AL-Draht Ø

350 µm

Voltage Drop Total in

Sectors A-D

Voltage at the ROC

[A] [V] [V] [V] [V] [V] [V]7 L2C2D7 D1C2 2.244 0.088 0.166 0.095 0.204 0.553 2.447 8 L2C2D8 D2C2 1.496 0.078 0.148 0.077 0.204 0.507 2.493 9 L2C2D9 D3C2 2.244 0.096 0.166 0.095 0.204 0.562 2.438

10 L3C2D10 D4C2 2.575 0.113 0.215 0.118 0.181 0.627 2.373 11 L3C2D11 D5C2 2.575 0.118 0.215 0.118 0.181 0.632 2.368 12 L3C2D12 D6C2 2.575 0.122 0.215 0.118 0.181 0.636 2.364

7 L2C2A7 A1C2 1.44 0.073 0.182 0.090 0.231 0.576 1.924 8 L2C2A8 A2C2 0.96 0.068 0.206 0.073 0.231 0.578 1.922 9 L2C2A9 A3C2 1.44 0.083 0.181 0.090 0.231 0.585 1.915

10 L3C2A10 A4C2 1.92 0.098 0.183 0.087 0.222 0.590 1.910 11 L3C2A11 A5C2 1.92 0.102 0.183 0.087 0.222 0.594 1.906 12 L3C2A12 A6C2 1.92 0.105 0.183 0.087 0.222 0.596 1.904


layout of the power distribution on support tube for phase i 29. 08. 2012 lutz feld, waclaw...

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