TECHNICAL PROGRAM

LATS201819th IEEE Latin-American Test SymposiumSão Paulo, Brazil, 12th - 16th March 2018

WELCOME MESSAGE

The Organizing and Program Committees, the General and Program Chairs warmly welcome all the participants to the 19th IEEE Latin-American Test Symposium (LATS2018). This year the conference is held in São Paulo, Brazil. LATS (previously named Latin-American Test Workshop - LATW) is a recognized forum for test and fault tolerance professionals as well as technologists from all over the world, in particular from Latin America, to present and discuss various aspects of system, board, and component testing as well as fault-tolerance with design, manufacturing and field considerations in mind.

This year LATS offers an excellent Technical Program, which is composed of 13 Regular Paper Sessions, 2 Poster Sessions, 1 Keynote Address, 2 Invited Talks, 1 Embedded Tutorial, 1 Panel, and 1 TTEP Tutorial. The Regular Paper Sessions cover contributions on fault simulation and modeling, automatic test generation, analog mixed signal test, memory testing and fault injection, system-on-chip test, software-based fault tolerance, built-in self-test, issues on EMC, EMI and radiation, design verification and validation, as well as fault tolerant architectures. This edition counts with an up to date Keynote Address entitled “Cognitive Computing: Design, Test and Verification Challenges” given by Kaushik Roy from Purdue University, USA. One interesting TTEP tutorials, ““Power-Aware Testing in the Era of IoT”, given by Patrick Girard from LIRMM, France is offered. Further, two Invited Talks in highly important novel topics are proposed: “Long- Term Electromagnetic Robustness of Integrated Circuits”, given by Sonia Ben Dhia from LAAS-INSA/Toulouse, France and Bernd Deutschmann from Technical University of Graz, Austria, as well as “Are Self-Driving Cars Reliable? Evaluation of Radiation-Induced Errors in GPUs for Automotive Applications”, given by Paolo Rech from UFRGS, Brazil. Finally, one Embedded Tutorial entitled

“Thermal Challenges for Reliable Cyber-Physical Systems” given by Zebo Peng from Linköping University, Sweden is offered.

The realization of LATS2018 could not be possible without the work of very dedicated volunteers. We deeply and sincerely thank the members of the various committees, the authors, the reviewers, the session chairs, the secretariat and the technical support personnel for their valuable contributions. Finally, we would also like to acknowledge the financial co-sponsorship given by CAPES, FAPESP and IEEE Council on Electronic Design Automatic (CEDA). We also thank the technical co-sponsorship of the IEEE, the Test Technology Technical Council and the IEEE Council on Electronic Design Automatic (CEDA).

We do hope that you take profit of the Technical Program, which has been carefully prepared for you. We also hope that you might enjoy São Paulo.

General Chairs:Fabian Vargas PUCRS, BrazilYervant Zorian Synopsys, USA

Program Chairs:Leticia Maria Bolzani Poehls PUCRS, Brazil Fernanda Kastensmidt UFRGS, Brazil

MONDAY, 12th March 2018

Reliability Analysis in SoCs

Session Chair: Matteo Sonza Reorda, Politecnico di Torino – Italy

Reliability Evaluation on Interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC Fabio Benevenuti (UFRGS, Brazil) and Fernanda Kastensmidt (UFRGS, Brazil)

Reliability Analysis on Case-Study Traffic Sign Convolutional Neural Network on APSoCIsrael Lopes (UFRGS, Brazil), Fabio Benevenuti (UFRGS, Brazil), Fernanda Kastensmidt, Altamiro Susin (UFRGS, Brazil) and Paolo Rech (UFRGS, Brazil)

Processor Core Profiling for SEU Effect AnalysisRodrigo Travessini (UFSC, Brazil), Paulo R. C. Villa (UFSC, Brazil), Fabian L. Vargas (PUCRS, Brazil) and Eduardo A. Bezerra (LIRMM Montpellier, France)

10:20 - 11:20 Session 1

08:00 - 09:00 Registration

General Chairs: Fabian Vargas, PUCRS – Brazil; Yervant Zorian, Synopsys – USAProgram Chairs:Letícia Maria Bolzani Poehls, PUCRS – Brazil; Fernanda Kastensmidt, UFRGS – Brazil

09:00 - 09:20 Opening Session

Cognitive Computing: Design, Test, and Verification ChallengesKaushik Roy, Purdue University – USAChair: Fabian Vargas, PUCRS – Brazil

09:20 - 10:00 Keynote Talk

10:00 - 10:20 Coffee Break

12:20 - 14:00 Lunch

Manufacturing Testing and Silicon Validation

Session Chair: Jean-Marc Galliere, LIRMM - France

A flexible stand-alone FPGA-based ATE for ASIC manufacturing testsDionisio Carvalho (USP, Brazil), Bruno Sanches (USP, Brazil), Mauricio de Carvalho (USP, Brazil) and Wilhelmus Van Noije (USP, Brazil)

Post-Silicon Validation based on synthetic test patterns for early detection of timing anomaliesEduardo Garcia-Espinosa (Intel, Mexico), Enrique Gonzalez-Garcia (Intel, Mexico), Omar H. Longoria Gandara (ITESO, Mexico) and Arturo Veloz Guerrero (ITESO, Mexico)

Direct Optimization of a PCI Express Link Equalization in Industrial Post-Silicon ValidationFrancisco Elias Rangel-Patino (ITESO and Intel, Mexico), Jose Ernesto Rayas-Sanchez (ITESO, Mexico), Edgar Andrei Vega-Ochoa (Intel, Mexico) and Nagib Hakim (Intel, USA)

11:20 - 12:20 Session 2

Are Self-Driving Cars Reliable? Evaluation of Radiation-Induced Errors in GPUs for Automotive Applications

Paolo Rech, UFRGS – BrazilChair: Letícia Maria Bolzani Poehls, PUCRS – Brazil

14:00 - 14:40 Invited Talk

Fault Tolerant Architectures

Session Chair: Zebo Peng, Linköping University – Sweden

RTOS for Mixed Criticality applications deployed on NoC-based COTS MPSoC Stefano Esposito (Politecnico di Torini, Italy), Serhiy Avramenko (Politecnico di Torini, Italy) and Massimo Violante (Politecnico di Torini, Italy)

Validation of a Dynamic Checkpoint Mechanism for Apache Hadoop with Failure ScenariosPaulo Vinicius Cardoso (UFSM, Brazil) and Patrícia Pitthan Barcelos (UFSM, Brazil)

A Review of Approximate Computing Techniques towards Fault Mitigation in HW/SW SystemsAlexander Aponte-Moreno (Universidad Nacional de Colombia, Colombia), Alejandro Moncada (Universidad Nacional de Colombia, Colombia), Felipe Restrepo-Calle (Universidad Nacional de Colombia, Colombia) and Cesar Pedraza (Universidad Nacional de Colombia, Colombia)

14:40 - 15:40 Session 3

Fault Injection Strategies

Session Chair: Fernanda Kastensmid, UFRGS – Brazil

On the use of a Failure Emulator Mechanism at Nanosatellite Subsystems Integration Tests Carlos Leandro Gomes Batista (National Institute for Space Researchers, Brazil), Eliane Martins (Campinas University, Brazil) and Maria De Fátima Mattiello-Francisco (National Institute for Space Researchers, Brazil)

16:00 - 16:40 Session 4

15:40 - 16:00 Coffee Break

20:00 - 22:00 Welcome Cocktail

Using FPGA self-produced transients to emulate SETs for SER estimationFábio B. Armelin (INPE and ITA, Brazil), Lírida A. B. Naviner (Telécom ParisTech, France) and Robeto d’Amore (ITA, Brazil)

Exploring Redundancy for Fault Tolerant Systems

Session Chair: Ernesto Sanchez, Politecnico di Torino – Italy

Fault Masking Ratio Analysis of Majority Voters TopologiesIngrid Oliveira (FURG, Brazil), Rafael Schvittz (FURG, Brazil) and Paulo F. Butzen (FURG, Brazil)

Improving Approximate-TMR using Multi-Objective Optimization Genetic Algorithm Iuri Albandes Cunha Gomes (UFRGS, Brazil), Alejandro Serrano-Cases (UFRGS, Brazil), Mayler Martins (UFRGS, Brazil), Antonio Sanchez-Clemente (UFRGS, Brazil), Sergio Cuenca (UFRGS, Brazil) and Fernanda Kastensmidt (UFRGS, Brazil)

16:40 - 17:20 Session 5

TUESDAY, 13th March 2018

Test and Fault Tolerance in Memories

Session Chair: Alberto Bosio, LIRMM University of Montpellier – France

Flexible Architecture of Memory BISTsReinaldo Silveira (NXP, Brazil), Qadeer Qureshi (NXP, Brazil)and Rodrigo Zeli (NXP, Brazil)

A Hardware-Based Approach for SEU Monitoring in SRAMs with Weak Resistive DefectsGeorge Redivo Pinto (PUCRS, Brazil), Guilherme Cardoso Medeiros (PUCRS, Brazil), Fabian Vargas (PUCRS, Brazil) and Leticia Bolzani Poehls (PUCRS, Brazil)

09:40 - 10:20 Session 6

Automated Design Flow for Applying Triple Modular Redundancy (TMR) in Complex Digital Circuits.Luis Alberto Contreras Benites (UFRGS, Brazil) and Fernanda Lima Kastensmidt (UFRGS, Brazil)

10:20 - 11:40 Poster Session

Long-term Electromagnetic Robustness of Integrated CircuitsSonia Ben Dhia, LAAS-INSA/Toulouse – FranceBernd Deutschmann, Graz University of Technology –AustriaChair: Fabian Vargas, PUCRS – Brazil

09:00 - 09:40 Invited Talk 2

10:20 - 10:40 Coffee Break

Towards Evolvable Hardware and Genetic Algorithm Operators to Fail Safe Systems Achievement.Gabriel Natan Silva (UFMG, Brazil) and Ricardo Duarte (UFMG, Brazil)

Fault-Tolerant architecture with full recovery under presence of SEU Augusto Einsfeldt (FEI, Brazil) and Renato Giacomini (FEI, Brazil)

A Novel Method of Impact and Failure Mechanism Analysis of RF-Based Fault Injection: a Frequency Response AnalyzerRicardo Maltione (University of Campinas, Brazil), Marcelo Vilalva (University of Campinas, Brazil) and Luiz Kretly (University of Campinas, Brazil) Alternative Functional Verification Methodology for Low and Medium Level Designs (Applied to an AES Encryption Module)Frank Plasencia Balabarca (PUC del Peru, Peru), Edward Mitacc Meza (PUC del Peru, Peru), Mario Raffo Jara (PUC del Peru, Peru) and Carlos Silva Cárdenas (PUC del Peru, Peru)

Architecture of an industrial analog input designed to meet safety requirements João Ricardo Wagner de Moraes (UFRGS, Brazil), Taisy Weber (UFRGS, Brazil), Guilherme Müller (UFRGS, Brazil), Tiago Dall’Agnol (UFRGS, Brazil), Rafael Broch Macedo (UFRGS, Brazil), Elaine Pereira Lima Scartezzini (UFRGS, Brazil), Roque Eduardo Dapper (UFRGS, Brazil), Sérgio Luis Cechin (UFRGS, Brazil) and João Cesar Netto (UFRGS, Brazil)

Fault Tolerance Techniques

Session Chair: Maksim Jenihinn, Tallinn University of Technology – Estonia

Processor Checkpoint Recovery for Transient Faults in Critical ApplicationsPaulo R. C. Villa (UFSC, Brazil), Rodrigo Travessini (UFSC, Brazil), Fabian Vargas (PUCRS, Brazil) and Eduardo Bezerra (LIRMM Montpellier, France)

Exploring the Inherent Fault Tolerance of Successive Approximation Algorithms under Laser Fault InjectionGennaro Rodrigues (UFRGS, Brazil), Fernanda Kastensmidt (UFRGS, Brazil), Vincent Pouget (IES University of Montpellier, France) and Alberto Bosio (LIRMM University of Montpellier, France)

Fault Tolerant Dynamically Scheduled Processor with Partial Permanent Fault HandlingFelix Mühlbauer (University of Potsdam, Germany), Lukas Schröder (University of Potsdam, Germany) and Mario Schölzel (University of Potsdam, Germany)

10:40 - 11:40 Session 7

Thermal Challenges for Reliable Cyber-Physical Systems

Zebo Peng, Linköping University – Sweden Chair: Yervant Zorian, Synopsys – USA

13:00 - 14:00 Embedded Tutorial

11:40 - 13:00 Lunch

15:00 - 19:00 Social Event

20:30 - 22:30 Gala Dinner

Aging Modeling and Mitigation

Session Chair: Bernd Deutschmann, Technical University of Graz – Austria

FA Metric-Guided Gate-Sizing Methodology for Aging Guardband ReductionAndrés Felipe Gómez (INAOE, Mexico), Roberto Gomez (University of Sonora, Mexico), Victor Champac (INAOE, Mexico) Ionizing Radiation Modeling in DRAM Moritz Fieback (Delft University of Technology, The Netherlands), Mottaqiallah Taouil (Delft University of Technology, The Netherlands), Said Hamdioui (Delft University of Technology, The Netherlands) and Marco Rovatti (European Space Agency, The Netherlands)

09:00 - 09:40 Session 8

Testing and Security of Microprocessor CoresSession Chair: Mario Schoelzel, University of Potsdam – Germany

About Functionally Untestable Fault Identification in Microprocessor Cores for Safety-Critical ApplicationsRiccardo Cantoro (Politecnico di Torino, Italy), Andrea Firrincieli (Politecnico di Torino, Italy), Davide Piumatti (Politecnico di Torino, Italy), Marco Restifo (Politecnico di Torino, Italy), Ernesto Sanchez (Politecnico di Torino, Italy) and Matteo Sonza Reorda (Politecnico di Torino, Italy)

Defeating Hardware Trojan in Microprocessor Cores through Software ObfuscationAndrea Marcelli, Ernesto Sanchez, Giovanni Squillero, Afnan Imtiaz, Paolo Monti, Muhammad Usman Jamal, Davide Pola, Alessandro Salvato, Michele Simili, Simone Machetti and Filippo Mangani (Politecnico di Torino, Italy)

09:40 - 10:20 Session 9

WEDNESDAY, 14th March 2018

Fault Tolerance Techniques

Session Chair: Said Hamdioui, Delft University of Technology – The Netherlands

Testing Approximate Digital Circuits: Challenges and OpportunitiesMarcello Traiola (LIRMM University of Montpellier, France), Arnaud Virazel (LIRMM University of Montpellier, France), Patrick Girard (LIRMM University of Montpellier, France), Mario Barbareschi (DIETI University of Naples Federico II, Italy) and Alberto Bosio (LIRMM University of Montpellier, France)

Design and Test of the RT-NKE Task Scheduling Algorithm for Multicore Architectures Renato Severo (State University of Rio Grande do Sul, Brazil), Celso Costa (State University of Rio Grande do Sul, Brazil), Adriane Parraga (State University of Rio Grande do Sul, Brazil), Debora Motta (State University of Rio Grande do Sul, Brazil), Ivan Muller (UFRGS, Brazil) and Fabian Vargas (PUCRS, Brazil)

Real-Time Validation of Mixed-Criticality Applications Stefano Esposito (Politecnico di Torino, Italy), Jacopo Sini (Politecnico di Torino, Italy) and Massimo Violante (Politecnico di Torino, Italy)

10:40 - 11:40 Session 10

10:20 - 10:40 Coffee Break

11:40 - 13:30 Lunch

Testing of Analog Systems

Session Chair: Fabian Vargas, PUCRS – Brazil

Using Short-Term Fourier Transform for Particle Detection and Recognition in a CMOS Oscillator-based ChainHassen Aziza, Karine Coulié, Wenceslas Rahajandraibe and Remy Vauche (Aix Marseille University, University Toulon, CNRS, IM2NP, France)

Exploiting Power Supply Ramp Rate for Calibrating Cell Strength in SRAM PUFs Wendong Wang (Auburn University, USA), Adit Singh(Auburn University, USA), Ujjwal Guin (Auburn Unviersity, USA) and Abhijit Chatterjee (Georgia Institute of Technolgy, USA)

13:30 - 14:10 Session 11

Dependable Embedded Systems

Session Chair: Leticia Maria Bolzani Poehls, PUCRS - Brazil

TDevCGen: A Synthesis Toolset of HW/SW Communication Protocol Monitors from high-level SpecificationsRafael Melo Macieira (UFP, SENAI Innovation Institute, Brazil) and Edna Barros (UFP, Brazil) Error Detection Methods for The ARINC429 CommunicationMarcos Silveira Santos (ITA, Brazil) and Roberto d’Amore (ITA, Brazil)

Superimposed In-Circuit Debugging for Self-Healing FPGA OverlaysAlexandra Kourfali (Ghent University, Belgium) and Dirk Stroobandt (Ghent University, Belgium)

14:10 - 15:10 Session 12

Influence of Passive Oscillator Component Variation on OBT Sensitivity in OTAs Pablo Petrashin (Universidad Catolica de Cordoba, Argentina), Tinus Stander (University of Pretoria, South Africa), Fortunato Dualibe (Université de Mons, Belgium), Luis Toledo (Universidad Catolica de Cordoba, Argentina), Walter Lancioni (Universidad Catolica de Cordoba, Argentina) and Carlos Vazquez (Universidad Catolica de Cordoba, Argentina)

Challenges and Emerging Solutions in Testing HBM IO & Systems Salem Abdennadher, Michael Altmann and Bin Xue (Intel Corporation, USA)

IJTAG Compatible Analogue Embedded Instruments for MPSoC Life-time Prediction Jerrin Pathrose (University of Twente, The Netherlands), Ghazanfar Ali (University of Twente, The Netherlands) and Hans Kerkhoff (University of Twente, The Netherlands)

Weibull Cumulative Distribution Function (CDF) Analysis with Life Expectancy Endurance Test Result of Power Window Switch Dave Lim and Miky Lee (LS Automotive, Korea)

Probability Aware Fault-Injection Approach for SER Estimation Fábio B. Armelin (INPE and ITA, Brazil), Lírida A. B. Naviner (Telécom ParisTech, France) and Robeto d’Amore (Telécom ParisTech, France)

15:10 - 16:10 Poster Session 2

15:10 - 15:30 Coffee Break

Single Event Effect: simulations and analysis on 3N163 PMOS transistor.Juliano Alves de Oliveira (FEI, Brazil), Renato Camargo Giacomini (FEI, Brazil), Marco Antônio Assis de Mello (FEI, Brazil) and Marcilei Guazzelli (FEI, Brazil)

Analysis of LEON3 systems integration for a Network-on-Chip Lucas Pereira (University of Vale do Itajai, Brazil), Douglas Melo (UFSC, Brazil), Cesar Zeferino (University of Vale do Itajai, Brazil) and Eduardo Bezerra (LIRMM Montpellier, France)

An Efficient EDAC Approach for Handling Multiple Bit Upsets in Memory Array Roger Goerl (PUCRS, Brazil), Paulo R. C. Villa (UFSC, Brazil), Leticia Bolzani Poehls (PUCRS, Brazil), Eduardo Bezerra (LIRMM Montpellier, France) and Fabian Vargas (PUCRS, Brazil)

Electrical Characterization and PV Analysis

Session Chair: Victor Champac, INOAE - Mexico

Time Domain Electrical Characterization in Zinc Oxide Nanoparticle Thin-Film Transistors Thales E. Becker (UFRGS, Brazil), Fábio F. Vidor (UFRGS, Brazil), Gilson I. Wirth (UFRGS, Brazil), Thorsten Meyers (University of Paderborn, Germany) , Julia Reker (University of Paderborn, Germany) and Ulrich Hilleringmann (University of Paderborn, Germany)

16:30 - 17:10 Session 13

15:30 - 16:30 PhD and Master Contests

Impact of Process Variations on the Detectability of Resistive Short Defects: Comparative Analysis between 28nm Bulk and FDSOI Technologies Amit Karel (LIRMM, CNRS/University of Montpellier, France), Florence Azais (LIRMM, CNRS/University of Montpellier, France), Mariane Comte (LIRMM, CNRS/University of Montpellier, France), Jean-Marc Galliere (LIRMM, CNRS/University of Montpellier, France)and Michel Renovell (LIRMM, CNRS/University of Montpellier, France)

Influence of Temperature on Dynamic Fault Behavior Due to Resistive Defects in FinFET-Based SRAMsG. Medeiros (PUCRS, Brazil), T. Copetti (UFGS, Brazil), E. Brum (PUCRS, Brazil), L. Bolzani Poehls (PUCRS, Brazil) and T. Balen (UFGS, Brazil)

Award Ceremony for the PhD and Master ThesisAward Ceremony for LATS2018 Best Paper

17:10 - 18:00 Closing Session