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TRANSCRIPT
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EE141
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EE141 EECS141 1 Lecture #4
EE141 EECS141 2 Lecture #4
New discussion session Fr 1-2pm
Homework #1 extension until Monday 5pm
Homework #2 to be posted later today
Labs start next week (Monday)
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EE141
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EE141 EECS141 3 Lecture #4
Last lecture
Basic metrics for IC design
Manufacturing
Today’s lecture
Design Rules
Introduction to switch logic
Reading (2.3, 3.3.1-3.3.2)
EE141 EECS141 4 Lecture #4
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EE141 EECS141 5 Lecture #4
EE141 EECS141 6 Lecture #4
(well contacts)
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EE141 EECS141 7 Lecture #4
Interface between designer and process
engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)
EE141 EECS141 8 Lecture #4
Intra-layer
Widths, spacing, area
Inter-layer
Enclosures, distances, extensions,
overlaps
Special rules (sub-0.25 m)
Antenna rules, density rules, (area)
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EE141 EECS141 9 Lecture #4
EE141 EECS141 10 Lecture #4
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EE141 EECS141 11 Lecture #4
EE141 EECS141 12 Lecture #4
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EE141 EECS141 13 Lecture #4
EE141 EECS141 14 Lecture #4
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EE141 EECS141 15 Lecture #4
EE141 EECS141 16 Lecture #4
• Dimensionless layout entities
• Only topology is important
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EE141 EECS141 17 Lecture #4
EE141 EECS141 18 Lecture #4
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Polysilicon
In Out
V DD
GND
PMOS 2
Metal 1
NMOS
Contacts
N Well
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EE141 EECS141 19 Lecture #4
Connect in Metal
Share power and ground
Abut cells
EE141 EECS141 20 Lecture #4
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EE141 EECS141 21 Lecture #4
|VGS|
An MOS Transistor
|VGS| |VT|
S D
Ron
A Switch!
S D
G
EE141 EECS141 22 Lecture #4
|VGS|
S D
G
|VGS| < |VT| |VGS| > |VT|
Ron
S D S D
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EE141 EECS141 23 Lecture #4
|VGS|
S D
G
|VGS| < |VT| |VGS| > |VT|
Ron
S D
Roff
S D
EE141 EECS141 24 Lecture #4
VGS > 0
S D
G
VGS < 0
S D
G
NMOS Transistor PMOS Transistor
Y=Z IF X=1 Y=Z IF X=0
Y Z
Ron X
Y Z
Ron X
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EE141 EECS141 25 Lecture #4
EE141 EECS141 26 Lecture #4
V in V out
C L
V DD
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EE141 EECS141 27 Lecture #4
VOL = 0
VOH = VDD VM = f(Rn, Rp)
V DD V DD
V in = V DD V in = 0
V out V out
R n
R p
EE141 EECS141 28 Lecture #4
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EE141 EECS141 29 Lecture #4
VOH =
VOL =
VIL =
VIH =
NMH =
NML =
VM =
EE141 EECS141 30 Lecture #4
VOH = VDD = 2.5V
VOL = 0V
VM = 1.2V
VIL = 1.05V
VIH = 1.45V
NMH =1.05V
NML = 1.05V
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EE141 EECS141 31 Lecture #4
t pHL = f(RonCL)
= 0.69 R n C L
(a) Low-to-high (b) High-to-low
EE141 EECS141 32 Lecture #4
Full rail-to-rail swing
Symmetrical VTC
Propagation delay function of load
capacitance and resistance of transistors
No static power dissipation
Direct path current during switching
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EE141 EECS141 33 Lecture #4
EE141 EECS141 34 Lecture #4
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EE141 EECS141 35 Lecture #4
EE141 EECS141 36 Lecture #4
CL
In Out
For some given CL:
How many stages are needed to minimize delay?
How to size the inverters?
Anyone want to guess the solution?
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EE141 EECS141 37 Lecture #4
Get fastest delay if build one very big
inverter
So big that delay is set only by self-loading
Likely not the problem you’re interested in
Someone has to drive this inverter…
EE141 EECS141 38 Lecture #4
Need to have a set of constraints
Constraints key to: Making the result useful
Making the problem have a ‘clean’ solution
For sizing problem: Need to constrain size of first inverter
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EE141 EECS141 39 Lecture #4
You are given:
A fixed number of inverters
The size of the first inverter
The size of the load that needs to be driven
Your goal:
Minimize the delay of the inverter chain
Need model for inverter delay vs. size
EE141 EECS141 40 Lecture #4
tpHL = (ln 2) RNCL tpLH = (ln 2) RpCL Delay:
2W
W
Assume we want equal rise/fall delays
tpHL = tpLH
Need approximately equal resistances, RN = RP PMOS approximately 2 times larger resistance
for same size;
Must make PMOS 2 times wider, WP = 2WN = 2W
tp = (ln 2) (Rmin/W) CL with Rmin resistance of
minimum size NMOS
Loading on the previous stage: Cin = WCgmin = W(3CG)
CP = 2WCg
CN = WCg
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EE141 EECS141 41 Lecture #4
Cint CL
Replace ln(2) with k (a constant):
Delay = kR(Cint + CL)
Delay = k(Rmin/W)(WCdmin + CL)
2W
W
R = Rmin/W
Cint = (3W)Cd = WCdmin
EE141 EECS141 42 Lecture #4
Load
Delay
Delay = kR Cin(Cint/Cin+ CL /Cin)
= kRminCgmin[Cdmin/Cgmin + CL/(WCgmin)]
= Delay (Internal) + Delay (Load)
Cdmin/Cgmin = = Constant independent of size
Cint CL
Cin 2W
W
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EE141 EECS141 43 Lecture #4
Cint = Cin ( 1 for CMOS inverter)
f = CL/Cin – electrical fanout
tinv = kRminCgmin
tinv is independent of sizing of the gate!!!
EE141 EECS141 44 Lecture #4
CL
In Out
1 2 N
tp = tp1 + tp2 + …+ tpN
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EE141 EECS141 45 Lecture #4
Delay equation has N-1 unknowns, Cin,2 … Cin,N
To minimize the delay, find N-1 partial derivatives:
EE141 EECS141 46 Lecture #4
Result: every stage has equal fanout:
In other words, size of each stage is geometric
mean of two neighbors:
Equal fanout every stage will have same delay
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EE141 EECS141 47 Lecture #4
When each stage has same fanout f :
Effective fanout of each stage:
Minimum path delay:
EE141 EECS141 48 Lecture #4
CL= 8 C1
In Out
C1 1 f f 2
CL/C1 has to be evenly distributed across N = 3 stages:
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EE141 EECS141 49 Lecture #4
You are given: The size of the first inverter
The size of the load that needs to be driven
Your goal: Minimize delay by finding optimal number and sizes of gates
So, need to find N that minimizes:
EE141 EECS141 50 Lecture #4
For = 0, f = e, N = ln (CL/Cin)
Rewrite N in terms of fanout/stage f:
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EE141 EECS141 51 Lecture #4
Optimum f for given process defined by
0 0.5 1 1.5 2 2.5 3 2.5
3
3.5
4
4.5
5
f opt
fopt = 3.6
for = 1
e
EE141 EECS141 52 Lecture #4
Curves very flat for f > 2
Simplest/most common choice: f = 4
[Hodges, p.281]
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EE141 EECS141 53 Lecture #4
Textbook: page 210
( = 1)
EE141 EECS141 54 Lecture #4
1
1
1
1
8
64
64
64
64
4
2.8 8
16
22.6
N f tp
1 64 65
2 8 18
3 4 15
4 2.8 15.3
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EE141 EECS141 55 Lecture #4
Ignoring diffusion capacitance:
Ctot = Cin + f Cin + … + fN Cin
= Cin (1 + f + … + fN)
= Cin + Cin fN + Cin f (1 + f + … +
fN-2) Overhead !!! f(fN-1-1) / (f-1)
Example ( =0): CL = 20pF; Ci = 50fF N = 6
Fixed: 20pF
Overhead: 11.66pF !!!
EE141 EECS141 56 Lecture #4
Example: CL = 20pF; Cin = 50fF