Large Scale Integrated Large Scale Integrated CircuitsCircuits

22

A Little HistoryA Little History

In 1942, in the University of In 1942, in the University of Pennsylvania's Moore School of Pennsylvania's Moore School of Engineering, John Mauchly and J Engineering, John Mauchly and J Presper Eckert built a machine to Presper Eckert built a machine to compute artillery firing tables for the compute artillery firing tables for the Amercian government. Amercian government.

33

A Little HistoryA Little History

This device weighing 30 tons and containing This device weighing 30 tons and containing 100,000 electronic components, including 100,000 electronic components, including 17,000 vacuum tubes, was called the 17,000 vacuum tubes, was called the Electronic Numerical Integrator and Computer Electronic Numerical Integrator and Computer (ENIAC). (ENIAC).

This machine was 80 feet long and 18 feet This machine was 80 feet long and 18 feet high and utilized the decimal numbering high and utilized the decimal numbering system. Mauchly and Eckert also claimed that system. Mauchly and Eckert also claimed that ENIAC was the first general-purpose electronic ENIAC was the first general-purpose electronic digital computer, but in 1973 this matter was digital computer, but in 1973 this matter was settled by a US court, which declared that the settled by a US court, which declared that the Atanasoff-Berry computer was entitled to that Atanasoff-Berry computer was entitled to that honor. honor.

44

A Little HistoryA Little History

Improvements continued until 1959, when Improvements continued until 1959, when both Jack Kilby, at Texas Insturments, and both Jack Kilby, at Texas Insturments, and Robert Noyce, at Fairchild Semiconductor, Robert Noyce, at Fairchild Semiconductor, discovered that resistors, capacitors and discovered that resistors, capacitors and transistors could be made from a transistors could be made from a semiconductor material and that vast semiconductor material and that vast numbers of transistors could be etched numbers of transistors could be etched onto a single silicon chip. onto a single silicon chip.

Thus, the age of integrated circuits had Thus, the age of integrated circuits had arrived, and from this point forward, arrived, and from this point forward, computers continuously decreased in size computers continuously decreased in size and increased in power and performance. and increased in power and performance.

55

Microchips, Miniaturization, &MobilityMicrochips, Miniaturization, &MobilityFrom Vacuum Tubes to Transistors to From Vacuum Tubes to Transistors to

MicrochipsMicrochips

Transistor - a Transistor - a tiny electrically tiny electrically operated switch, operated switch, or gate, that can or gate, that can alternate alternate between “on” between “on” and “off” many and “off” many millions of times millions of times per secondper second 1940s vacuum tube

towering over 1950s transistor

66

TransistorsTransistors

Replaced vacuum tubesReplaced vacuum tubes SmallerSmaller CheaperCheaper Less heat dissipationLess heat dissipation Solid State deviceSolid State device Made from Silicon (Sand)Made from Silicon (Sand) Invented 1947 at Bell LabsInvented 1947 at Bell Labs

77

Transistor Based ComputersTransistor Based Computers

Second generation machinesSecond generation machines NCR & RCA produced small transistor NCR & RCA produced small transistor

machinesmachines IBM 7000IBM 7000 DEC - 1957DEC - 1957

Produced PDP-1Produced PDP-1

88

MicroelectronicsMicroelectronics

Literally - “small electronics”Literally - “small electronics” A computer is made up of gates, A computer is made up of gates,

memory cells and interconnectionsmemory cells and interconnections These can be manufactured on a These can be manufactured on a

semiconductorsemiconductor e.g. silicon wafere.g. silicon wafer

99

Generations of ComputerGenerations of Computer Vacuum tube - 1946-1957Vacuum tube - 1946-1957 Transistor - 1958-1964Transistor - 1958-1964 Small scale integration - 1965Small scale integration - 1965

Up to 100 devices on a chipUp to 100 devices on a chip Medium scale integration - to 1971Medium scale integration - to 1971

100-3,000 devices on a chip100-3,000 devices on a chip Large scale integration - 1971-1977Large scale integration - 1971-1977

3,000 - 100,000 devices on a chip3,000 - 100,000 devices on a chip Very large scale integration - 1978 to dateVery large scale integration - 1978 to date

100,000 - 100,000,000 devices on a chip100,000 - 100,000,000 devices on a chip Ultra large scale integrationUltra large scale integration

Over 100,000,000 devices on a chipOver 100,000,000 devices on a chip

MemoryMemory

1111

Dr. Jay W. Forrester Dr. Jay W. Forrester  1946-19511946-1951

Dr. Forrester was director of MIT's Digital Dr. Forrester was director of MIT's Digital Computer Laboratory and was responsible Computer Laboratory and was responsible for for the design and construction of Whirlwind Ithe design and construction of Whirlwind I, the first large scale, high-speed digital , the first large scale, high-speed digital computer to go into complete operation. computer to go into complete operation. While working on computer technology, While working on computer technology, Dr. Forrester invented random-access, coinciDr. Forrester invented random-access, coincident-current magnetic storagedent-current magnetic storage, which was for many years the standard  , which was for many years the standard  memory device for digital computers.         memory device for digital computers.         This invention , which is called This invention , which is called magnetic core memorymagnetic core memory, involved the , involved the phenomenon that when current flows phenomenon that when current flows through a core, the core becomes through a core, the core becomes magnetized even the current is removed. magnetized even the current is removed. The introduction of this kind of memory The introduction of this kind of memory makes computers smaller in size, faster to makes computers smaller in size, faster to access data, and more powerful. It also was access data, and more powerful. It also was what today's memory technology was based what today's memory technology was based on. on.

1212

RAMRAM

In 1970, the newly formed In 1970, the newly formed IntelIntel company company publicly released the 1103, the first publicly released the 1103, the first DRAM (Dynamic Random Access DRAM (Dynamic Random Access Memory) chip (1K bit PMOS dynamic Memory) chip (1K bit PMOS dynamic RAM ICs), and by 1972 it was the best RAM ICs), and by 1972 it was the best selling semiconductor memory chip in selling semiconductor memory chip in the world, defeating magnetic the world, defeating magnetic core type memorycore type memory.  The first .  The first commercially available computer using commercially available computer using the 1103 was the HP 9800 series. the 1103 was the HP 9800 series.

1313

RAMRAM

Dr. Robert H. Dr. Robert H. DennardDennard, a Fellow at the IBM Thomas , a Fellow at the IBM Thomas J. Watson Research Center created the one-J. Watson Research Center created the one-transistor DRAM in 1966. Dennard and his team transistor DRAM in 1966. Dennard and his team were working on early field-effect transistors and were working on early field-effect transistors and integrated circuits, and his attention to memory integrated circuits, and his attention to memory chips came from seeing another team's research chips came from seeing another team's research with thin-flim magnetic memory. Dennard claims with thin-flim magnetic memory. Dennard claims he went home and within a few hours had gotten he went home and within a few hours had gotten the basic ideas for the creation of DRAM. He the basic ideas for the creation of DRAM. He worked on his ideas for a simpler memory cell that worked on his ideas for a simpler memory cell that used only a single transistor and a small capacitor. used only a single transistor and a small capacitor. IBM and Dennard were granted a patent for DRAM IBM and Dennard were granted a patent for DRAM in 1968. in 1968.

1414

RAMRAM

RAM stands for random access memory, memory RAM stands for random access memory, memory that can be accessed or written to randomly -- any that can be accessed or written to randomly -- any byte or piece of memory can be used without byte or piece of memory can be used without accessing the other bytes or pieces of memory. accessing the other bytes or pieces of memory. There were two basic types of RAM, dynamic RAM There were two basic types of RAM, dynamic RAM (DRAM) and static RAM (SRAM). DRAM needs to be (DRAM) and static RAM (SRAM). DRAM needs to be refreshed thousands of times per second. SRAM refreshed thousands of times per second. SRAM does not need to be refreshed, which makes it does not need to be refreshed, which makes it faster. Both types of RAM are volatile -- they lose faster. Both types of RAM are volatile -- they lose their contents when the power is turned off. In their contents when the power is turned off. In 1970, Fairchild Corporation invented the first 256-k 1970, Fairchild Corporation invented the first 256-k SRAM chip. Recently, several new types of RAM SRAM chip. Recently, several new types of RAM chips have been designed. chips have been designed.

1515

RAM BasicsRAM Basics

Similar to a microprocessor, a memory chip is an Similar to a microprocessor, a memory chip is an integrated circuit (IC) made of millions of transistors integrated circuit (IC) made of millions of transistors and capacitors. In the most common form of computer and capacitors. In the most common form of computer memory, dynamic random access memory (DRAM), a memory, dynamic random access memory (DRAM), a transistor and a capacitor are paired to create a transistor and a capacitor are paired to create a memory cell, which represents a single bit of data. memory cell, which represents a single bit of data.

The capacitor holds the bit of information -- a 0 or a 1 The capacitor holds the bit of information -- a 0 or a 1 (see How Bits and Bytes Work for information on bits). (see How Bits and Bytes Work for information on bits). The transistor acts as a switch that lets the control The transistor acts as a switch that lets the control circuitry on the memory chip read the capacitor or circuitry on the memory chip read the capacitor or

change its state.change its state.

1616

RAM Basics Con’tRAM Basics Con’t

A capacitor is like a small bucket that is able to store A capacitor is like a small bucket that is able to store electrons. To store a 1 in the memory cell, the bucket is electrons. To store a 1 in the memory cell, the bucket is filled with electrons. To store a 0, it is emptied. The filled with electrons. To store a 0, it is emptied. The problem with the capacitor's bucket is that it has a leak. problem with the capacitor's bucket is that it has a leak. In a matter of a few milliseconds a full bucket becomes In a matter of a few milliseconds a full bucket becomes empty.empty.

Therefore, for dynamic memory to work, either the CPU or Therefore, for dynamic memory to work, either the CPU or the memory controller has to come along and recharge the memory controller has to come along and recharge all of the capacitors holding a 1 before they discharge. To all of the capacitors holding a 1 before they discharge. To do this, the memory controller reads the memory and do this, the memory controller reads the memory and then writes it right back. This refresh operation happens then writes it right back. This refresh operation happens automatically thousands of times per second. automatically thousands of times per second.

1717

RAM Memory CellRAM Memory Cell

1818

Memory ModulesMemory Modules

Memory chips in desktop computers originally Memory chips in desktop computers originally used a pin configuration called dual inline used a pin configuration called dual inline package (DIP). This pin configuration could be package (DIP). This pin configuration could be soldered into holes on the computer's soldered into holes on the computer's motherboard or plugged into a socket that was motherboard or plugged into a socket that was soldered on the motherboard. This method soldered on the motherboard. This method worked fine when computers typically operated worked fine when computers typically operated on a couple of megabytes or less of RAM, but as on a couple of megabytes or less of RAM, but as the need for memory grew, the number of chips the need for memory grew, the number of chips needing space on the motherboard increased. needing space on the motherboard increased.

1919

Memory Modules Con’tMemory Modules Con’t

The solution was to place the memory chips, The solution was to place the memory chips, along with all of the support components, on a along with all of the support components, on a separate printed circuit board (PCB) that could separate printed circuit board (PCB) that could then be plugged into a special connector then be plugged into a special connector (memory bank) on the motherboard. (memory bank) on the motherboard.

2020

RAM ExamplesRAM Examples

Moore’s LawMoore’s Law

2222

Moore’s LawMoore’s Law Gordon Moore made his famous observation in Gordon Moore made his famous observation in

1965, just four years after the first planar 1965, just four years after the first planar integrated circuit was discovered. The press called integrated circuit was discovered. The press called it "Moore's Law" and the name has stuck. In his it "Moore's Law" and the name has stuck. In his original paperoriginal paper, Moore observed an exponential , Moore observed an exponential growth in the number of transistors per integrated growth in the number of transistors per integrated circuit and predicted that this trend would circuit and predicted that this trend would continue. Through Intel's relentless technology continue. Through Intel's relentless technology advances, Moore's Law, the doubling of transistors advances, Moore's Law, the doubling of transistors every couple of years, has been maintained, and every couple of years, has been maintained, and still holds true today. Intel expects that it will still holds true today. Intel expects that it will continue at least through the end of this decade. continue at least through the end of this decade.

2323

Moore’s LawMoore’s Law

Increased density of components on chipIncreased density of components on chip Gordon Moore - cofounder of IntelGordon Moore - cofounder of Intel Number of transistors on a chip will double every Number of transistors on a chip will double every

yearyear Since 1970’s development has slowed a littleSince 1970’s development has slowed a little

Number of transistors doubles every 18 monthsNumber of transistors doubles every 18 months Cost of a chip has remained almost unchangedCost of a chip has remained almost unchanged Higher packing density means shorter electrical Higher packing density means shorter electrical

paths, giving higher performancepaths, giving higher performance Smaller size gives increased flexibilitySmaller size gives increased flexibility Reduced power and cooling requirementsReduced power and cooling requirements Fewer interconnections increases reliabilityFewer interconnections increases reliability

2424

Moore’s LawMoore’s Law

2525

Moore’s LawMoore’s Law

Chip FabricationChip Fabrication

2727

Steps in Manufacture of a Steps in Manufacture of a MicrochipMicrochip

1 Make large Make large drawing. Reduce drawing. Reduce drawing drawing hundreds of hundreds of times to times to microscopic size.microscopic size.

2 Duplicate Duplicate reduced photo reduced photo many times on many times on sheet.sheet.

2828

Steps in Manufacture of a Steps in Manufacture of a MicrochipMicrochip

3 Print sheet of Print sheet of multiple copies multiple copies on a wafer made on a wafer made of silicon, a of silicon, a semiconductor.semiconductor.

4 Print layer after Print layer after layer above and layer above and below original below original silicon surface.silicon surface.

2929

Steps in Manufacture of a Steps in Manufacture of a MicrochipMicrochip

5 Cut wafer Cut wafer into chips.into chips.

6 Mount chip Mount chip in frame in frame with with connective connective pins pins extruding.extruding.

3030

Miniaturization Miracles: Miniaturization Miracles: Microchips, Microprocessors, & Microchips, Microprocessors, &

MicromachinesMicromachines Types of microchips:Types of microchips: MemoryMemory LogicLogic CommunicationsCommunications GraphicsGraphics MathMath MicroprocessorMicroprocessor MicrocontrollerMicrocontroller

3131

Overview of Wafer Overview of Wafer FabricationFabrication

3232

Overview of Wafer Overview of Wafer FabricationFabrication Four stages of Semiconductor Four stages of Semiconductor

ManufacturingManufacturing material prepmaterial prep crystal growth and wafer prepcrystal growth and wafer prep wafer fabricationwafer fabrication packagingpackaging

Wafer FabricationWafer Fabrication the series of processes used to create the the series of processes used to create the

semiconductor devices in/on the surface of the semiconductor devices in/on the surface of the waferwafer

3333

Wafer TerminologyWafer Terminology Chip, die, microcircuit, die,barChip, die, microcircuit, die,bar

the identical circuits covering the waferthe identical circuits covering the wafer Scribe lines, saw lines, streets, avenuesScribe lines, saw lines, streets, avenues

small areas between the chips used to small areas between the chips used to separate themseparate them

Engineering die, test dieEngineering die, test die special devices or circuits containing special special devices or circuits containing special

chemicals to be tested during processingchemicals to be tested during processing Edge dieEdge die

partial die patterns that will not functionpartial die patterns that will not function

3434

Wafer Terminology (cont.)Wafer Terminology (cont.)

Wafer crystal planeWafer crystal plane the crystal structure toward which the the crystal structure toward which the

chip edges are orientedchip edges are oriented Wafer FlatsWafer Flats

the flatted edge which indicates the the flatted edge which indicates the crystal structure and material typecrystal structure and material type

3535

Basic Wafer Fab OperationsBasic Wafer Fab Operations

LayeringLayering PatterningPatterning Doping Doping Heat TreatmentsHeat Treatments

3636

LayeringLayering Adding thin layers to the wafer surfaceAdding thin layers to the wafer surface

either insulators, conductors or either insulators, conductors or semiconductorssemiconductors

deposited by two major techniques - growing deposited by two major techniques - growing or depositionor deposition

Oxidation - growing a silicon dioxide layer Oxidation - growing a silicon dioxide layer on the wafer surfaceon the wafer surface

Deposition - common techniques are CVD Deposition - common techniques are CVD (chemical vapor deposition) Evaporation (chemical vapor deposition) Evaporation and Sputtering.and Sputtering.

3737

PatterningPatterning Series of steps resulting in removal of certain Series of steps resulting in removal of certain

portions of the added surface layersportions of the added surface layers After removal a After removal a patternpattern of the layerof the layer is left on the is left on the

wafer surface.wafer surface. Material removed may be in the form of a whole Material removed may be in the form of a whole

or just an island of material.or just an island of material. Patterning process known by names Litho, Patterning process known by names Litho,

Masking, Photolithography, Photomasking, Masking, Photolithography, Photomasking, MicrolithographyMicrolithography

Patterning is the most critical basic operation.Patterning is the most critical basic operation.

3838

Patterning (cont)Patterning (cont) Goal is to:Goal is to:

create circuit parts in the exact dimensions create circuit parts in the exact dimensions (feature size) required by the circuit design(feature size) required by the circuit design

locate them in their precise location on the locate them in their precise location on the wafer surface.wafer surface.

Errors in process or placement can change Errors in process or placement can change the electrical functions of the device.the electrical functions of the device.

Contamination can introduce serious Contamination can introduce serious defects that result in loss of good die.defects that result in loss of good die.

3939

DopingDoping Places specific amounts of dopant in the wafer Places specific amounts of dopant in the wafer

surface through openings in the surface layer.surface through openings in the surface layer. Two techniques used are Ion Implantation and Two techniques used are Ion Implantation and

Thermal Diffusion.Thermal Diffusion. Thermal diffusion - chemical process that takes Thermal diffusion - chemical process that takes

place when wafer is heated to about 1000° C and place when wafer is heated to about 1000° C and exposed to vapors of the proper dopant.exposed to vapors of the proper dopant.

Ion Implantation - physical process in which Ion Implantation - physical process in which dopant atoms are ionized, accelerated to high dopant atoms are ionized, accelerated to high speed and “shot” into the wafer surfacespeed and “shot” into the wafer surface

4040

Doping (cont)Doping (cont)

Purpose:Purpose: create either N type or P type pockets in create either N type or P type pockets in

the wafer surfacethe wafer surface these pockets form the PN junctions these pockets form the PN junctions

required for operation of the transistors, required for operation of the transistors, capacitors, diodes and resistors in the capacitors, diodes and resistors in the circuitcircuit

4141

Heat TreatmentHeat Treatment Heat treatment to achieve specific results.Heat treatment to achieve specific results. Annealing - Annealing -

heat treatment (about 1000° C) occurring heat treatment (about 1000° C) occurring after ion implantation to repair disruptions in after ion implantation to repair disruptions in the wafer crystal structure.the wafer crystal structure.

Alloying -Alloying - occurs after metal conductor strips placed on occurs after metal conductor strips placed on

wafer. Metal wafer. Metal alloyedalloyed (about 450° C) to wafer (about 450° C) to wafer surface to ensure good electrical conduction.surface to ensure good electrical conduction.

4242

Semiconductor Semiconductor ManufacturingManufacturingProcess StepsProcess Steps

Hundreds of steps are often required Hundreds of steps are often required in the wafer processing of an I.C.in the wafer processing of an I.C.

The four basic operations are used The four basic operations are used repeatedly to build the parts of the repeatedly to build the parts of the device in and on the wafer.device in and on the wafer.

4343

Building an MOS TransistorBuilding an MOS Transistor Circuit DesignCircuit Design

Block diagram of the circuitBlock diagram of the circuit SchematicSchematic Circuit layout - using CAD of the composite Circuit layout - using CAD of the composite

(composite - the entire circuit including (composite - the entire circuit including every layer)every layer)

The drawings are separated into layers and The drawings are separated into layers and digitized (translating to a digital database)digitized (translating to a digital database)

Final drawing completed on a computerized Final drawing completed on a computerized X-Y plotter tableX-Y plotter table

4444

Reticles and MaskReticles and Mask Reticle -a “hard copy” of the individual Reticle -a “hard copy” of the individual

drawing recreated in a thin layer of chrome drawing recreated in a thin layer of chrome deposited on a glass or quartz plate.deposited on a glass or quartz plate.

May be used directly in the photo process or May be used directly in the photo process or used to make a photo-mask or mask.used to make a photo-mask or mask.

Masks are used to pattern a whole surface in Masks are used to pattern a whole surface in one pattern transfer. Masks and reticles are one pattern transfer. Masks and reticles are similar in makeup.similar in makeup.

Reticles and Masks are produced in a Reticles and Masks are produced in a separate department or purchased from an separate department or purchased from an out side vendor.out side vendor.

A Mask “set”is supplied for each type of A Mask “set”is supplied for each type of

circuitcircuit..

Semiconductor Semiconductor ManufacturingManufacturing

Wafer Fabrication OverviewWafer Fabrication Overview

4646

Wafer Fabrication OverviewWafer Fabrication Overview

LayeringLayering PatterningPatterning DopingDoping Heat TreatmentHeat Treatment

4747

Layering OperationLayering Operation Thin layers of either conductor or insulator Thin layers of either conductor or insulator

material are added to a wafer of silicon using material are added to a wafer of silicon using one of two techniques.one of two techniques.

GrownGrown OxidationOxidation NitradationNitradation

DepositedDeposited Chemical Vapor DepositionChemical Vapor Deposition EvaporationEvaporation SputteringSputtering

4848

Patterning Patterning Series of steps to remove oxide from a new Series of steps to remove oxide from a new

layer to begin to form the circuit path.layer to begin to form the circuit path. These processes are known as Lithography, These processes are known as Lithography,

Masking or variations of those names.Masking or variations of those names. The repeating of this process creates the The repeating of this process creates the

surface parts of the device that make up surface parts of the device that make up the circuit.the circuit.

A most critical operation - sets dimensions A most critical operation - sets dimensions for devicefor device

4949

DopingDoping

Process whereby specific amounts of Process whereby specific amounts of dopant are embedded in the wafer dopant are embedded in the wafer through openings in the surface through openings in the surface layers.layers.

Thermal Diffussion and Ion Implant Thermal Diffussion and Ion Implant are two techniques commonly used are two techniques commonly used to accomplish this.to accomplish this.

5050

Heat treatmentHeat treatment Operations in which the wafer is heated Operations in which the wafer is heated

and cooled to obtain two specific and cooled to obtain two specific outcomes, “annealing” and “alloying”.outcomes, “annealing” and “alloying”.

Annealing is the repair of a wafer’s Annealing is the repair of a wafer’s crystal structure after ion implant has crystal structure after ion implant has disrupted it.disrupted it.

Alloying is heat treating the wafer after Alloying is heat treating the wafer after metal deposition to ensure good metal deposition to ensure good electrical conduction.electrical conduction.

5151

Layering Step 1Layering Step 1 The Step - This first layer, called Field or The Step - This first layer, called Field or

Start Oxide, is a layer of silicon dioxide Start Oxide, is a layer of silicon dioxide grown on a wafer through a process known grown on a wafer through a process known as oxidation. as oxidation.

The Purpose - for protection and the The Purpose - for protection and the creation of a doping barrier. creation of a doping barrier.

The Method - Thermally grown in a diffusion The Method - Thermally grown in a diffusion furnace.furnace.

The Illustration - Shows the new layer above The Illustration - Shows the new layer above the silicon substrate of a new wafer.the silicon substrate of a new wafer.

5252

1) Layering - field oxide1) Layering - field oxide

5353

Patterning Step 2Patterning Step 2 The Step - This pattern process leaves two The Step - This pattern process leaves two

holes in the field oxide known as source-drain holes in the field oxide known as source-drain holesholes

The Purpose - These holes define the source The Purpose - These holes define the source and drain areas of the transistor. and drain areas of the transistor.

The Method - Photolithography, including The Method - Photolithography, including masking process of spin, expose, develop of the masking process of spin, expose, develop of the pattern and etch to remove unwanted oxide.pattern and etch to remove unwanted oxide.

The Illustration - shows the oxide removed to The Illustration - shows the oxide removed to form the pattern.form the pattern.

5454

2) Patterning - source drain 2) Patterning - source drain holesholes

5555

Doping Step 3Doping Step 3

The Purpose -these “pockets” will form the P-N The Purpose -these “pockets” will form the P-N junctions required for the construction of junctions required for the construction of diodes and transistorsdiodes and transistors

The Step - creates two “N” type pockets in the The Step - creates two “N” type pockets in the wafer surface.wafer surface.

The Method - pockets formed through diffusion The Method - pockets formed through diffusion process and driven deeper through reoxidationprocess and driven deeper through reoxidation

The Illustration - shows resultant “N”pockets The Illustration - shows resultant “N”pockets (green) and new oxidation layer.(green) and new oxidation layer.

5656

3) Doping Layer3) Doping LayerN-type doping and reoxidation of source - N-type doping and reoxidation of source -

draindrain

5757

Patterning Step 4Patterning Step 4 The Step - patterning is used to remove The Step - patterning is used to remove

the field oxide in the gate region. the field oxide in the gate region. The Purpose - preparing the device for The Purpose - preparing the device for

the construction of the gate region.the construction of the gate region. The Method - spin, expose, develop and The Method - spin, expose, develop and

etch to form the new region.etch to form the new region. The Illustration - shows the material The Illustration - shows the material

removed forming the gate region. removed forming the gate region.

5858

4) PatterningGate region is formed

5959

Layering Step 5Layering Step 5 The Step - exposed silicon in gate region The Step - exposed silicon in gate region

and source and drain holes are reoxidized. and source and drain holes are reoxidized. The Purpose - preparation for contact The Purpose - preparation for contact

holes into source and drain regions.holes into source and drain regions. The Method - thermal oxidation in a The Method - thermal oxidation in a

heating furnace.heating furnace. The Illustration - the area above the The Illustration - the area above the

source and drain regions shows oxide source and drain regions shows oxide layer.layer.

6060

5) LayeringGate oxide is grown

6161

Patterning Step 6Patterning Step 6 The Step - two holes are patterned in the The Step - two holes are patterned in the

reoxidized source and drain regions.reoxidized source and drain regions. The Purpose - “contact” holes to The Purpose - “contact” holes to

connect the metalization layer to the connect the metalization layer to the source and drain regions.source and drain regions.

The Method - spin, expose, develop and The Method - spin, expose, develop and etchetch

The Illustration - shows the path opened The Illustration - shows the path opened to the source and drain regions.to the source and drain regions.

6262

6) PatterningContact holes are patterned into source/drain regions

6363

Layering Step 7Layering Step 7

The Step - deposition of a layer of metal The Step - deposition of a layer of metal across the entire surface of the wafer.across the entire surface of the wafer.

The Purpose - to provide a conduction The Purpose - to provide a conduction path to the source, drain and gate path to the source, drain and gate regions.regions.

The Method - low pressure chemical vapor The Method - low pressure chemical vapor deposition (LPCVD).deposition (LPCVD).

The Illustration - shows the metal layer The Illustration - shows the metal layer overlaying the entire device.overlaying the entire device.

6464

7) LayeringConducting metal layer is deposited

6565

Patterning Step 8Patterning Step 8 The Step - patterning the wafer to define The Step - patterning the wafer to define

the circuit path.the circuit path. the Purpose - removal of unwanted metal to the Purpose - removal of unwanted metal to

reveal electrical path for circuit operation.reveal electrical path for circuit operation. The Method - metal etch using high energy The Method - metal etch using high energy

plasma generated in RF field.plasma generated in RF field. The Illustration - the metal conduction layer The Illustration - the metal conduction layer

shown in blue above the source, drain and shown in blue above the source, drain and gate regions.gate regions.

6666

8) PatterningMetal layer is patterned

6767

Heat Treatment (Alloy) Heat Treatment (Alloy) Step 9Step 9

The Step - wafer is heated to alloy the The Step - wafer is heated to alloy the metal to the exposed source and drain metal to the exposed source and drain regions.regions.

This Purpose - ensures good electrical This Purpose - ensures good electrical contact.contact.

The Method - annealing in a nitrogen The Method - annealing in a nitrogen gas atmosphere. gas atmosphere.

The Illustration - the device appears the The Illustration - the device appears the same.same.

6868

9) Heat TreatmentMetal is alloyed to layer

6969

Layering Step 10Layering Step 10

The Step - application of a passivating The Step - application of a passivating layerlayer

The Purpose - to protect the wafer The Purpose - to protect the wafer surface during testing and packaging.surface during testing and packaging.

The Method - a polyimide spin which The Method - a polyimide spin which includes a curing process in diffusion.includes a curing process in diffusion.

The Illustration - Shows the final The Illustration - Shows the final protective layer.protective layer.

7070

10) LayeringProtective passivation layer is deposited

7171

Pad Mask Step11Pad Mask Step11 The Step - patterning process removing the The Step - patterning process removing the

passivating layer from over the terminal passivating layer from over the terminal pads on the periphery of the chip.pads on the periphery of the chip.

The Purpose - to provide electrical to the The Purpose - to provide electrical to the chip through the passivation layer.chip through the passivation layer.

The Method - a more involved masking The Method - a more involved masking process to remove the unwanted polyimide.process to remove the unwanted polyimide.

The Illustration - the opening above the The Illustration - the opening above the bond pad is shown.bond pad is shown.

7272

11) PatterningPassivation layer is removed over metal pads

7373

Electrical Test and SortElectrical Test and Sort The Steps - wafer is electrically tested The Steps - wafer is electrically tested

for each component of the process and for each component of the process and sorted for speed and functionalitysorted for speed and functionality

The Purpose - to determine if process is The Purpose - to determine if process is correct and functionality and correct and functionality and speciifcations of each device.speciifcations of each device.

The Method - electrical test and sort The Method - electrical test and sort test each device on the wafer in a test each device on the wafer in a systematic method.systematic method.

7474

Wafer SortWafer Sort Each chip is electrically tested for Each chip is electrically tested for

continuity and functionalitycontinuity and functionality Wafer is mounted on a vacuum chuck Wafer is mounted on a vacuum chuck

and aligned to thin electrical probes that and aligned to thin electrical probes that contact each bonding pad on the chip.contact each bonding pad on the chip.

Wafer probers are automated so that Wafer probers are automated so that after aligning with an automatic vision after aligning with an automatic vision system to the first chip the entire system to the first chip the entire sequence is completed without operator sequence is completed without operator assistance.assistance.

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Wafer Sort (cont)Wafer Sort (cont) Goals of wafer sortGoals of wafer sort

Identification of working chips before they go Identification of working chips before they go into packaginginto packaging

Characterization of the electrical parameters Characterization of the electrical parameters of the device (engineering tracking of device of the device (engineering tracking of device performance)performance)

Yield determination (good vs bad or non-Yield determination (good vs bad or non-functioning die) used for feedback to process functioning die) used for feedback to process engineering.engineering.

Bad die are usually marked with an ink dot or Bad die are usually marked with an ink dot or located on a computer map of the wafer.located on a computer map of the wafer.

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PackagingPackaging Sorted wafers are then moved to packaging.Sorted wafers are then moved to packaging. This may be off shore or in another part of the This may be off shore or in another part of the

facility,facility, The wafers are sawn into chips with a diamond The wafers are sawn into chips with a diamond

saw and the good die separated from the badsaw and the good die separated from the bad The chips are them mounted into lead frames The chips are them mounted into lead frames

and die attached.and die attached. The bond pads are wired bonded and the The bond pads are wired bonded and the

package is finally sealed.package is finally sealed.