lappeenranta university of technology lut energy
TRANSCRIPT
LAPPEENRANTA UNIVERSITY OF TECHNOLOGY
Faculty of Technology
LUT Energy
Electrical Engineering
Savelii Zhukov
Loss Modelling of Three-Level Inverters controlled with Space Vector Modulation
Technique
Examiners: Professor Olli Pyrhönen
M.Sc. Tatu Musikka
Advisors: M.Sc. Raimo Juntunen
ABSTRACT
LAPPEENRANTA UNIVERSITY OF TECHNOLOGY
Faculty of Technology
LUT Energy
Electrical Engineering
Savelii Zhukov
Loss Modelling of Three-Level Inverters controlled with Space Vector Modulation
Technique
Master’s Thesis
2012
87 pages, 33 figures, 13 tables and 10 appendices
Examiners: Professor Olli Pyrhönen
M.Sc Tatu Musikka
Keywords: ANPC, Losses, SVM, IGBT, Three-level inverter
The objective of this master’s thesis is to investigate the loss behavior of three-level ANPC
inverter and compare it with conventional NPC inverter. The both inverters are controlled
with mature space vector modulation strategy. In order to provide the comparison both
accurate and detailed enough NPC and ANPC simulation models should be obtained.
The similar control model of SVM is utilized for both NPC and ANPC inverter models. The
principles of control algorithms, the structure and description of models are clarified. The
power loss calculation model is based on practical calculation approaches with certain
assumptions. The comparison between NPC and ANPC topologies is presented based on
results obtained for each semiconductor device, their switching and conduction losses and
efficiency of the inverters.
Alternative switching states of ANPC topology allow distributing losses among the switches
more evenly, than in NPC inverter. Obviously, the losses of a switching device depend on its
position in the topology. Losses distribution among the components in ANPC topology
allows reducing the stress on certain switches, thus losses are equally distributed among the
semiconductors, however the efficiency of the inverters is the same.
As a new contribution to earlier studies, the obtained models of SVM control, NPC and
ANPC inverters have been built. Thus, this thesis can be used in further more complicated
modelling of full-power converters for modern multi-megawatt wind energy conversion
systems.
ACKNOWLEDGEMENTS
This thesis has been written to Electrical Engineering Department of Lappeenranta
University of Technology in the spring semester 2012 during my studies as a double-degree
student there.
Firstly, I wish announce my gratitude to Professor Olli Pyrhönen. I am thankful to him for
his right path guidance during this work and suggestive comments. I also would like to thank
Dr. Katja Hynynen on the first steps of the work and both Mr. Tatu Musikka and Mr. Raimo
Juntunen for their words of advice, discussions and patience. Without their help in difficult
times it would be much harder to obtain any results, and I appreciate it.
Secondly, I also wish thank my colleagues and people both in Finland and Russia for their
support and understanding during my studies here: Prof. Alexander Mikerov, Dr. Victor
Vtorov, Nikita Potashko, Peter Leshev and Lina Shilkova. I am grateful to you.
Finally, my thanks would be incomplete, if I would not thank my mother Dr. Elvira Zhukova
for her comprehensive support. I appreciate it and I will always be thankful to you.
TABLE OF CONTENTS
1 INTRODUCTION 7
1.1 WIND ENERGY CONVERSION SYSTEMS 8
1.1.1 Frequency converters in WECS 12
1.2 CONVERTER TOPOLOGIES FOR HIGH POWER APPLICATIONS 13
1.2.1 Three-level Neutral Point Clamped inverter 19
1.2.2 Three-level Active Neutral Point Clamped inverter 22
1.2.3 Switching devices of the inverter 25
2 POWER LOSSES IN THE INVERTER 28
2.1 COMMUTATIONS AND LOSSES IN THREE-LEVEL NPC INVERTER 28
2.2 COMMUTATIONS AND LOSSES IN THREE-LEVEL ANPC INVERTER 32
2.2.1 Loss balancing in three-level ANPC converter 38
2.3 POWER LOSSES OF SEMICONDUCTOR DEVICES 40
2.3.1 IGBT and diode switching losses 44
2.3.2 IGBT and diode conduction losses 45
3 DYNAMIC SIMULATION AND MODULATION PRINCIPLES 49
3.1 MODULATION STRATEGIES FOR MULTILEVEL CONVERTERS 49
3.2 SPACE VECTOR MODULATION OF NPC INVERTER 52
3.2.1. Determination of sector and region of SV 55
3.2.2 Determination of switching states and their sequences 57
3.3.3 Calculating the switching times and durations 62
4 SIMULATION METHODS AND RESULTS 65
4.1 MODELLING OF THREE-LEVEL INVERTER CONTROLLED WITH SVM 65
4.1.1 SVM control of NPC inverter model 66
4.2 SIMULATION RESULTS FOR NPC AND ANPC INVERTERS 71
4.2.1 Comparison of losses calculation results and efficiency 75
5 SUMMARY AND CONCLUSIONS 78
REFERENCES 80
LIST OF SYMBOLS
Roman letters
E Energy [J]
f Frequency [Hz]
I, i Current [A]
k Number of base vectors in a sector [-]
L Inductance [H]
m Number of phases [-], Modulation index [-]
N Number of switching states [-]
n Number of voltage levels [-]
P Power loss [W]
R Resistance [Ω]
T, t Time period [s], Switching duration [s]
U Voltage [V]
V Unity voltage vector [-]
Greek letters
α Phase angle of voltage vector [rad]
ϑ Junction temperature [°C]
Subscripts
av Average value
0 Initial, Default value
b Blocking
CE Collector-emitter
com Commutation
C, cond Conducting, conduction
d Delay, Discretization
DC Direct Current, DC-link parameter
D Diode parameter
f Fall, Fundamental
i Current parameter
IGBT IGBT parameter
in Inner
LL Line-to-line
load Load parameter
loss Losses
min Minimum
n Nominal,
npc Neutral Point Clamped
off Turn-off state
o, on Turn-on state
out Outer
ph Phase
r Rise
rated Rated value
rec Recovery
ref Reference
RMS Root Mean Square
sec Sector
sw Switching
s Sampling
tol Tolerance
v Voltage parameter
x Number of phase
LIST OF ABBREVIATIONS
AC Alternating Current
ANPC Active Neutral Point Clamped
CHB Cascade Half Bridge
CSI Current Source Inverter
D Diode
DC Direct Current
DFIG Doubly Fed Induction Generator
DPGS Distributed Power Generation System
FLC Flying Capacitor
G Generator
IGBT Insulated Gate Bipolar Transistor
ML Multi-Level
NPC Neutral Point Clamped
NTV The Nearest Triangle Vector
PEBB Power Electronics Building Blocks
PEC Power Electronics Converter
PF Power Factor
PMSG Permanent Magnet Synchronous Generator
PWM Pulse-Width Modulation
RMS Root-mean-square
S Switch
SVM Space Vector Modulation
THD Total Harmonic Distortion
VSI Voltage Source Inverter
VSC Voltage Source Converter
VSWT Variable Speed Wind Turbine
WECS Wind Energy Conversion System
WTG Wind Turbine Generator
WWEA World Wind Energy Association
7
1 INTRODUCTION
Nowadays the amount of installed variable speed wind turbines (VSWT) increased, since
the importance of power electronics converters (PECs) performance also becomes crucial,
as PEC provides an interface between wind turbine generator (WTG) and the electrical
grid. In general, the performance of PEC is widely discussed in literature from two points
of view, which are the efficiency of the converter and the quality of output voltages and
currents. These issues become vital for PECs, as the share of energy produced by wind
energy conversion systems (WECS) increases worldwide annually. So, mature and
extensively used two-level topology converters dominating on the market are replaced by
the converters with multi-level (ML) including three-level topology with better
performance. The performance of the three-level inverter as an integral part of the three-
level converter is investigated in this work. As a new contribution to earlier studies, both
simulation models of three-level active neutral point clamped (ANPC) and neutral-point
clamped (NPC) inverters are presented in this study, combined with space vector
modulation (SVM) strategy and simulations in order to adequately assert and compare their
efficiencies.
Thus, the objective of this thesis is to design a simulation model of three-level (ANPC)
inverter with a space vector pulse-width modulation (SVPWM) control module in order to
compare its performance with neutral-point clamped (NPC) inverter. So, a simulation
model of NPC inverter should be also designed.
In general, the thesis comprises four parts with summary and conclusions. The first part is
devoted to frequency converters utilized in wind energy conversion systems, different
topologies of available medium-voltage inverters and their switching devices. In addition,
NPC and ANPC topologies are investigated here in details.
8
Power losses occurring in semiconductor devices of the inverter are discussed in the second
part of the thesis. The nature of switching and conduction losses of these components is
investigated here. In addition, methods for losses calculation are also presented in this part.
In the third part of the thesis available modulation strategies are discussed. Attention is
mostly focused on the space-vector modulation (SVM) principle, as exactly this method is
used in simulation models.
In the fourth part simulation models are described as well as obtained results are presented.
The implementation of the utilized SVM principle and techniques of efficiency calculation
are also presented here. The obtained voltage and current curves, as well as calculated
results can be found here. Finally, the summary with discussion of obtained results and
conclusions are presented. The further possible improvements and development of the
models are also discussed here.
1.1 Wind energy conversion systems
Greenhouse effect control has been one of the crucial global challenges, especially for the
last couple decades, when more evidences of global warming had been reported. It is
known that the further greenhouse effect developments can be eliminated only if CO2
emissions are reduced significantly. Recently, the European Commission has announced a
proposal for a new Energy Policy for Europe. One of the issues of the Energy Policy is to
increase the share of renewable energy sources in the overall generation production in order
to decrease CO2 emissions by at least 20% by 2020 and 50% until 2050 (MELICIO et al
2010). So, environmental concerns become extremely relevant for electric companies as
regulations on pollutions become more severe as well.
9
Another issue is that in general, it is predicted that prices on fossil fuels will increase
annually in next decades (DECC 2011). In addition, governments of some countries, for
instance in Germany, announced the plan to renounce the nuclear power plants on the
territory of the country or at least drastically reduced its share in electricity generation.
Hence, it is expected that renewable energy sources will be an important part of the future
Energy Policy for Europe. Even nowadays distributed power generation systems (DPGS),
including for instance wind turbines, photovoltaic and solar panels, become an integral part
of modern power generation sector (MELICIO et al 2010).
Among all DPGSs, WECSs are the most mature and rapidly developing technology. Thus,
its annual installation growth rate exceed 30% every year and sets new records, for instance
42 GW of new capacity was installed in 2011. According to the preliminary published data
gathered by World Wind Energy Association (WWEA 2012), the total capacity of wind
power generation reached 239 Gigawatt worldwide in 2011, and it is enough to cover 3 %
of the world's electricity demand already.
Figure 1. Wind power world total installed capacity in GW (WWEA 2012)
10
As it can be seen from Fig.2, any modern WECS comprise three integral aspects:
aerodynamic, mechanical and electrical ones. The aim of this kind of the complex system is
to convert motional energy of the wind into electrical power.
Figure 2. Wind energy conversion system general structure (KIM et al 2010)
In this thesis the issues related only to electrical aspect are discussed. Variable-speed wind
energy conversion systems offer the following advantages: mechanical stress is reduced,
torque oscillations are not transmitted to the grid, and below rated wind speed the rotor
speed is controlled to achieve maximum aerodynamic efficiency. Thus, induction
generators or doubly fed induction generators (DFIGs) fully dominate on the variable-speed
WECSs market nowadays (MELICIO et al 2010). However, as alternative for generator
unit of these conventional variable-speed WECSs with DFIGs, modern permanent magnet
synchronous generators (PMSGs) have been introduced recently. Advantages of this
approach can be found in (LAMPOLA 2000). In particular, the whole system structure with
PMSG as a generator unit is presented in Fig.3.
Figure 3. Permanent magnet wind power drive (PYRHONEN et al 2011)
11
From the structure scheme in Figure 3 it can be seen clearly that such a directly driven wind
turbine has gearless nature and obviously low speed. In general, in gearless drive multi-pole
low speed high power generators are preferred. In addition, the generator is completely
decoupled from the grid in this variable-speed WECS structure with full-power converter.
One of the advantages of full-power converter wind energy conversion systems is ability to
control active and reactive output power (NALLAVAN et al 2011). The possible converters
structures which are commonly used in wind power applications are considered in the
following chapters.
According to (MELICIO et al 2010; WIZELIUS 2006), in recent years, there has been a
kind of new tendency of wind turbine generators (WTGs) design revealed. Thus, the rotor
size of new WTGs has been significantly increased in order to extract more power from
wind and improve performance of wind energy conversion systems. In general, the cost
structure for wind power applications is based on the fact, that a turbine shares 40-80% of
the whole costs depending on onshore or offshore application. As a turbine comprises both
generator unit and gearbox components, eliminating gearbox and related mechanical
components may be preferable alternative.
In addition, reliability is an important factor for economic efficiency since maintenance and
repair are extremely expensive and not guaranteed at any time, for instance due to difficult
access to the offshore wind turbines especially during periods of bad weather conditions.
Therefore, gearless approach is more preferable in the most cases, as gearbox breakdown
can be one of the common causes of the whole system failure and it requires a plenty of
maintenance. In addition, the gearbox and its own losses obviously affect the efficiency of
the whole system and causes unpleasant noise.
In (BAROUDI et al 2005) it is also stated that PMSG can be recommended alternative as
well even for newer smaller scale turbine design, since it allows better performance and
higher efficiency with smaller wind turbine blade diameter. More detailed discussions
about this promising concept of variable-speed WECS with PMSG and its comparison with
12
conventional DFIG approach especially for large offshore wind farm applications can be
found in (LAMPOLA 2000) and (RAMTHARAN et al 2007).
1.1.1 Frequency converters in WECS
As described earlier, the contribution of power electronics is crucial for wind energy
conversion systems, as increasing share of wind in power generation will influence
significantly the dynamic behaviour of the power system. In addition, network operators
have to ensure that consumer power quality is not compromised. Hence, new technical
challenges emerge due to the increased wind power penetration, dynamic stability and
power quality, so it consequently implies new challenging requirements and demands for
power electronics converters (PECs) either.
The main aim of a PEC in any wind energy conversion system it has been developed for is
to integrate wind power with the electric grid. Moreover, power electronics system is used
to achieve variable speed operation while wind speed varies either. In addition, the use of
PECs for variable-speed operating WECSs allows enhancing its power extraction. In
variable-speed operation, a control method also designed to extract maximum power from
the wind turbine and provide desirable constant grid voltage and frequency, and this
controlling methods issue is discussed in Chapter 3 of this work.
Hence, full-power converters offer both variable speed operation of wind turbine and its
smooth integration to grid. In general, according to (NALLAVAN et al 2011) contribution
of modern semiconductor full-power PECs in WECSs can be summarized as follows:
Based on the wind speed, the generator speed is controlled by means of PEC, thus
variable speed operation is implemented, including gearless approach as well;
Enhancing of maximum power extraction from WTG;
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Constant power factor (PF) and as sinusoidal as possible output voltages and
currents are obtained, in order to supply quality power to the grid;
High level of reliability of the system, including both protection of the generating
unit and the grid;
The possibility of bi-directional power flow.
Thus, frequency converters can be determined as integral part of directly driven WECS
with PMSG. It should be also mentioned, that PECs for the modern trend of multi-
megawatt wind turbines for offshore applications should be able to provide higher voltage
and power capability. The possible topologies of available approaches for converters
utilized in WECSs are considered in the following chapter.
1.2 Converter topologies for high power applications.
The increase of the power capabilities of modern wind turbines in general, and wind
turbines with PMSGs in particular, definitely influence on requirements and appearance of
new power converter topologies capable to drive all desired power. In addition, the trend of
development higher voltage and current power semiconductor devices also still continues.
Thus, according to the latest generation of power semiconductor devices is capable to
support high-level voltages in the ranges up to 20kV (SUI 2007). However, such kind of
devices does not fully dominate even in high power application, due to utilization of variety
of topologies using medium power semiconductors. Further semiconductor devices used in
PECs of WECSs are considered in chapter 1.2.3.
The classification of modern available PEC topologies for high power applications is
presented in Figure 4.
14
Figure 4. Classification of high-power converters. Adopted from (FRANQUELO et al 2008)
In general, among all represented converter topologies there are three the most interesting
ones from wind power generation point of view, they are two-level PWM converters,
matrix converters and multilevel (ML) converters.
The most conventional type of PEC for variable speed wind turbine (VSWT) widely
available in the current energy market is two-level PWM converter. It has relatively low
cost due to its maturity technology. Basic scheme of two-level converter is presented in
Figure 5, and it can be clearly seen two voltage source inverters (VSIs) on both generator
and grid sides divided by DC-link capacitor or just often called DC-link. In general, the
DC-link capacitor of a converter is an energy storage component of the system. In addition,
the capacitor of DC-link is the most vulnerable component of any indirect converter and it
significantly affects reliability of the system. In general, the capacitance of the intermediate
of the DC-link significantly influence on the performance of the VSI. Thus, it is reported in
15
(PYRHONEN 2010), that generally DC-link capacitor is dimensioned in a way to be in a
range about 20 µF per one ampere of the rated value of the converter current.
Figure 5. Basic scheme of 2-level converter. Adopted from (KIM et al 2010).
There are some key drawbacks of 2-level converters which limit their application in
modern VSWT and yield to their displacement from the wind energy market by ML, in
particular 3-level converters. Among them can be noticed relatively high transients and
switching losses, oversized semiconductor components and poor quality of harmonic
content of output voltages and currents comparing with ML converters, which yields to
necessity of including complex and expensive filters (KIM et al 2010).
Another alternative approach is utilization of matrix converters, which have a key
difference from the both 2-level and ML converters in such a way, that the matrix converter
is capable of conversion of variable frequency AC of generator side directly into constant
AC frequency of the grid. Thus, passive DC-link capacitor is removed from such AC-AC
converter design, consequently more reliable performance and smaller dimensions of
converter system are obtained. However, the number of semiconductor switching devices is
also significantly increased for this topology.
As shown in Figure 6, the basic scheme for three-phase matrix converter connecting
generator unit with the grid consists of 9 semiconductor switches, which controlled in such
a way that any of three switches in one common leg cannot be turned on instantly. Then, to
provide bi-directional power flow total number of switches should be doubled up to 18.
Generator side: Rectifier DC-link Grid side: Inverter
16
Clarified performance of matrix converters can be found in references (WHEELER et al
2002) and (JIA et al 2007).
Figure 6. Basic scheme of matrix converter (KIM et al 2010).
Despite certain advantages, some undesirable features still limit wide industrial use of
matrix converters. They can be reported as sensitivity to distortion in input power supply
and grid disturbances due to the lack of reactive component in the power circuit and rapid
change in the input voltage frequency when used in WECSs. In addition, the level of output
voltage is limited by certain level, and relatively high conduction losses should be
mentioned (KIM et al 2010).
The most promising PEC approach for modern VSWT is multilevel converters. Compared
with two-level converters, ML converters, which have various designs, comprise three or
more voltage levels. Such a design results in certain advantages. Firstly, lower total
harmonic distortion (THD) of output signals is obtained, compared with conventional 2-
level converters. It can be noticed as one of the key issue, due to increased share of wind
power contribution in total power generation. Secondly, multilevel converters are capable
for higher power capability, even using medium power semiconductor switches, due to
voltage sharing between levels, so ML converters are fully suitable for multi-megawatt
scale VSWTs. This results also in reduction of switching losses, since voltage values during
transients are also significantly decreased, as well as switching frequency can be increased
drastically compared with 2-level converters. In addition, one DC-link capacitor, is
replaced by two or more ones, which are also should be chosen during the design of the ML
17
converter. However, as capacitors are the most expensive elements of the converter, the
number of semiconductor components and capacitors in ML converter yields to increased
costs for such applications (IKONEN et al 2005).
In general, for all ML converters the following formula for different possible converter
switching states is valid
Nsw=nm, (1)
where n is the number of voltage levels in the DC-link and m is the number of phases of the
converter. Thus, for three-phase two-level, three-level and five-level converters the variety
of different switching states is 8, 27 and 125, respectively.
Considering rectifier part of the ML converter, it should be mentioned that conventional
approach usually includes 6-pulse rectifier on the generator side. However, such an
approach cannot provide quality performance of full-power ML converter for the
application of PMSG in VSWT, which is in general scope of this thesis, due to the fact that
it cannot be fully controlled. The full-control converter implies the presence of controlled
both inverter and rectifier, which design is fairly demanding task. However, requirement of
full-controlled converter is crucial for modern multi-megawatt WTGs, in order to regulate
torque, rotational speed and power (MULJADI et al 1998).
In addition, unity power factor (PF) is required for modern high power rating VSWT, and
rectifier should be capable to provide it along with harmonic requirements of the grid.
Furthermore, regenerative capability and active mitigation of the system oscillations should
be provided. Therefore, it is crucial that the rectifier is an active part of the full-controlled
ML converter in order to provide harmonic mitigation and unity power factor for the whole
speed and load range (HAITHAM et al 2010).
Despite all mentioned above, multilevel converters are, however, still limited by drawbacks
of voltage unbalances, count of components and relatively complex modulation
approaches. In particular, a critical issue in three-level converters is the design of the DC-
18
link capacitors, which already mentioned in previous discussion. Thus, special attention
should be paid to the unbalance in the voltage of the capacitors for the three-level
converters, which may cause a certain control problems (MELICIO et al 2010; KIM et al
2010).
Figure 7. a) Three-level FLC VSI; b) Three-level CHB VSI (POTASHKO 2011)
According to classification presented in Figure 4, except neutral point clamped (NPC)
converters there are also so called cascade half-bridge (CHB) and fly-capacitor (FLC)
multilevel converters available for high power applications, in particular for already
mentioned multi-megawatt WTGs. FLC voltage source converters (VSCs) are characterized
with twice higher switching losses than NPC converters with the same switching frequency,
in addition its design requires 5 capacitors comparing with 2 capacitors for the same 3-level
NPC design, so the cost of the system drastically increased. On the other hand, as it can be
seen from Figure 7 the total amount of semiconductor components is less than in NPC
application.
Another available approach CHB VSC is not in favour for this work due to its general
complicity and relatively high number of switching devices which results in increased
dimensions and high cost of the system. Furthermore, high switching losses are another con
of CHB VSCs. Therefore, the detail designs of CHB and FLC VSCs are outside the focus
of this thesis, however they can be found in the literatures (RUDERMAN et al 2009),
a) b)
19
(HAITHAM et al 2010) and (MALINOWSKI et al 2010). Further, only scheme of 3-level
NPC inverter as a part of the converter is considered, which model and control strategy has
been discussed and implemented in the following chapters of the thesis.
1.2.1 Three-level Neutral Point Clamped inverter.
To build adequately performing simulation and control model of the NPC inverter the
principle of its design and performance should be fully clarified. So, the scheme description
according to Figure 8 follows and possible switching states are represented below.
In general, the circuit comprises three phases connected to the common DC-link capacitors.
The whole scheme consists of 12 active switches, isolated gate bipolar transistors (IGBTs)
in our case, with inversed power diodes connected in parallel and 6 neutral point clamp
diodes. Thus, switches S11, S21 and S31, either S14, S24 and S34 are called outer switches Sout,
as well as corresponding inverse diodes have the same indexes and also named Dout. All
three phases have the same structure and behaviour with assumption that load phases are
also equal and balanced, since further the first subscript number means the phase number is
replaced with ‘x’. However, it should be kept in mind that this assumption is valid only in
cases, when rough transients are not considered, as it is assumed during the simulations in
this thesis. Thus all the 6 remaining switches Sx2 and Sx3 and corresponding to them inverse
or free-wheeling diodes are named Sin and Din, respectively. The group of 6 diodes
connected to the neutral point further is marked as Dx5 and Dx6 or Dnpc.
20
Figure 8. Three-phase three-level NPC inverter (BRUCKNER 2005).
As it was mentioned in previous chapter and according to (1) the number of possible
converter switching positions for three-phase 3-level inverter can be calculated as
Nsw=nm=3
3=27. (2)
All these switching positions correspond to the three possible states of each inverter phase
leg. Thus, independently of two other phases each phase terminal of the inverter can be
connected to DC bus in the three terminal points: upper positive ‘+VDC/2’ DC rail, neutral
‘0’ point or lower negative ‘-VDC/2’ DC rail. Thus, possible switching positions table of
three-level NPC inverter can be formed, as presented below.
Table 1. Switching positions for a phase of three-level NPC inverter.
State
Switch position
Sx1 Sx2 Sx3 Sx4
’+VDC/2’ 1 1 0 0
’0’ 0 1 1 0
’-VDC/2’ 0 0 1 1
21
Then, consider the available current paths in each phase of the inverter both for positive and
negative phase currents formed by certain switch positions considered previously. From the
Figure 9 it can be clearly seen that all IGBTs and diodes might be stressed with maximum
levels of voltage and current Îph and VDC/2 respectively, and definitely these parameters
influence on the selection of the semiconductor devices for certain application
(BRUCKNER 2005).
Figure 9. Conduction paths for one phase of three-level NPC inverter (BRUCKNER 2005)
In principle, at any state of a phase two semiconductor devices provide a conduction path
for one direction. Thus, in case of upper path positive current flows through active IGBT
switches, whereas inverse diodes provide negative direction of current flow. Otherwise,
lower current path provide positive current flow through the power diodes, while negative
current flows through IGBTs there. It should be kept in mind that in NPC inverters active
IGBT switches, which are not utilized in forming corresponding path for current flow,
should be switched off, in order to prevent short-circuit failure. In contrast to ‘+’ and ‘-’
states, in zero state ‘0’ both upper and lower paths of neutral tap are utilized in order to
provide bi-directional current flow as it shown in Figure 9. So, in the NPC voltage source
inverter the utilization of the upper or lower NPC path is determined by itself with the
natural direction of the phase current (BRUCKNER et al 2005).
Thus a relatively simple theoretical operation principle allows to create easy implemented
control algorithm, especially thanks to symmetrical switching states for upper and lower
22
halves of the NPC inverter topology. Since, generally control signals may be formed only
for the upper Sx1 and Sx2 switch branches. On the other hand such conduction paths created
by switching positions create uneven power loss distribution between switching devices.
More detailed discussion for both control and losses issues for NPC inverter are presented
in Chapters 2 and 3.
1.2.2 Three-level Active Neutral Point Clamped inverter
Bruckner (2001) first introduced the modified design of NPC converter, which is referred
as active neutral point clamped (ANPC) converter. This 3-level ANPC design was
developed in order to overcome the main drawback of conventional NPC approach, namely
the uneven loss distribution among the semiconductor devices, limiting output power of the
converter. This drawback has been eliminated with adding two active switching devices,
for instance IGBTs, in antiparallel with the clamping diodes. In general, such a modified
design provides additional current paths, but the total number of active switches is
increased up to 18, as it can be seen from topology of ANPC in Figure 10.
Figure 10. Three-phase three-level ANPC topology. Adopted from (BRUCKNER 2005)
23
Consider any phase leg of the ANPC topology shown in Figure 10, in order to obtain
possible switching positions and states of the phase. Thus, additional active NPC switches
referred as Sx5 and Sx6 allow implement more than one state to connect the phase to the
neutral tap. These new zero switching positions form possible phase states ’0Up1’, ’0Up2’,
’0Low1’ and ’0Low2’ either positive ’+VDC/2’ and negative ’-VDC/2’, which are presented
in Table 2.
Table 2. Switching positions for a phase of three-level ANPC inverter.
State
Switches position
Sx1 Sx2 Sx3 Sx4 Sx5 Sx6
’+VDC/2’ 1 1 0 0 0 1
’0Up1’ 0 1 0 1 1 0
’0Up2’ 0 1 0 0 1 0
’0Low1’ 1 0 1 0 0 1
’0Low2’ 0 0 1 0 0 1
’-VDC/2’ 0 0 1 1 1 0
Comparing states of the NPC and ANPC inverters presented both in Table 1 and Table 2,
one can noticed that positive and negative states are similar for both topologies. The only
except is additional turned on switch Sx6 for ’+VDC/2’ state, which provides an equal
voltage sharing between Sx3 and Sx4. Similarly, the same function is provided by Sx5 for Sx1
and Sx2 in ’-VDC/2’ state. Thus, the voltage balancing is guaranteed across the inner
switches.
In contrast to NPC topology described in previous chapter neutral tap current paths of
ANPC topology are implemented with 4 states. Thus, if active NPC switches Sx2 and Sx5
are turned on ’0Up1’ and ’0Up2’ states are obtained, and the phase current is conducted
through the upper path of the neutral tap in both directions. Analogously, turned on Sx3 and
24
Sx6 lower inner switches provide current conduction in both directions through the lower
path of the neutral tap in ’0Low1’ and ’0Low2’ sates. Obviously, all the four inner switches
Sx2, Sx5 and Sx3, Sx6 also can be turned on instantaneously, but this state is not considered
due to unclear current distribution among the devices (BRUCKNER et al 2005). In
addition, in case of upper NPC path is utilized IGBT Sx4 may be both turned on or off, as
well as Sx1 for lower neutral path. These additional switching alternatives can be utilized in
distribution of switching losses among the active switches. Thus, current paths
implemented by these four inverter neutral states as well as positive and negative paths for
the ANPC inverter are shown in Figure 11.
Figure 11. Possible conduction paths for one phase of three-level ANPC inverter. a) ’+VDC/2’ state;
b) ’0Up1’ and ’0Up2’ states; c) ’0Low1’ and ’0Low2’ states; d) ’-VDC/2’ state (BRUCKNER 2005).
25
1.2.3 Switching devices of the inverter
In recent years, the field of high power applications has been one of the most actively
researched and developed area of power electronics, mainly due to increased power level
needs of industry and power generation. The development of new power semiconductor
devices obviously increases the power capability of medium voltage converters for high
power applications.
The development of high power converters started in the middle of 1980s with 4500V gate-
turn-off (GTO) thyristors introduced in commercial market. The GTOs dominated on the
market of high power applications until the end of 1990s, when insulated gate bipolar
transistors (IGBTs) and gate commutated thyristors (IGCTs) technologies were developed.
Nowadays these switching devices are mostly used in high power applications, including
multi megawatt VSWTs, due to its controllability, quality switching characteristics and
reduced power losses (RODRIGUEZ et al 2007).
Nowadays, Siemens, ABB and Converteam offer some three-level NPC inverters in range
of 2.3-6.5kV based on IGCT and IGBT modules technology. The selection of a certain
multi voltage inverter depends on a certain criteria. The most important are its initial and
operating cost, reliability, technical performance and power capability. The initial cost of
the inverter is largely influenced by the cost of the semiconductor devices due to its
contribution of about 40% of the total material cost of the NPC inverter. Operating cost is
mostly assesses with maintenance and efficiency of the inverter. Power capability and
corresponding dimensions are also important issues especially for WTG because of limited
space in windmills. The guideline for selection technique of appropriate application of 3-
level NPC converters can be found in (SAYAGO et al 2008).
26
High voltage IGBT module is one of the most promising device technology nowadays,
which capable to provide standard voltage level ratings for high power applications, as it is
presented in Table 3 (SAYAGO et al 2008).
Table 3. Voltages of three-level NPC inverter available on the market.
Line-to-line voltage of
the system (DC-link
voltage)
Semiconductor device
voltage
2.3kV 3.3kV
3.3kV 4.5kV
4.16kV 6.5kV
However, it should be kept in mind that to achieve an output line-to-line voltage the
minimum DC-link voltage should be applied to switching device, calculated as follows
rmsLL,minDC, 2VV (3)
To determine the nominal DC-link voltage of the converter 4% f the theoretical value is
added in order to eliminate imperfections of a real system
minDC,nDC, 04.1 VV (4)
One of the feature of IGBT converters is that its modern technology is based on so called
power electronic building blocks (PEBBs), which include IGBT modules and have the
same interfaces and dimensions independently from their voltage levels (SAYAGO et al
2008). For instance, some parameters for the model of the inverter built during this work
have been taken directly from the datasheet of the 2.3kV IGBT module FZ1200R33KF2C
by Infineon, which can be found in Appendix 1.
The IGBTs are very popular in high power and high frequency applications, including
three-level NPC inverter simulated in this work. However, these applications require
27
sophisticated thermal management systems to protect the utilized IGBTs and provide
reliable performance of the whole application system in general, as the devices commonly
operate with minimum safety margins due to the cost considerations (RAJAPAKSE et al.
2005).
28
2 POWER LOSSES OF THE INVERTER
In general, power losses of any power electronic equipment comprise of power losses of all
components contained in the equipment. In electrical components the power losses caused
in the resistances of these components, so power losses, by nature, means heating of the
component. Such an undesirable in the most of applications heating limits the load
capabilities and affects either efficiency of the inverter or efficiency of the whole system. In
addition, if the temperature of any component of the system exceed a certain acceptable
limit due to untransfered heat or overload of the component, it could be finally damaged,
which in its turn might cause the failure of the whole system.
Conduction and switching losses of semiconductor devices occurred in three-level NPC
inverter during its performance are discussed in this chapter. In addition, along with loss
behaviour of the inverter, calculation methods used to assess amount of losses and its
implementation in the simulation model are also discussed here.
2.1 Commutations and losses in three-level NPC inverter
In general, switching and recovery losses are created during the commutation processes
between different switching states. The following discussion on commutations of NPC
converter is based on (BRUCKNER 2005). They are worth to mention it here since the
significant part of the thesis research is focused on losses occur during the inverter
performance. In the following discussion only on commutations obtained with positive
phase current direction are considered, however the resulting figures and tables for both
positive and negative currents are presented as well.
29
As in previous chapter the commutation processes and losses occurred during them are
considered only for one ‘x’ phase of the inverter, as the principles are the same for all the
three phases. Firstly, consider the commutation from positive DC-rail, referred as ‘+’ state,
to neutral tap ‘0’ state, which initiated by turning off the outer switch Sx1, and results in the
current flow through the NPC diode Dx5. Then inner active switch Sx3 is also turned on,
however turn-on losses do not occur in it, because there is no current there during the
commutation. Instantaneously, Sx2 and Sx4 stay turned on and off, respectively. Thus, Sx1
and Dx5 devices are utilized in commutation, but only Sx1 experiences significant turn-off
losses, as turn-on losses of free-wheeling diodes are negligibly small and are not taken into
account during the further discussion and simulations as well.
Then, consider the reverse commutation from zero state’0’ to positive one ‘+’. It is initiated
by turning off Sx3, however turn-off losses are not experienced there, as case for positive
current is under observation. Following, after dead time Sx1 is turned on, since turn-on
losses occur in it, while Dx5 experiences recovery losses. Thus, both commutations are
presented in Figure 12, where Sx1 and Dx5 are encircled, as they experience switching losses
during these commutations for positive load current.
The commutations result switching losses in Dx1 and Sx3 at negative phase current also
shown in Figure 12. In this case the principles of losses behaviour in these devices are the
same as it was described for positive load current iph.
Figure 12. Commutations for both from ‘+’ to ‘0’ states and reversed. a) for positive load current b) for
negative load current. Adopted from (BRUCKNER 2005).
a) b)
30
The commutation from zero state ‘0’ to negative state ‘–‘ and stressed switching devices
are shown in Figure 13. During the commutation four devices are employed. Thus, the
commutation is initiated by turning off the inner switch Sx2, immediately the current is
forced to Dx3 and Dx4. Then, Sx4 is turned on, while Sx3 is in on state. During these
transients only Sx2 experiences essential turn-off losses for positive current direction.
However, for negative load current this commutation yields significant turn-on losses in Sx4
and recovery losses in Dx6, as Sx3 stays in turn-on state during the commutation.
The back reversed commutation principle is based on turning off Sx4 firstly and turning on
Sx2 then. Thus, for positive load current Dx4 experiences recovery losses, while turn-on
losses in Sx2 occur. It should be noticed that although Dx3 connected in series with Dx4 also
turns off by nature, it does not face turn-off losses, due to Sx3 remains turned on and there is
no voltage across the Dx3 during the commutation, while the whole blocking voltage UDC/2
is adopted by Dx4 only. In case for negative load current turn-off losses occur in Sx4, as it is
turned off firstly. There no any losses are experienced by other devices for this
commutation in case of negative current direction.
Figure 13. Commutations for both from ‘0’ to ‘-’ states and reversed. a) for positive load current b) for
negative load current. Adopted from (BRUCKNER 2005).
As a result, switching losses distribution between all semiconductor devices is presented in
Table 3. It can be seen, that regardless up to four devices are utilized in each commutation,
a) b)
31
only two or even one device experience essential switching losses during the commutation
(BRUCKNER 2005).
Table 4. Switching losses distribution between semiconductor devices for one phase in three-level NPC
inverter. - turn-on losses, - turn-off losses, - recovery losses.
Commutation Sx1 Sx2 Sx3 Sx4 Dx1 Dx2 Dx3 Dx4 Dx5 Dx6
Positive load current
From ‘+VDC/2’ to ‘0’
From ‘0’ to ‘-VDC/2’
From ‘-VDC/2’ to ‘0’
From ‘0’ to ‘+VDC/2’
Negative load current
From ‘+VDC/2’ to ‘0’
From ‘0’ to ‘-VDC/2’
From ‘-VDC/2’ to ‘0’
From ‘0’ to ‘+VDC/2’
Along with switching losses conduction losses are also experienced by semiconductor
devices during the inverter performance. The conduction losses distribution both for
positive and negative load current is presented in Table 4 according to NPC inverter
possible states.
Table 5. Conduction losses distribution between semiconductor devices for one phase in three-level
NPC inverter.
State Sx1 Sx2 Sx3 Sx4 Dx1 Dx2 Dx3 Dx4 Dx5 Dx6
Positive load current
‘+VDC/2’
‘0’
‘-VDC/2’
Negative load current
‘+VDC/2’
‘0’
‘-VDC/2’
Device
Device
32
2.2 Commutations and losses in three-level ANPC inverter
The possible states for ANPC inverter have been considered in Chapter 1.2.2. The
commutations between these states and corresponding losses occur during the
commutations are considered in this chapter. In addition, to switching losses, distribution of
conduction losses in ANPC inverter is also presented below.
In contrast to NPC inverter, there are four alternatives for commutation from positive
‘+VDC/2’ state to neutral state in ANPC topology. Firstly, consider commutations to the
upper part of neutral tap. Thus, transient from ‘+VDC/2’ to ’0Up2’ initiated by turning off
Sx1 and then Sx5, while Sx6 has been already in off state. So, the inverter behaves in the
same manner as NPC during this commutation. Both commutations from ‘+VDC/2’ to
’0Up1’ and from ‘+VDC/2’ to ’0Up2’ are identical with only difference that in ’0Up1’ Sx4 is
turned on after Sx5. However, only Sx1 is stressed with positive load current during these
transients and experiences turn-off switching losses (RODRIGUEZ et al 2010).
The backward commutations from neutral tap to ‘+VDC/2’ positive state are implemented in
reversed order. Consequently, Sx5 is turned off first, then Sx1 is turned on, and Sx6 is turned
off finally for ’0Up1’, which yields in recovery losses in Dx5 and turn-on losses in Sx1 for
positive load current. The same commutations from ‘+VDC/2’ to ’0Up1’ and ’0Up2’ states
and reversed result in both switching losses in Sx5 and recovery losses in Dx1 for negative
load current. The all considered cases of commutations and corresponding lossy devices are
shown in Figure 14 (BRUCKNER et al 2005).
Commutations from negative state ‘-VDC/2’ to both ’0Up1’ and ’0Up2’ states of neutral tap
are similar, and losses occur during the transients in symmetrical devices are summarized
in Table 5.
33
Figure 14. Commutations for both from ‘+VDC/2’ to ‘0Up1’ and ’0Up2’ states and reversed. a) for
positive load current b) for negative load current. Adopted from (BRUCKNER et al 2005).
In contrast to previous case commutation, during the transient from positive ‘+VDC/2’ to
zero ’0Low1’ state, the phase current iph commutates to the lower path of the neutral tap, as
it is depicted in Figure 15. During this commutation Sx2 is turned off first, then Sx3 is turned
on, while Sx1 and Sx6 switches stay in turn-on state, and switching losses do not occur there.
Thus, only Sx2 experiences essential turn-off losses for positive current direction. On the
other hand, for negative load current Sx3 and Dx2 are under stress and face to turn-on and
recovery losses, respectively.
The commutation in reversed direction from ’0Low1’ to ‘+VDC/2’ is analogous, but in
backward direction. Since, it is initiated by turning off the inner Sx3 switch, and Sx2 is turned
on after dead time. In this case, for positive load current, Sx2 experiences essential turn-on
losses, while recovery losses occur in Dx3 , due to blocking voltage after commutation. The
commutation with negative load current characterized only with essential turn-off losses in
Sx3 (BRUCKNER et al 2005). The description of these commutations both for negative and
positive load current is shown in Figure 15.
a) b)
34
Figure 15. Commutations for both from ‘+VDC/2’ to ‘0Low1’ state and reversed. a) for positive load
current b) for negative load current. Adopted from (BRUCKNER 2005)
In general, both commutations from ‘+VDC/2’ to neutral states ’0Low1’ and ’0Low2’ result
in lower conduction path for both positive and negative load currents. However, during the
transient to ’0Low2’ neutral tap from positive DC rail Sx1 is turned off first, which yields in
turn-off losses in it, and Sx3 is turned on after that without any stress for positive load
current. On the other hand, turning on Sx3 during the commutation results in switching
losses both in Sx3 and Dx1 for negative load current.
The reversed commutation from zero ’0Low2’ to positive ‘+VDC/2’ state, during which Sx2
is turned on and Sx3 turned off, yields only in turn-on losses in Sx1 and recovery losses in
Dx3.Instanteneously, negative load current stressed Sx3 with significant turn-off switching
losses.
It should be mentioned, that losses distribution for commutations from both neutral states
’0Low1’ and ’0Low2’ to negative ‘-VDC/2’ state can be considered in the same manner.
Switching losses occur during these commutations in symmetrical devices of lower part of
ANPC topology are summarized in Table 5 , too.
b) a)
35
Figure 16. Commutations for both from ‘+VDC/2’ to ‘0Low2’ state and reversed. a) for positive load
current b) for negative load current. Adopted from (BRUCKNER 2005).
According to Bruckner (2005) and Apeldoorn (2005), all the commutations of ANPC
inverter considered below can be divided in 3 types according to their switching losses
distribution and involved in commutation stressed devices.
Thus, first Type 1 comprises commutations, which involve one outer and one NPC device,
for instance commutation between ‘+VDC/2’ and ’0Up1’ or ’0Up2’ states for positive and
negative load currents with positive voltage polarity. During Type 2 commutations, there
are one outer and one inner devices experience switching losses. The example of Type 2
commutation can be switching between ‘+VDC/2’ and ‘0Low2’ states. Finally,
commutations of Type 3 involved in stressed switching two inner semiconductor devices
(BRUCKNER 2005).
The summarized classification of commutations and involved switching devices with
corresponding losses are presented in Table 5. All three types of commutations for positive
voltage and omitted negative one with respect to the both current directions can be found in
it.
a) b)
36
Table 6. Switching losses distribution between semiconductor devices of one phase in three-level ANPC
inverter. - turn-on losses, - turn-off losses, - recovery losses
Commutation type Load
current Sx1 Sx2 Sx3 Sx4 Sx5 Sx6 Dx1 Dx2 Dx3 Dx4 Dx5 Dx6
1 From ‘+VDC/2’
to ‘0Up1’
+
-
1 From ‘0Up1’
to ‘+VDC/2’
+
-
1 From ‘+VDC/2’
to ‘0Up2’
+
-
1 From ‘0Up2’
to ‘+VDC/2’
+
-
3 From ‘+VDC/2’
to ’0Low1’
+
-
3 From ’0Low1’
to ‘+VDC/2’
+
-
2 From ‘+VDC/2’
to ’0Low2’
+
-
2 From ’0Low2’
to ‘+VDC/2’
+
-
3 From ‘0Up1’
to ‘-VDC/2’
+
-
3 From ‘-VDC/2’
to ‘0Up1’
+
-
2 From ‘0Up2’
to ‘-VDC/2’
+
-
2 From ‘-VDC/2’
to ‘0Up2’
+
-
1 From ’0Low1’
to ‘-VDC/2’
+
-
1 From ‘-VDC/2’
to ’0Low1
+
-
1 From ’0Low2’
to ‘-VDC/2’
+
-
1 From ‘-VDC/2’
to ’0Low2
+
-
37
Using Table 5, appropriate commutations can be chosen, in order to distribute losses among
stressed devices by shifting switching losses from on device to another. However, in
practice, in order to achieve even loss distribution conduction losses also should be taken
into account. Thus, conduction losses distribution according to possible states of ANPC
inverter is summarized in Table 6 for both positive and negative load currents.
Table 7. Conduction losses distribution between semiconductor devices of one phase in three-level
ANPC inverter.
State
Sx1 Sx2 Sx3 Sx4 Sx5 Sx6 Dx1 Dx2 Dx3 Dx4 Dx5 Dx6
Positive load current
‘+VDC/2’
‘0Up1’
‘0Up2’
’0Low1’
’0Low2’
‘-VDC/2’
Negative load current
‘+VDC/2’
‘0Up1’
‘0Up2’
’0Low1’
’0Low2’
‘-VDC/2’
From Tables presented below both for NPC and ANPC topology one can see that
regardless the increased number of switching devices, the same number of IGBTs and
diodes experience both conduction and switching losses during the transients or staying in a
certain states. Thus in each state if three-level inverter four devices face to conduction
losses for both current directions, regardless the chosen NPC or ANPC topology.
Furthermore, the same commutation voltage VDC/2 and current iph stress the switches, as the
number of voltage levels remains the same. Therefore, it can be assumed that ANPC
Device
38
topology can be used mostly for even distribution losses among the semiconductor devices
of the inverter, while the total inverter loss dissipation is not notably decreased.
Furthermore, based on the analysis of commutation, it can be clearly seen, that all the
commutations involve the same number of switching devices and make three of them (one
diode and two IGBTs) experience losses. Thus, all the commutations can be either assumed
as equal from total loss dissipation point of view (APELDOORN et al 2005).
2.2.1 Loss balancing in three-level ANPC converter
In practice, to achieve the most quality performance of ANPC converter loss-balancing
module is integrated to the control system of the converter. The modelling of this part of
the converter control is a demanding task, as it comprises different aspects of loss and
thermal behaviour of the converter. However, this system is crucial for reliable
performance of modern high power applications, including multi-megawatt VSWTs. On
the other hand, design of complex control systems including measurement equipment and
sensors also influences initial costs of the application.
In general, loss balance can be obtained only for each phase leg of the converter, as balance
between phases mostly depends on the load and grid properties. Thus, switching losses are
distributed in desirable way according with certain algorithm between switching devices of
topology by applying alternative types of commutations considered above. For instance, the
undesirable switching losses can be shifted from the overheated outer switches to the inner
ones, and then appropriate control vectors can be generated for ANPC to distribute losses
among inner devices as well (APELDOORN et al 2005).
In general, the main objective of the working algorithm of the loss-balancing system is to
optimize the control signal in order to keep the most stressed or hottest device of each
39
phase as cool as possible (BRUCKNER et al 2005), for instance by choosing relevant
switching vector from available alternatives. Such a feedback-controlled balancing system
is shown in Figure 17.
Figure 17. Principle of the active loss-balancing system (BRUCKNER 2005).
As it can be seen from the block diagram, both switching and conduction losses are
calculated on-line from phase currents and DC-link voltages. In addition, junction
temperatures are calculated instantaneously. Then, using a thermal model of the converter
based, for instance on a Foster equivalent network, behaviour of the converter can be
simulated. Based on the obtained values of temperatures, losses and sampled phase currents
the most appropriate commutations paths are selected choosing certain suitable switching
positions, in order not to stress with significant losses the hottest semiconductor. Thus, the
loss balance requirements can be fulfilled (RODRIGUEZ et al 2010).
Thus, to achieve the quality loss balance of the converter several parameters and
characteristics of the system should be known during its performance, including real-time
parameters. Furthermore, aspects of heat network, junction temperatures of devices and, of
course, both switching and conduction losses are integral issues for such a system.
Therefore, the whole system requires efficient and modern embedded system to implement
its performance, on the other hand a certain assumptions can be made during the design in
order to simplify the approach and make it more feasible in practice.
40
In this thesis, control of ANPC inverter has been implemented in the simplest case, with
assumption, that ambient temperature is constant. In addition, heat network as well as
model of thermal behaviour of the converter is out of the scope on this stage of modelling,
however it can be found in literature some approaches for implementation of the whole
system, as well as thermal behaviour issues, for instance in (MUSIKKA 2010) and
(HONSBERG et al 2009).
2.3 Power losses of semiconductor devices
Obviously, not only the fact of loss occasion, but the amount of power dissipation is crucial
in practice during modelling and design of the inverter. Regardless to the topology and type
of the switching device the generic nature of losses are analogous, and basic factors
influence the power dissipation in the same way.
Consider the principle switching characteristics of an ideal active switch shown in Figure
18. In general, the switch is turned on by applying positive control signal, for instance to
the gate of IGBT. Current through the switch start to increase after a delay time td during
rise time tr,i. Then, voltage across the switch falls during tf,v. These two intervals comprise
turn-on time duration
vf,ir,on ttt (3)
Analogously, after the delay time the turn-off transition occur in the reversed order during
turn-off time duration
if,vr,off ttt (4)
41
Figure 18. Principle switching characteristics: a) control signals; b) switching waveforms; c) instantaneous
switch power loss. Adopted from (MOHAN et al 2003).
Thus, switching dissipation energy through the both transitions can be obtained by
estimating the areas under waveforms during the switching occasions
)(2/1 offoncondcomsw ttIVW (5)
Between turn-on and turn-off transitions the switch stay turned on. However, due to a
certain voltage drop occurs even during conducting through the switch, conduction energy
dissipation can be estimated as
condcondcondcond 2/1 tIVW (6)
a)
b)
c)
tr,i tf,v tr,v tf,i
ton
ton toff
Tsw=1/fsw
toff
Woff
Wcond
Won
Vcom Vcom
Vcond
Icond
I, V
W
42
Dividing (5) and (6) by switching time period Tsw average switching and conduction power
loss values per switching period can be obtained
)(2/1)(2/1
offonswcondcom
sw
offoncondcomsw ttfIV
T
ttIVP
(7)
and
cond
condcondcond
2/1
T
IVP
(8)
From the obtained equations one can see, that switching power loss linearly depends on the
switching frequency. In addition, the proportion of the on-state period of the switch also
affects the conduction losses (MOHAN et al 2003).
In general, it can be concluded that, in principle, any switching losses calculation technique
is a geometrical method by nature. It should be kept in mind that linearized methods of
approximation and estimation of losses may be not accurate, as switching transient
waveforms usually have a complex shape, as it is shown in Figure 19. However, in practice
the accuracy of such methods is appropriate enough even with certain assumptions.
Thus, the aim of any calculation approach is to find as accurate approximation of
commutation current and voltage waveforms as possible. On the other hand it should be not
very complicated, as feasibility of the method is also important. There are certain methods
and approximation approaches can be found in literature, for instance in (RAJAPAKSE et
al 2005) and (FEIX et al 2009). The results obtained with geometrical representation of
current and voltage turn-on and turn-off waveforms are accurate enough, however, in
addition to detailed data-sheet data, some measurements should be also available.
43
Figure 19. Real IGBT waveforms: a) turn-on b) turn-off. Adopted from (RAJAPAKSE et al 2005).
From the above discussion it can be summarized that power losses Ploss of any
semiconductor component comprise three following types: switching losses Psw,
conduction losses Pcond and blocking or leakage losses Pb (MOHAN et al 2003;
GRAOVAC et al 2009). However, normally blocking losses assumed to be neglected, thus
Ploss = Psw + Pcond + Pb ≈ Psw + Pcond. (9)
a)
b)
44
2.3.1 IGBT and diode switching losses
Obviously, switching losses share a significant portion of the total amount of power losses
in a switching device. Since, accurate enough calculation of switching losses is an
important part of the loss-balancing system discussed previously. As it has been already
considered, due to derivative waveforms of commutation currents and voltages, linearized
loss model for calculation switching losses should be designed (RAJAPAKSE et al. 2005).
One of examples of such implementation can be found in (BIERHOFF et al 2004).
Recently, the equations for calculation switching losses occur in the components of two-
level application have been presented in (AARNIOVUORI et al 2012). However, the same
approach can be used for three-level inverter as well, since switching losses are calculated
for each independent device, regardless the topology and control method. Thus, the average
switching losses of an IGBT for the fundamental period fT in the three-level inverter can
be obtained as follows
swIGBT sw,
ratedrated
comcomIGBT sw, NE
UI
UIP (10)
Where swN is a number of switch changes during the fundamental period fT depending on
the fundamental frequency f =50 Hz
fT 1
f . (11)
However, it should be mentioned that any period under observation can be chosen.
Switching loss energy of the IGBT IGBT sw,E for the fixed datasheet parameters, including
reference commutation voltage and current, comprises turn-on and turn-off energies per
pulse, which are constant and can be taken from the datasheet
offonIGBT sw, EEE . (12)
45
The actual commutation voltage comU corresponds to the DC-link voltage and depends on
the number of levels of the converter. Thus, for three-level inverter commutation voltage
comU is equal to the half of DC-link voltage
2DC
com
UU . (13)
In general, during the design the turn-on losses of modern fast recovery free-wheeling
diodes are not taken into account, due to its less than 1% share of the total switching losses
in the diode. However, the reverse recovery process during the transients produce
significant amount of losses, also referred as recovery losses of free-wheeling diode, which
obviously affect the amount of switching losses, as well as total losses in general
(RAJAPAKSE et al. 2005).
Analogously with IGBT switching losses, recovery losses for the free-wheeling diode can
be calculated
swrec
ratedrated
DCcom
rec2 NE
UI
UI
P (14)
where recE is reverse recovery energy taken from data-sheet for ϑ=125°C
2.3.2 IGBT and diode conduction losses
Obviously, along with switching losses conduction losses are also experienced by
semiconductor devices during the inverter performance. During the implementation of the
loss calculation model for the inverter the technique for conduction losses calculation in
IGBTs and diodes proposed in (GRAOVAC et al 2009) is utilized. Thus, conduction losses
46
in IGBT or diode are calculated using common approximation of the semiconductor as a
series connected DC voltage source and a resistor. So, the voltage source represents IGBT
on-state zero-current collector-emitter voltage UCE0, while the resistor is a collector-emitter
on-state resistance of the IGBT RC
CCCE0CCE )( IRUIU . (15)
The parameters needed in calculation are taken from the data-sheet available in Appendix
1. It should be mentioned that the parameters of on-state resistance RC and threshold
voltage UCE0 are not given directly there, however sometimes these values can be given by
manufacturers in datasheets. Since, the determination technique of the threshold voltage of
the IGBT UCE0 and RC is represented in Figure 20. It can be also done by using any
software, for instance MatLab, thus more accurate margin can be obtained. It should be
kept in mind that obtained parameters correspond to the toughest conditions. In other
words, it is assumed that inverter performs at high ambient temperature or without cooling,
thus junction temperature of the device is ϑ=125°C, as it can be seen from the data-sheet.
Figure 20. Reading the UCE0 and RC using IGBT output characteristics from the data-sheet Appendix 1.
47
Then, IGBT collector-emitter on-state resistance RC can be calculated as follows
C
CEC
dI
dUR . (16)
The instantaneous value of IGBT conduction losses is
)()()()()( 2
CCCCE0CCEIGBT cond, tIRtIUtItUtP , (17)
from which the average losses can be obtained by
2
RMSC,CavC,CE0
0
2
CCCCE0
cond0
IGBT cond,
cond
IGBT cond,
condscond
))()((1
)(1
IRIUdttIRtIUT
dttPT
P
TT
(18)
Where avC,I and RMSC,I are the average and root-mean-square value (RMS) IGBT currents
for the conduction period, respectively:
avC,I cond
0
C
cond
)(1
T
dttIT
, (19)
cond
0
2
C
cond
RMSC, )(1
T
dttIT
I . (20)
Analogously, the approximation discussed in the beginning of the chapter gives for the
anti-parallel diode the following
DDD0DD )( IRUIU . (21)
The diode parameters UD0 and RD are determined in the same way using typical transfer
characteristic taken from the data-sheet, as it is represented in Figure 21.
48
Figure 21. Reading the UD0 and RD using IGBT transfer characteristics from the data-sheet Appendix 1.
In the same manner, the on-state resistance of the free-wheeling diode is obtained as
follows
D
DD
dI
dUR . (22)
The instantaneous value of the diode conduction losses is
)()()()()( 2
DDDD0DDD cond, tIRtIUtItUtP , (23)
from which the average losses of the diode for the conduction period can be obtained by
2
RMSD,DavD,D0
0
2
DDDD0
cond0
D cond,
cond
D cond,
condcond
))()((1
)(1
IRIUdttIRtIUT
dttPT
P
TT
(24)
49
3 DYNAMIC SIMULATION AND MODULATION PRINCIPLES OF NPC AND
ANPC INVERTERS
Along with the converter topologies discussed in the previous chapter, chosen control
technique of a converter also impact on the efficiency and quality of the output voltages
and currents. There are some control strategies available to produce the desired output
signals, however pulse width modulation (PWM) is one of the most common used control
methods for power electronics converters (PEC) with alternating current output, due to its
maturity and known feasibility of implementation in embedded systems and
microcontrollers.
3.1 Modulation strategies for multilevel converters
From wind energy conversion system (WECS) point of view, the major objective of any
PWM method is to produce stable output voltage and current waveforms. However, another
essential aim of PWM schemes is to reduce the impact on the quality of the output signals,
for instance total harmonic distortion (THD), so they should comply with requirements of
the international standards.
In general, all the plenty of PWM methods despite of their different modifications are
usually categorized into three main groups. They are carrier-based PWM, selective
harmonic elimination (SHE) and space vector modulation (SVM) (KIM et al 2010). These
three PWM techniques are considered in the following discussion.
The most conventional PWM strategy is carrier-based PWM, due to relatively simple
implementation even using analog devices in the past. Nowadays digital implementation of
50
this technique is also used, however the basic principle is the same for both
implementations, which is based on the comparison of the fundamental frequency
sinusoidal reference voltage with high frequency carrier signal. The switching states are
produced every time as reference signal intersects carrier signal. The basic control diagram
for three-phase pulse width modulator is presented in Figure 22. It should be mentioned,
that the frequency of the carrier signal corresponds to switching frequency of the inverter,
while reference signal frequency is equal to desired output voltage frequency.
Figure 22. Basic control diagram of three-phase carrier-based PWM.
In order to control multi-level (ML) inverters by based-carrier PWM some modifications of
this method can be employed. Thus, a modulation signal of level-shifted multilevel PWM is
represented in Figure 23. As it can be seen, the number of carrier signals for this multi-level
pulse width modulator is defined as (N-1), where N is the number of levels of the voltage
source inverter (VSI). Thus, for three-level NPC VSI N=2.
51
Figure 23. Modulation signal for three-level application (RODRIGUEZ et al 2009).
The basic principle of SHE PWM strategy for three-level applications is based on the
control of the fundamental frequency by Fourier analysis of the inverter voltage, while the
most significant undesirable 5th
and 7th
harmonics are eliminated by using a certain
switching angles. This method from the control of three-level inverters point of view is a
suitable alternative, due to the fact that inverter can be operated at a relatively low
switching frequency. Since, the switching losses of semiconductor devices can be reduced
significantly. Thus, recently efficient SHE PWM technique has been presented for
multilevel converters, in particular for 3-level ANPC converter (PULIKANTI et al 2011).
Figure 24. SHE PWM modulation signal for 3-level ANPC application (PULIKANTI et al 2011).
52
SHE approach is used quite widely in system level in distributed power generation systems,
for instance in large wind parks, in order to reduce the interconnection of harmonics and
eliminate the 11th
harmonic. There are obvious advantages of SHE PWM strategy usually
mentioned, such as high quality harmonic content of output voltage and reduction of
switching losses thanks to its harmonic elimination nature and low switching frequency
respectively. However, a certain drawbacks also exist, for instance relatively narrow
modulation range and complex implementation (BIERK et al 2009; PONTT et al 2003;
KIM et al 2010).
Another alternative to control three-level inverter is SVM method based on the space vector
theory with coordinate transformations. This method is the most widely utilized strategy for
three-phase NPC and ANPC three-level inverters. This fact can be explained with its
certain advantages, such as relatively simple digital implementation and quite wide linear
modulation range, as well as achievable low harmonic content of output signals and high
voltage capability (KIM et al 2010). Thus, this method has been implemented in this thesis
both for NPC and ANPC inverter topologies. So, more detailed discussion about SVM
technique to control NPC inverter is presented in the following chapter.
3.2 Space Vector Modulation of NPC inverter
As it is mentioned previously, in this thesis the mature and efficient SVM strategy is
offered to control three-phase NPC inverter in order to obtain desirable sinusoidal output
voltage. The output voltage waveform of each phase comprises three levels: 2/DCU , 0
and 2/DCU . In total, three-phase output sinusoidal voltages are generated by 33=27
switching combinations of the inverter, according to (2). The switching states of the
inverter have been already discussed in Chapter 1.2.1 and summarized in Table 1.
53
The space vector diagram for the three-level inverter is presented in Figure 25. As the space
vector diagram of two-level inverter it is also regular hexagon consisting of six A, B, C, D,
E and F 60-degrees sectors. However, in contrast to two-level application each sector is
divided into four regions, which are equilateral triangles 1, 2, 3 and 4. As it also can be
seen from Figure 25 all the apices of the triangle regions correspond to 27 inverter
switching states: 24 active and 3 zero ones lying at the centre of the hexagon.
Figure 25. General representation of space-vector diagram of three-level inverter. Adopted from
(YAMANAKA et al 2002).
All the 27 switching states determine 27 base vectors, thus using these vectors output
voltage vector of the inverter Vref is formed. Each region as well as each sector contains
combination of relevant base vectors (switching states) utilized to obtain desired output
voltage vector. In addition, a certain sequence of switching positions which should be
54
utilized for each region is also defined beforehand. So, a required sector is selected
according to the phase of the output vector, whereas region is identified with the amplitude
of the output vector.
The SV PWM strategy is based on the principle that the output voltage vector Vref can be
accurately enough calculated by using three adjacent vectors, also referred as the nearest
triangle vectors (NTVs) (KOCALMIS et al 2006; YAMANAKA et al 2002),
sref332211 TTTT VVVV (25)
where 1V , 2V and 3V are vectors defined by a triangle region where output voltage vector
Vref is located. The durations 1T , 2T and 3T for corresponding base voltage vectors
comprise the sampling time sT
s321 TTTT . (26)
Thus, the control SV PWM strategy for three-level NPC inverter has been implemented
with the algorithm based on two papers (KOCALMIS et al 2006) and (YAMANAKA et al
2002). The point of the designed algorithm includes four steps, as follows
1. Determination of the sector, in which desired output voltage vector Vref is located,
with according to phase of the vector.
2. Determination of the region, in which desired output voltage vector Vref is located,
with according to amplitude of the vector.
3. Definition of combination of switching positions (base vectors) utilized in forming
of Vref and sequence of its switching on in the combination.
4. Calculation of turning on durations for base vectors included in the combination.
The description of used methods and calculation approaches of each step are considered in
the following chapters.
55
3.2.1. Determination of sector and region of SV
The first design step is determining the sector. Its determination is similar to two-level
applications, as phase angle α of the voltage vector is calculated and known, the sector,
where the reference output vector Vref is located, is determined based on the following
inequalities (KOCALMIS et al 2006)
If 0° ≤ α < 60°, then Vref is in sector A (27)
If 60° ≤ α < 120°, then Vref is in sector B (28)
If 120° ≤ α < 180°, then Vref is in sector C (29)
If 180° ≤ α < 240°, then Vref is in sector D (30)
If 240° ≤ α < 300°, then Vref is in sector E (31)
If 300° ≤ α < 360°, then Vref is in sector F (32)
Sector A for three-level inverter and its switching states are presented in Figure 26. It can
be seen, that every switching state of the inverter is described with combination of three
symbols corresponding to three phases of the inverter. Each symbol means connection of
corresponding phase to positive +UDC/2, negative -UDC/2 voltage and neutral point, ‘P’, ‘N’
and ‘0’, respectively. For instance, combination of N0P means that IGBT switches S11 and
S12, S22 and S23, S33 and S34 of the three-level NPC inverter topology in Figure 8 are turned
on.
56
Figure 26. a) Sector A and its switching states; b) Space vector geometrical determination. Adopted
from (KOCALMIS et al 2006).
Determining the region in the sector is provided with projection of the vector Vref on the
borders of the sector, as it depicted in Figure 26. Thus, from Figure 26 (b) both m1 and m2
components can be calculated as follows (KOCALMIS et al 2006)
3
sin2
3
2
)3
sin(
n2
mbbam (33)
)3
sin(cos)
3cos()
3
sin2(cos n
nn1
mm
mm (34)
where modulation index mn corresponds to the length of the reference voltage vector Vref. In
general, the length of the maximum base voltage vector maxbase,V , for instance vectors a, b
m1
P0N
PNN P00
0NN
PPP
000
NNN
PP0
00N
A1
A3
A2
A4
PPN
m2
a)
b)
α
mn
m1
m2
mn
a
c
b
57
and c from Figure 25, is equal to 2/3UDC. Thus, the maximum length for the amplitude of
the sinusoidal voltage is obtained as (PYRHÖNEN 2010)
maxbase,DCmaxbase,maxref,maxn, 866.0)3/1(2/3 VVV Um (35)
Thus, modulation index is
0 < mn ≤ 0.866. (36)
Therefore, the following inequalities are used to determine the region.
If m1 ≤ 0.5, m2 ≤ 0.5 and m1 + m2 ≤ 0.5, then Vref is located in Region 1 (37)
If m1 > 0.5, then Vref is located in Region 2 (38)
If m1 ≤ 0.5, m2 ≤ 0.5 and m1 + m2 > 0.5, then Vref is located in Region 3 (39)
If m2 > 0.5, then Vref is located in Region 4 (40)
3.2.2 Determination of switching states and their sequences
In general, transitions between switching states inside the regions are provided according to
the criterion of minimum switching changes. Since, for the constant modulation index only
one phase of the inverter changes its switching state, while other two phases remain in the
same state during a commutation, as it can be seen from space vector diagram in Figure 25.
In addition, for the following discussed sequences changing a state of any phase provided
by switch changes of two active switching devices of the inverter model.
Thanks to the symmetry of upper and lower parts of NPC inverter topology, vector of
control signals only for upper part is formed directly, whereas control vector for the lower
58
part is generated just by inversing the binary code containing in the vector control. Thus,
the switching change of only one IGBT at any transition is considered, while corresponding
second IGBT is switched automatically due to control implementation approach.
The directions of switching sequences in the regions for all sectors are shown in Figure 27.
For instance, the switching orders for four regions and corresponding phases states of
sector A are as follows, according to Figures 25 and 27 (YAMANAKA et al 2002):
For region A1, as the switching direction is clockwise: PPP, PP0, P00, 000, 00N, 0NN,
NNN.
For region A2, as the switching direction is clockwise: P00, P0N, PNN, 0NN.
For region A3, as the switching direction is counter clockwise: PP0, P00, P0N, 00N.
For region A4, as the switching direction is clockwise: PP0, PPN, P0N, 00N.
Figure 27. Vector diagram for three-level inverter with directions of switching sequences.
Sector B
Sector C Sector A
Sector D Sector F
Sector E
59
Then, consider two conventional alternatives for forming sequences of switching states of
the inverter. Both symmetrical and asymmetrical orders for region A2 are shown in Figure
28.
Figure 28. The asymmetrical (a) and symmetrical (b) switching sequences for sampling period Ts. Adopted
from (YAMANAKA et al 2002).
As it can be seen from Figure 28, the symmetrical approach requires twice more switching
transitions per one sampling period Ts, than asymmetrical one does. However, for both
sequences the following expression is true
sTttt 321 (41)
P P P 0 0 P P P
0 0 N N N N 0 0
0 N N N N N N 0
A2 V
U
W
A2 V
U
W
Ts Ts
Ts
t1/2 t2 t3 t1/2
t1/4 t2/2 t3/2 t1/4 t1/4 t2/2 t3/2 t1/4
a)
P P P 0 0 P P P
0 0 N N N N 0 0
0 N N N N N N 0
b)
60
where t1, t2 and t3 are duration times of applying corresponding NTVs. The calculations of
these durations for each region are discussed in the following chapter. In addition, for three-
level inverter, as well as for two-level one, the sampling time can be calculated as
kfTs
6
1 (42)
where k is a total number of base vectors formed in one sector, and f is the fundamental
frequency. In this thesis, as inverter is a grid side application of the frequency converter, f =
50 Hz is the grid frequency.
In general, the appropriate switching sequence approach is chosen based on certain
compromise between better quality of output signals on one hand and reduced switching
losses of the IGBTs and more simple implementation on the other one. Thus, symmetrical
approach provides better harmonic content of output voltages and currents, due to twice
more switching transitions, however the control of the inverter becomes either more
awkward, especially during modelling, as it is described in Chapter 4.1. In addition,
complex and sophisticated analysis of the quality of output signals is out of the scope in
this thesis. However, general harmonic content analysis of output signals have been
provided during the simulations and THD has been evaluated as well. The obtained results
are also presented in Chapter 4.
Thus, the asymmetrical switching sequences have been chosen and utilized in the
simulation model, due to its more feasible implementation and reduced switching loss
dissipation. The pulse patterns and switching states for three phases in four regions of
sector 1 are presented in the diagram shown in Figure 29.
61
Figure 29. The asymmetrical switching sequences for one sampling period Ts in regions A1-A4.
Adopted from (YAMANAKA et al 2002).
t1/4 t3/2 t2/2 t1/2 t3/2 t2/2 t1/4
t1/2 t2 t3 t1/2
t2/2 t1/2 t3 t2/2 t1/2
A2 V
U
W
A3 V
U
W
A1 V
U
W
W
A4 V
U
W
0 N N N N N N 0
P P P 0 0 P P P
0 0 N N N N 0 0
P P P 0 0 0 N N 0 0 0 P P P
P P 0 0 0 N N N N 0 0 0 P P
P 0 0 0 N N N N N N 0 0 0 P
P P P 0 0 0 0 P P P
P 0 0 0 N N 0 0 0 P
P P P 0 0 0 0 P P P
P P P 0 0 P P P
P P 0 0 0 0 P P
0 N N N N N N 0 t1/2 t3 t2 t1/2
62
Therefore, as it can be seen from the diagram below, during sampling period Ts there are 7
and 5 switching changes in the first and third regions respectively. Both second and fourth
regions are characterized with 4 switching transients per region. The time periods during
which the corresponding to each region NTVs utilized are also shown under each region
pattern in Figure 29. These durations t1, t2 and t3 of applied NTVs for all the regions are
calculated in the following chapter.
3.2.3 Calculating the switching times and durations
As it has been already considered, the asymmetric switching sequences have been
implemented in the simulation model. However, for changing the switching combination
from asymmetric to symmetric one, all the time durations should be just divided by two. In
addition, the calculations of the time durations t1, t2 and t3 are independent from the sector,
in which the desired output voltage vector Vref is located. Thus, regardless to the number of
sector the phase angle α of Vref is chosen for calculations from the range
0° ≤ α ≤ 60°. (43)
In general, durations t1, t2 and t3 can be defined as weighting coefficients calculated from
geometrical representations of applied NTVs. The time lengths for the utilized in the
simulations NTVs are calculated according to formulas taken from (YAMANAKA et al
2002).
Thus, for first regions durations are calculated
))3/sin(21(1 ns mTt (44)
)3/sin(22 snTmt (45)
63
sin23 snTmt (46)
In second regions base vectors are applied with the following durations
))3/sin(1(21 ns mTt (47)
sin22 snTmt (48)
)1)3/sin(2(3 ns mTt (49)
Base vectors of the third regions for all sectors are characterized with
)sin21(1 ns mTt (50)
))3/sin(21(2 ns mTt (51)
)1)3/sin(2(3 ns mTt (52)
Finally, durations of applying base vectors in the fourth regions are
))3/sin(1(21 ns mTt (53)
)3/sin(22 snTmt (54)
)1sin2(3 ns mTt (55)
For all time durations the expression for sampling time Ts (40) is fair. However, for these
calculations modulation index nm is always taken equal to unity during the simulations.
Thus, NTV duty-cycle calculations for all regions can be summarized in Table 7
(YAMANAKA et al 2002).
64
Table 8. Time durations of adjacent NTVs utilized in SVM control model.
Region Applied NTVs Time length of NTV applying
A1, B1,
C1, D1,
E1, F1
op, oo, on ))3/sin(21(1 ns mTt
ap, an )3/sin(22 snTmt
bp, bn sin23 snTmt
A2, B2,
C2, D2,
E2, F2
ap, an ))3/sin(1(21 ns mTt
c sin22 snTmt
a )1)3/sin(2(3 ns mTt
A3, B3,
C3, D3,
E3, F3
ap, an )sin21(1 ns mTt
bp, bn ))3/sin(21(2 ns mTt
c )1)3/sin(2(3 ns mTt
A4, B4,
C4, D4,
E4, F4
bp, bn ))3/sin(1(21 ns mTt
c )3/sin(22 snTmt
b )1sin2(3 ns mTt
The NTVs and regions are referred according to the vector diagram and pulse patterns
diagram shown in Figure 25 and Figure 29, respectively. For instance, it can be seen that
total time length for base vectors op, oo and on is 1t . However, the total length 1t for these
vectors is divided in the following proportions for the first regions: t1/4 for op-vector, t1/2
for oo-vector and t1/4 for on-vector. Analogously, 2t and 3t are divided between ap, an and
bp, bn base vectors with certain proportions, thus the whole switching period Ts comprised
from 7 durations for A1, B1, C1, D1, E1 and F1 regions. The duty-cycles for all remain
regions are divided in the same manner according to the patterns in Figure 29.
65
4 SIMULATION METHODS AND RESULTS
In this chapter, modelling and simulation of both NPC and ANPC three-level inverters have
been performed with RL-load using MatLab/Simulink package program. In addition, based
on the discussion in Chapter 2 losses calculation model is performed, too.
4.1 Modelling of three-level inverter controlled with SVM
The simulation model of three-level NPC inverter has been built in MatLab/Simulink
package program. The general models of the inverters with control block and loss
calculation module is presented in Appendix 2. The control algorithm of SVM technique
has been implemented with asymmetric sequences of inverter states and forming six base
vectors of output voltage in each sector. The frequency of output voltage is assumed to be
constant (50 Hz).
In convenience, the control model can be divided in 4 functional blocks shown in Appendix
3. The first one is ‘Definition_of_sector_and_angle’, where the frequency and amplitude of
output voltage is defined. The second block ‘Definition_of_Region’ is used to specify the
region location of the reference output voltage vector Vref. The block
‘Conducting_Time_Calculator’ is based on equations (43) - (54), where time durations of
applying base vectors are calculated for each region. Finally, ‘Switching_Control’ is the
block of logic elements and multiple switches perform connection, shift and switching of
base switching states of the inverter. Obviously, the last block differs in certain extent for
NPC and ANPC models, however its basic principle is the same for both models.
66
4.1.1 SVM control of NPC inverter model
The input signals for SVM control block are the modulation index m and frequency f of
output signal. The block ‘Definition_of_sector_and_angle’ is shown in Appendix 4. The
sequence of sector number is defined with digital counter, and the period of changing the
sector number is
6secsT
T (56)
In addition, the amount of forming base vectors in the sector is also defined here with
sequence of the phase angle α, in particular the sequence discretely varies from 0° to 50°
with 10° step. The discrete change of α is initiated by every pulse of digital pulse generator.
The period of discretization is defined as
6s
d
TT (57)
Thus, control signals for six base vectors are formed for each sector. The outputs of the
‘Definition_of_sector_and_angle’ block are phase angle in range from 0° to 50° and
number of sector from 1 to 6.
Figure 30. The variation of phase angle α during fundamental period.
67
The variation of phase angle α is shown in Figure 30. It can be also seen that during one
fundamental period Tf=0.02 the angle is counted six times up to 50 degrees, which
corresponds to 6 sectors. The counter of the sector number is reset every fundamental
period, thus output of the counter is control signal containing the number for enabling one
of six sectors.
The content of ‘Definition_of_Region’ block is presented in Appendix 5. Here, the
calculation is performed according with (36) - (39). As a result, the region, where the
output voltage vector is located, is defined. The inputs of the block are varying phase angle
α and modulation index m. The synchronization of calculations is performed with standard
Triggered Subsystem.
The outputs of the block are four digital control signals, which define the location of output
voltage vector. Thus, at any time the base vectors for only one region should be applied,
since the only one output signal contains positive control voltage, whereas the three others
are zero. For instance, the signals for regions are shown in Figure 31. As it can be seen for
modulation index m=1, the output vector is located in 2 and 4 regions.
Figure 30. The signals defining regions 1, 2, 3 and 4 for m=1.
68
The calculation block for time durations t1, t2 and t3 of applied base vectors can be found in
Appendix 6. The calculations in ‘Conducting_Time_Calculator’ block are based on (43) -
(54) for each region. There are three inputs for this block, they are sampling time Ts,
modulation index m=1 and varying phase angle α. The output signals are durations of
applying vectors for four regions, which are identical for all sectors, so there are twelve
output signals, according to Table 7.
Then, the signals of time durations t1, t2 and t3 from ‘Conducting_Time_Calculator’ block
are one of the inputs for ‘Switching_Control’ compound module consisting of several
blocks, as it shown in Appendix 7. In general, the block contains four control channels for
four regions and the twelve time duration inputs, thus three t1, t2 and t3 time durations are
connected to each region block. In addition, the signals defining the region and sector are
the other two inputs.
The forming of asymmetric sequences of pulses with desirable durations as it depicted in
Figure 29 is provided in internal blocks ‘Switching_Sequence’. The principle of performing
for each block is similar, but the only difference is the number of switching changes and
lengths of forming pulses for each region. Therefore, the following method of
implementation is considered only for one region, for instance for region 2.
For region 2 the asymmetric sequence of switching states is formed in
‘Switching_Sequence2’ internal block, and it can be written as 22
132
1 ttt
t .
Thus, the inputs for this block are the signal defining the region 2, the signals of time
durations t1/2, t2 and t3 calculated for vectors formed in region 2 and synchronizing pulses
utilized to initiate the forming of sequences. The signals defining the length of pulses are
compared with reference signal from digital counter and using the logic elements desired
sequence 22
132
1 ttt
t is obtained, as it shown in Figure 31.
69
Figure 31. The sequence of pulses region. theof signal control and2
1t
3t2t2
1t
Analogously, the following sequences4222224
1231321 ttttttt ,
and 2222
123
12 ttt
tt blocksin formed are
221
231 t
ttt
for
regions 1, 3 and 4, respectively.
Then, formed sequences of pulses are distributed between inputs of IGBTs of the inverter
simulation model according with the vector diagram shown in Figure 25 above. In addition,
the distribution of base states of the inverter is also provided here with respect to the sector,
which is defined with the signal coming from ‘Definition_of_sector_and_angle’ block. In
the model, multiple switches are utilized in order to obtain appropriate inverter states.
There are four multiple switches with six alternative base vectors formed in region 2 for all
six sectors in the block corresponding to region 2. Obviously, the number of the switches is
equal to the number of time pulses, thus for region 2 sequence 22
132
1 ttt
t
70
there are four multiple switches with six stored base vectors corresponding to every time
length of the sequence. Thus, there are seven, five and four multiple switches for 1, 3 and 4
regions, containing six base vectors for every sector of the diagram.
The variation of the signal from 1 to 6 defines the number of the sector, thus reading of
appropriate base vector from the switch is initiated. Each base vector of the switch contains
6-bit binary code defining a desirable combination of turned on 6 IGBTs of upper half of
the NPC inverter. As it has been mentioned previously, the upper half IGBTs Sx1 and Sx2
perform in antiphase with lower half ones Sx3 and Sx4 respectively of the NPC inverter.
Since, control signals contains six-digit vectors for upper part of three-phase inverter,
whereas control signals for the lower part are obtained just with block of logical inversion.
In addition, the block ‘Switching_Control’ contains compound logical subsystems, which
provide applying the combination of desired switching positions for the period of time,
corresponding, for instance to t1/2, t2 and t3 time durations in region 2. Then, control pulses
corresponding to a certain switch are summed up with operator of logical addition OR with
four inputs, corresponding to four switching states in region 2 for four time durations,
discussed above. Further, the control pulses are serially multiplied with the signal of
corresponding region in blocks of logical conjunctions. Finally, obtained control pulses for
every one IGBT analogously summed up with OR-operators, thus control signal with
desired duration for every switch is obtained for a certain moment of time.
The only difference in control models of SVM for NPC and ANPC inverter is the
implementation of forming the base switching states of the inverter. Thus,
‘Switching_Control’ block is more complicated for ANPC application, due to the fact that
control vector for the ANPC inverter is not symmetric, as upper and lower parts in the
ANPC inverter do not perform in opposite phase, and specific switching combinations
should be applied, as it was presented in Table 2. Thus, in general asymmetric control
vector for ANPC inverter contains 18-bit code for all switches instantaneously for three
phase legs of the inverter.
71
The power electronics part of the simulation model with measurement model to assess
losses has been built from IGBTs, wheel-forward diodes and measurement elements of
SimPower library of Simulink. The both NPC and ANPC inverter models are presented in
Appendix 8.
4.2 Simulation results for NPC and ANPC inverters
The first step of modelling is the simulation of NPC and ANPC inverters for RL-load.
During the simulations DC-link voltage and output frequency are assumed to be constant
and modulation index m=1. Thus, basically regions 2 and 4 are utilized during the
simulations, however for NPC inverter the model is capable to perform in all the four
regions and full modulation index range, except overmodulation mode, when m>1. The
IGBTs and diodes parameters for the inverter are taken from the data-sheet Appendix 1 and
obtained from Figures 20 and 21.
Table 9. Inverters and loss calculation model simulation parameters.
Parameter Explanation Value
UDC DC-link voltage [kV] 2.8
Rload Load resistance [Ω] 1
Lload Load inductance [mH] 2
ttol The minimum pulse length [µs] 50
tr Rise time [µs] 0.2
tf Fall time [µs] 0.2
fsw Switching frequency [kHz] 1.8
UCE0 Threshold voltage of IGBT [V] 1.9
RC IGBT collector-emitter on-state resistance [mΩ] 2
UD0 Threshold voltage of free-wheeling diode [V] 1.4
RD On-state resistance of free-wheeling diode [mΩ] 2.3
Eon Turn-on energy loss per pulse [mWs] 2200
Eoff Turn-off energy loss per pulse [mWs] 1550
Erec Free-wheeling diode reverse recovery energy [mWs] 1550
72
In general, the given values correspond to the toughest conditions, when junction
temperature of devices is ϑ=125°C. Simulation results shown in Figure 32 and Figure 33
are obtained for output frequency f=50Hz and modulation index m=1. Obviously, obtained
results are generally identical for NPC and ANPC inverters, as the same modulation
strategy with the equal parameters is utilized during the simulations. Thus, Figure 32
illustrates output line-to-line voltage waveform with five levels.
Figure 32. The line-to-line output voltage waveform for f=50Hz and m=1.
73
Figure 33. Three-phase output current waveforms and its spectrum for f=50Hz and m=0.866.
74
Table 10. Comparison of obtained values of harmonic currents and permitted values from IEC 61000-
4-7 standard.
Harmonic
order
Permitted value of related harmonic
currents according to IEC 61000-4-7
for 10kV networks
Obtained values of harmonic
currents for ANPC inverter model
5 0.058 0.0255
7 0.082 0.0157
11 0.052 0.0078
13 0.038 0.003
17 0.022 0.0035
19 0.018 0.0046
23 0.012 0.0048
25 0.010 0.0106
In general, considering obtained waveforms of voltages and currents the quality of
performance of the inverter model can be assessed.
For instance, the output current harmonic content obtained with Simulink FFT-analysis is
presented in Figure 33 and Table 9. From its spectra it can be clearly seen the fundamental
50 Hz first harmonic, and THD is equal to 3.49% for ANPC inverter. During the
simulations, the tolerance parameter for minimum pulse length has been varied in narrow
ranges, however the THD value for both NPC and ANPC models do not exceed 3.5% for
these simulations.
The quality of output signals can be increased with implementation of symmetrical
switching sequences instead of asymmetrical ones, which are discussed in Chapter 3.2.2.
Thus, the number of switching transitions can be twice increased in order to reduce current
ripple. On the other hand, it can lead to significant increase of the switching losses and
overheating the components of the inverter. Therefore, as an option a simple LCL-filter can
be designed for the grid side to improve harmonic content of output signals.
75
4.2.1 Comparison of losses calculation results and efficiency
Then, losses calculation results are considered. The results were obtained according to the
description of the methodology from Chapter 2.3.1 and 2.3.2. It should be noted that the
following assumptions were adopted to calculate power losses of the devices during the
simulations. Firstly, the load current is assumed to be sinusoidal and current and voltage
ripples are also neglected. Secondly, the dead times of switching devices are not taken into
account during the calculation (FLORICAU et al 2009). In addition, DC-link voltage is
kept constant and auxiliary losses corresponding to stray inductances in the inverter are also
neglected, and almost unity power factor (PF) is also assumed. Moreover, due to specific
modulator model m=0.866 is kept during the simulations. Thus, the total power dissipation
of the inverter is calculated as the sum of total conduction and switching losses.
The following Tables 11 and 12 show the distribution of conduction and switching losses
between devices for a phase for the toughest conditions.
Table 11. Losses distribution between devices in NPC inverter model.
Device Sx1 Dx1 Sx2 Dx2 Sx3 Dx3 Sx4 Dx4 Dx5 Dx6
Conduction
losses [W] 1290 19 1538 19 1538 19 1290 19 279 279
Switching
losses [W] 365 10 6 10 6 12 355 12 138 142
Total
losses [W] 1655 29 1544 29 1544 31 1645 31 417 421
Conditions: Eupec 3.3kV IGBTs Appendix 1 for ϑ=125°C, UDC=2.8kV, Iph=1.2kA,
fsw=1.8kHz, m=0.866, PF≈1
76
Table 12. Losses distribution between devices in ANPC inverter model.
Device Sx1 Dx1 Sx2 Dx2 Sx3 Dx3 Sx4 Dx4 Sx5 Dx5 Sx6 Dx6
Conduction
losses [W] 1308 15 1343 93 1342 93 1308 15 174 207 173 207
Switching
losses [W] 140 13 112 87 111 88 140 14 105 65 104 63
Total
losses [W] 1448 28 1455 180 1453 181 1448 29 279 272 277 270
Conditions: Eupec 3.3kV IGBTs Appendix 1 for ϑ=125°C, UDC=2.8kV, Iph=1.2kA,
fsw=1.8kHz, m=0.866, PF≈1.
In general, as it is known, due to the symmetrical structures of NPC and ANPC topologies,
the loss behaviour of the upper and lower half components is similar for the both inverters.
Therefore, the symmetrical switches Sx1 and Sx4 are stressed equally, as well as Sx2 and Sx3.
In addition, simultaneously conducting Dx1 and Dx2 as well as Dx3 and Dx4 for NPC inverter
are also stressed equally. Actually, for PF is close to unity, there should be no losses for
FWDs, however small inductance in the load cause conducting losses there as well. The
current waveforms for the corresponding semiconductors can be found in Appendix 10.
The approach of losses distribution between outer and inner devices using the similar SVM
technique has been implemented for ANPC inverter. As it can be seen, the symmetrical
behaviour of ANPC topology also yields in equal losses for outer and inner
semiconductors.
As it can be seen from the both tables above the total losses distributed more evenly
between switching devices, due to increased number of active switches up to 18 and created
alternative current paths in the middle NPC part of the topology. Thus, outer symmetrical
switches Sx1 and Sx4 of ANPC topology are less stressed with total losses, comparing with
NPC one. In addition, Table 11 shows that NPC components are significantly stressed due
to the lack of alternative paths for both negative and positive load current during all the
77
operation cycle, as it has already discussed in theory in Chapter 1.2.1. Therefore, additional
active switches in NPC point of ANPC inverter share the losses creating alternative ways
for current flow, since the inner and NPC semiconductors are unloaded to certain extent in
ANPC application.
For the same simulation conditions, the following total power loss calculation results are
presented in Table 12 for NPC and ANPC models.
Table 13. General loss distribution and efficiency of NPC and ANPC inverter models.
Loss type NPC ANPC
IGBTs conduction losses [kW] 16.95 16.95
Diodes conduction losses [kW] 1.89 1.89
Total conduction losses [kW] 18.84 18.84
IGBTs switching losses[kW] 2.2 2.14
Diodes switching losses[kW] 0.97 0.98
Total switching losses[kW] 3.17 3.12
Total loss dissipation [kW] 22.01 21.96
Efficiency, % 98 98
Conditions: Eupec 3.3kV IGBT-module from Appendix 1 for ϑ=125°C, UDC=2.8kV,
Iph=1.2kA, fsw=1.8kHz, m=0.866, PF≈1.
The obtained results show that conduction losses share significant part of total losses for
both topologies, and the most stressed devices are active IGBT switches, whereas
conduction and switching losses of free-wheeling diodes share less of total loss dissipation
for chosen simulation conditions. Furthermore, the conduction losses are equal, as the one
direction current flow is always provided by two components for both topologies. The
switching losses are mostly affected by utilized PWM method and switching frequency,
however the difference in their values between inverters is not significant either. In
addition, the total loss dissipations are approximately the same for NPC and ANPC
inverters, so, as it has been already mentioned previously, the aim of implementation of the
Simulation model
78
ANPC is not to save total inverter losses, but distribute them evenly between the
components.
It should be mentioned that obtained results can be affected by some reasons, for instance
rough approximations and assumptions during the modelling and calculations. In addition,
the system with ANPC model is simulated with just ordinal sequences of NPC base
alternative vectors, whereas quite fair results can be obtained only with integration of
thermal behaviour of the inverter.
79
5 SUMMARY AND CONCLUSIONS
As a contribution to previous studies in this thesis the SVM technique to control NPC and
ANPC inverters has been implemented in Matlab/Simulink environment. In addition, the
obtained simulation models have been utilized to investigate the distribution of both
switching and conduction losses between the components of the inverters. The analysis also
includes the calculation of total loss dissipations and efficiencies for both NPC and ANPC
inverters.
During the implementation of ANPC modelling an unequal distribution of power losses of
three-level NPC inverter has been overcome. The improved ANPC inverter model has been
simulated, and, as a result obtained waveforms of output voltages and currents show the
quality performance of the inverter. Thus, harmonic content of output signals correspond to
IEC 61000-4-7 international EMC energy supply quality standard and THD does not
exceed the accepted values. However, a simple model of grid filter can be implemented in
order to improve the model or make it more realistic, as real power converters are usually
include a certain filters in order to protect both the grid from the converter and vice versa.
The methods of calculations has been utilized in simulations are commonly used in
practise, however the assumptions which were accepted during the simulations may
essentially affect the obtained results. In general, obtained results correspond to the
theoretical issues discussed in background theories of the thesis and the similar results can
be found in and (FLORICAU et al 2009). Thus, the most stressed devices of NPC
application have been revealed. Then, extended topology of ANPC has been simulated, in
order to achieve more even distribution between semiconductors, so the losses distribution
and total loss dissipation for the both topologies can be compared. However, it should be
kept in mind that without relevant thermal behaviour model of the inverters the simulations
could be incomplete.
80
Thus, the conduction and switching losses have been calculated for each component of
NPC and ANPC structures. Then, the relations and distribution between conduction and
switching losses among the semiconductors have been also investigated. Also, it has been
shown that the total losses are the same for both structures.
In general, designed models can be characterized as base ones and not flexible enough,
which can be used for different simulations by adding desired modules into them. For
instance, more complex analysis with varying PF values and sophisticated control strategies
can be provided, for instance SHE PWM. Moreover, the increased share of wind power in
total energy production demands more realistic modelling, including fully controlled AC-
DC-AC high power converter models, so not only the inverter model, but rectifier one can
be simulated further.
81
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APPENDIX 1 I(VII)
APPENDIX 1: IGBT-module datasheet
APPENDIX 1 II(VII)
APPENDIX 1 III(VII)
APPENDIX 1 IV(VII)
APPENDIX 1 V(VII)
APPENDIX 1 VI(VII)
APPENDIX 1 VII(VII)
APPENDIX 2 I(I)
Appendix 2: General model of NPC and ANPC inverter block diagrams with SVM control
blocks
1
m
50
f
m
f
Out1
Out2
Out3
Out4
Out5
Out6
Out7
Out8
Out9
Out10
Out11
Out12
SVM
PhaseA
PhaseB
PhaseC
Network_load
In1
In2
In3
In4
In5
In6
In7
In8
In9
In10
In11
In12
PhaseA
PhaseB
PhaseC
3-level NPC Inverter
Discrete,Ts = 5e-006 s.
powergui
1
m
50
f
In1
In2
Out1
Out2
Out3
Out4
Out5
Out6
Out7
Out8
Out9
Out10
Out11
Out12
Out13
Out14
Out15
Out16
Out17
Out18
SVM
PhaseA
PhaseB
PhaseC
Network_load
In1
In2
In3
In4
In5
In6
In7
In8
In9
In10
In11
In12
In13
In14
In15
In16
In17
In18
PhaseA
PhaseB
PhaseC
3-level ANPC Inverter
APPENDIX 3 I(I)
Appendix 3: The compound SVM control module
12
Out12
11
Out11
10
Out10
9
Out9
8
Out8
7
Out7
6
Out6
5
Out5
4
Out4
3
Out3
2
Out2
1
Out1
1/(6*6*50)
Ts
In1
In2
In3
In4
In5
Out1
Out2
Out3
Out4
Out5
Out6
Out7
Out8
Out9
Out10
Out11
Out12
Switching_Control
Pulse
T=Ts/10
reg4_t1
Goto9
reg3_t3
Goto8
reg3_t2
Goto7
reg3_t1
Goto6
reg2_t3
Goto5
reg2_t2
Goto4
reg2_t1
Goto3
reg1_t3
Goto2
reg4_t3
Goto11
reg4_t2
Goto10
reg1_t2
Goto1
reg1_t1
Goto
(3^0.5)/2
Gain
f requency
clock
alpha
sector
Definition of angle and sector
m=0.866
alpha
Region1
Region2
Region3
Region4
Definition of Region
Ts
m
alpha
reg1_t1
reg1_t2
reg1_t3
reg2_t1
reg2_t2
reg2_t3
reg3_t1
reg3_t2
reg3_t3
reg4_t1
reg4_t2
reg4_t3
Conducting_Time_Calculator
2
f
1
m
APPENDIX 4 I(I)
Appendix 4: ‘Definition_of_angle_and_sector’ block diagram
Num_vectors
2
sector
1
alpha
0
zero
10
scale_koeff
1/10
scale-koeff
1
increase1
60
degrees_in_sector
floor
Rounding
Function
==
Relational
Operator3
==
Relational
Operator1
>=
Relational
Operator
Product
6
Num_of_sectors
1
u
Math
Function1
1
u
Math
Function
pi/180
Gain2
1/6
Gain
double
double
Count
Up
Inc
Rst
Cnt
Hit
Counter1
Count
Up
Inc
Rst
Cnt
Hit
Counter
50*36
1/Ts
2
clock
1
frequency
APPENDIX 5 I(I)
Appendix 5: ‘Definition_of_Region’ block diagram
m2
4
Region4
3
Region3
2
Region2
1
Region1
sin
Trigonometric
Function2
cos
Trigonometric
Function1
sin
Trigonometric
Function
In1 Out1
Triggered
Subsystem
Scope2
==
<
<
<=
<=
>
>
>
<=
Pulse
T=Ts
Product1
Product
AND
OR
NOT
AND
AND
2/sqrt(3)
Gain1
1/sqrt(3)
Gain
3^0.5/2
Constant4
0.5
Constant3
0.5
Constant2
0.5
Constant1
0.5
Constant
2
alpha
1
m=0.866
m1
APPENDIX 6 I(I)
Appendix 6: ‘Conducting_Time_Calculator’ block diagram
alpha
m
Ts
12
reg4_t3
11
reg4_t2
10
reg4_t1
9
reg3_t3
8
reg3_t2
7
reg3_t1
6
reg2_t3
5
reg2_t2
4
reg2_t1
3
reg1_t3
2
reg1_t2
1
reg1_t1
sin
Trigonometric
Function9
sin
Trigonometric
Function8
sin
Trigonometric
Function7
sin
Trigonometric
Function6
sin
Trigonometric
Function5
sin
Trigonometric
Function4
sin
Trigonometric
Function3
sin
Trigonometric
Function2
sin
Trigonometric
Function1
In1 Out1
Triggered
Subsystem
Pulse
T=Ts
Product9
Product8
Product7
Product6
Product5
Product4
Product3
Product2
Product15
Product14
Product13
Product12
Product11
Product10
Product1
Product
2
Gain9
-2
Gain8
-2
Gain7
2
Gain6
2
Gain5-1
Gain4
2
Gain3
2
Gain2
2
Gain11
-1
Gain10
-2
Gain1
Dead Zone9
Dead Zone8
Dead Zone7
Dead Zone6
Dead Zone5
Dead Zone4
Dead Zone3
Dead Zone2
Dead Zone11
Dead Zone10
Dead Zone1
Dead Zone
1
Constant9
pi/3
Constant8
pi/3
Constant7
1
Constant6
pi/3
Constant5
1
Constant4
pi/3
Constant3
pi/3
Constant2
1
Constant13
pi/3
Constant12
1
Constant11
1
Constant10
1
Constant1
pi/3
Constant
3
alpha
2
m
1
Ts
APPENDIX 7 I(V)
Appendix 7: ‘Switching_Control’ block diagram for NPC inverter and Region2 signal
routing
12
Switch12
11
Switch11
10
Switch10
9
Switch9
8
Switch8
7
Switch7
6
Switch6
5
Switch5
4
Switch4
3
Switch3
2
Switch2
1
Switch1
sector
reg4_state1
reg4_state2
reg4_state3
reg4_state4
Region4
sector
reg3_state1
reg3_state2
reg3_state3
reg3_state4
reg3_state5
Region3
sector
reg2_state1
reg2_state2
reg2_state3
reg2_state4
Region2
sector
reg1_state1
reg1_state2
reg1_state3
reg1_state4
reg1_state5
reg1_state6
reg1_state7
Region1
In1
In2
In3
In4
In5
In6
In7
In8
In9
In10
In11
In12
In13
In14
In15
In16
In17
In18
In19
In20
In21
In22
In23
In24
Switch1
Switch2
Switch3
Switch4
Switch5
Switch6
Switch7
Switch8
Switch9
Switch10
Switch11
Switch12
Final_Logic
reg4_state1
reg4_state2
reg4_state3
reg4_state4
Region4
S1
S2
S3
S4
S5
S6
AND_Mux_block4
reg3_state1
reg3_state2
reg3_state3
reg3_state4
reg3_state5
Region3
S1
S2
S3
S4
S5
S6
AND_Mux_block3
reg2_state1
reg2_state2
reg2_state3
reg2_state4
Region2
S1
S2
S3
S4
S5
S6
AND_Mux_block2
reg1_state1
reg1_state2
reg1_state3
reg1_state4
reg1_state5
reg1_state6
reg1_state7
Region1
S1
S2
S3
S4
S5
S6
AND_Mux_block1
5
In5
4
In4
3
In3
2
In2
1 In1
APPENDIX 7 II(V)
4
reg2_state4
3
reg2_state3
2
reg2_state2
1
reg2_state1
1
2
3
4
5
*, 6
region2_state4
1
2
3
4
5
*, 6
region2_state3
1
2
3
4
5
*, 6
region2_state2
1
2
3
4
5
*, 6
region2_state1
(1 1 1 1 0 0)
PPN1
(1 1 1 1 0 1)
PP0
(1 1 0 0 1 1)
PNP
(1 1 0 0 0 0)
PNN1
(1 1 0 0 0 1)
PN01
(1 1 0 1 1 1)
P0P1
(1 1 0 1 0 0)
P0N
(1 1 0 1 0 1)
P00
(0 0 1 1 1 1)
NPP1
(0 0 1 1 0 0)
NPN1
(0 0 1 1 0 1)
NP0
(0 0 0 0 1 1)
NNP1
(0 0 0 0 0 1)
NN01
(0 0 0 1 1 1)
N0P
(0 0 0 1 0 0)
N0N1
(0 0 0 1 0 1)
N00
(0 1 1 1 1 1)
0PP1
(0 1 1 1 0 0)
0PN1
(0 1 1 1 0 1)
0P0
(0 1 0 0 1 1)
0NP
(0 1 0 0 0 0)
0NN1
(0 1 0 0 0 1)
0N0
(0 1 0 1 1 1)
00P
(0 1 0 1 0 0)
00N
1
sector
APPENDIX 7 III(V)
6
S6
5
S5
4
S4
3
S3
2
S2
1
S1
ramp
t3
t1/2
t2
t1/2_f
t1/2_s
t3F
t2F
Switching sequence Reg2
In1
In2
In3
In4
In5
In6
In7
Out1
Out2
Out3
Out4
Out5
Out6
Subsystem3
In1
In2
In3
In4
In5
In6
In7
Out1
Out2
Out3
Out4
Out5
Out6
Subsystem2
In1
In2
In3
In4
In5
In6
In7
Out1
Out2
Out3
Out4
Out5
Out6
Subsystem1
In1
In2
In3
In4
In5
In6
In7
Out1
Out2
Out3
Out4
Out5
Out6
Subsystem
Pulse
T=Ts
AND
Logical
Operator9
AND
Logical
Operator8
AND
Logical
Operator7
AND
Logical
Operator6
OR
Logical
Operator5
OR
Logical
Operator4
OR
Logical
Operator3
OR
Logical
Operator2
AND
Logical
Operator11
AND
Logical
Operator10
OR
Logical
Operator1
OR
Logical
Operator
1/2
Gain6
reg2_t2
From2
reg2_t3
From1
reg2_t3
From
5
Region2
4
reg2_state4
3
reg2_state3
2
reg2_state2
1
reg2_state1
APPENDIX 7 IV(V)
Forming signals for lower part of NPC topology IGBTs
12
Switch12
11
Switch11
10
Switch10
9
Switch9
8
Switch8
7
Switch7
6
Switch6
5
Switch5
4
Switch4
3
Switch3
2
Switch2
1
Switch1
OR
S6
OR
S5
OR
S4
OR
S3
OR
S2
OR
S1
NOT
Logical
Operator5
NOT
Logical
Operator4
NOT
Logical
Operator3
NOT
Logical
Operator2
NOT
Logical
Operator1
NOT
Logical
Operator
24
In24
23
In23
22
In22
21
In21
20
In20
19
In19
18
In18
17
In17
16
In16
15
In15
14
In14
13
In13
12
In12
11
In11
10
In10
9
In9
8
In8
7
In7
6
In6
5
In5
4
In4
3
In3
2
In2
1
In1
APPENDIX 7 V(V)
‘Switching_Sequence’ for region 2
4
t2F
3
t3F
2
t1/2_s
1
t1/2_f
ScopeAND
ANDAND
NOT
ANDAND
NOT
NOT
In_t
rampOut_t
Form_imp7
In_t
rampOut_t
Form_imp6
In_t
rampOut_t
Form_imp5
In_t
rampOut_t
Form_imp1
4
t2
3
t1/2
2
t3
1
ramp
APPENDIX 8 I(II)
Appendix 8: Three-level NPC and ANPC inverter models with measurement blocks
3
PhaseC
2
PhaseB
1
PhaseA
g CE
S34
g CE
S33
g CE
S32
g CE
S31
g CE
S24
g CE
S23
g CE
S22
g CE
S21
g CE
S14
g CE
S13
g CE
S12
g CE
S11
Is4
Goto9
Is3
Goto8
Is2
Goto7
Is1
Goto6
Id02
Goto5
Id01
Goto4
Id4
Goto3
Id3
Goto2
Cs4
Goto13
Cs3
Goto12
Cs2
Goto11
Cs1
Goto10
Id2
Goto1
Id1
Goto
DC Voltage Source1
DC Voltage Source
D34
D33
D32
D31
D24
D23
D22
D21
D14
D13
D12
D11
D06
D05
D04
D03
D02
D01
i+
-
Cd4
i+
-
Cd3
i+
-Cd2
i+
-
Cd1
i+
-
Cd02
i+
-
Cd01
i+
-
CS4
i+
-
CS2
i+
-
CS1i
+-
C
12
In12
11
In11
10
In10
9
In9
8
In8
7
In7
6
In6
5
In5
4
In4
3
In3
2
In2
1
In1
APPENDIX 8 II(II)
3
PhaseC
2
PhaseB
1
PhaseA
Scope
g CE
S36
g CE
S35
g CE
S34
g CE
S33
g CE
S32
g CE
S31
g CE
S26
g CE
S25
g CE
S24
g CE
S23
g CE
S22
g CE
S21
g CE
S16
g CE
S15
g CE
S14
g CE
S13
g CE
S12
g CE
S11
i+
-
Is6
i+
-
Is5
i+
-
Is4
i+
-
Is3
i+
-
Is2
i+
-
Is1
i+
-
Id4
i+
-
Id3
i+
-
Id2
i+
-
Id1
i+
-
Id02
i+
-
Id01
Id4
Goto9
Id3
Goto8
Id2
Goto7
Id1
Goto6
Is6
Goto5
Is5
Goto4
Is4
Goto3
Is3
Goto2
CS6
Goto17
CS5
Goto16
CS4
Goto15
CS3
Goto14
CS2
Goto13
CS1
Goto12
Id5
Goto11
Id6
Goto10
Is2
Goto1
Is1
Goto
DC Voltage Source1
DC Voltage Source
D34
D33
D32
D31
D24
D23
D22
D21
D14
D13
D12
D11
D06
D05
D04
D03
D02
D01
18
In18
17
In17
16
In16
15
In15
14
In14
13
In13
12
In12
11
In11
10
In10
9
In9
8
In8
7
In7
6
In6
5
In5
4
In4
3
In3
2
In2
1
In1
APPENDIX 9 I(I)
Appendix 9: m-file with simulation parameters and base vectors arrays declaration for
NPC and ANPC models
clc; clear all; % Switching states for one phase a...f=[s1 s2 s3 s4 s5 s6]. % States a and f give fully positive and negative voltages for one phase, % respectively, and create paths for positive and negative currents, % whereas states b,c,d and e create alternative paths for current flow % in the middle point of ANPC topology.
a=[1 1 0 0 0 1]; b=[0 1 0 0 1 0]; c=[0 1 0 1 1 0]; d=[1 0 1 0 0 1]; e=[0 0 1 0 0 1]; f=[0 0 1 1 1 0];
% Parameters of the model and load m=3; % number of phases init_t=1e-9; %losses calculation Cur_rise_tol=4; %assumptions A_Cur_rise_tol=20; Time_sat_limit=2e-5; Tf=1/50; % Fundamental period [s] Tsw=1/(50*36); % Switching period [s] tolerance=0; % min pulse length [s] Udc=2.8e+3; % DC-link voltage [V] Rload=1; % Load resistance [Ohm] Lload=2e-3; % Load inductance [H]
% Parameters of IGBTs and diodes used in calculation model Tail_time=0.0000002; % Rise time [s] Fall_time=0.0000002; % Fall time [s] RGin=0.42; Ldcl=0; uCEO=1.9; % IGBT threshold voltage [V] rC=0.002; % IGBT on-state resistance [Ohm] uDO=1.4; % Diode threshold voltage [V] rD=0.0023; % Diode on-state resistance [Ohm] Irated=1200; % Rated current from the datasheet [A] Urated=1650; % Rated voltage from the datasheet[V] Eon=2.2; % Turn-on energy loss [J] Eoff=1.55; % Turn-off energy loss [J] Erec=1.55; % Recovery energy loss [J]
sim('ANPC_final.mdl'); sim('NPC_final.mdl');
APPENDIX 10 I(I)
Appendix 10: Currents of symmetrical components Sx1, Sx4 and Sx2, Sx3 simultaneously
conducting Dx1 and Dx2 for NPC inverter.