lad[31:0] 32 mbd[127:0] 128 mux pci r reg pci w reg mb r reg mb w reg mb r/w reg pci r/w reg pci r...
DESCRIPTION
Memory Base AddressOffsetTypeWidth (bits)Depth (Words)accesses Local bus Function I/O Control Register LBA 0 0x0000Register NoneR/W Magic Bus Width (bits)Depth (Words)accesses 10 b1 PCI Translation Base LBA 0 0x0010Register NoneR/W16 b1 MBus Upper Memory Address LBA 0 0x0014Register NoneR/W16 b1 MBus Lower Memory Address LBA 0 0x0018Register NoneR/W16 b1 MBus Translation Base LBA 0 0x001CRegister NoneR/W16 b1 MBus Error Register LBA 0 0x0020Register NoneR/W16 b1 Group I/O Control PIO Configuration TSI Registers Mapper Registers 0x010CBroadcast Status RegisterRegister LBA 0 NoneR32 b1 0x0110Crate Master RegisterRegister LBA 0 NoneR/W32 b1 0x0114 Internal Control Register Register LBA 0 NoneR/W32 b1 0x0134Internal Request RegisterRegister LBA 0 NoneR32 b1 0x013CInternal Test RegisterRegister LBA 0 NoneR/W32 b1 0x0140User Output RegisterRegister LBA 0 NoneR/W8 b1 0x0144 User Input Register Register LBA 0 NoneR8 b1 0x0148 Geographic Address Register Register LBA 0 NoneR32 b1 0x1000 Mapper Array RAM LBA 0 NoneR/W32 b Data storage Address FIFO Data FIFOFIFO 128 b 10 b 0x1000 W W 32 b 10 b 0x4000 0x1000 R R LBA 0 PIO Transfers PIO PCI to MB register win A/B?LBA 1/2RegisterRW128 b32 b11 0x400 ? ? 0x0130 Scaler Register Register LBA 0 NoneR/W32 b1 PIO MB to PCI register?LBA 1RegisterWR128 b32 b11TRANSCRIPT
![Page 1: LAD[31:0] 32 MBD[127:0] 128 Mux PCI R Reg PCI W Reg MB R Reg MB W Reg MB R/W Reg PCI R/W Reg PCI R /MB R Reg PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB](https://reader036.vdocuments.mx/reader036/viewer/2022081808/5a4d1b227f8b9ab059995b46/html5/thumbnails/1.jpg)
LAD[31:0]32
MBD[127:0]128
Mux
MuxMux
PCI R Reg
PCI W Reg
MB R Reg
MB W Reg
MB R/W Reg
PCI R/W Reg
PCI R /MB R Reg
PCI R /MB W Reg
PCI R /MB R/W Reg
PCI W /MB R Reg
PCI W /MB W Reg
PCI W /MB R/W Reg
PCI R/W /MB R Reg
PCI R/W /MB W Reg
PCI R/W /MB R/W Reg
Mux
Mux
Mux
General Interconnection design
![Page 2: LAD[31:0] 32 MBD[127:0] 128 Mux PCI R Reg PCI W Reg MB R Reg MB W Reg MB R/W Reg PCI R/W Reg PCI R /MB R Reg PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB](https://reader036.vdocuments.mx/reader036/viewer/2022081808/5a4d1b227f8b9ab059995b46/html5/thumbnails/2.jpg)
LAD[31:0]32
MBD[127:0]128
128
Mux
32
32
8
8
32
32
32
32
32
128
32
16
16
16
16
10
16
10
128
32
I/O Control Register
PCI Translation Base
MBus Upper Memory Address
MBus Lower Memory Address
MBus Translation Base
MBus Error Register
Broadcast Status Register
Crate Master Register
Internal Control Register
Internal Request Register
Internal Test Register
User Output Register
User Input Register
Geographic Address Register
Mapper Array
Address FIFO
Data FIFO
PIO PCI to MB register
PIO MB to PCI register
Data Busses
PCI In Address Register32
PCI Out Address Register 32
![Page 3: LAD[31:0] 32 MBD[127:0] 128 Mux PCI R Reg PCI W Reg MB R Reg MB W Reg MB R/W Reg PCI R/W Reg PCI R /MB R Reg PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB](https://reader036.vdocuments.mx/reader036/viewer/2022081808/5a4d1b227f8b9ab059995b46/html5/thumbnails/3.jpg)
Memory
Base AddressOffset Type Width (bits) Depth (Words) accesses
Local bus
Function
I/O Control Register LBA 00x0000 Register None R/W
Magic Bus
Width (bits) Depth (Words) accesses
10 b 1
PCI Translation Base LBA 00x0010 Register None R/W16 b 1
MBus Upper Memory Address LBA 00x0014 Register None R/W16 b 1
MBus Lower Memory Address LBA 00x0018 Register None R/W16 b 1
MBus Translation Base LBA 00x001C Register None R/W16 b 1
MBus Error Register LBA 00x0020 Register
None R/W16 b 1
Group
I/O Control
PIO Configuration
TSI Registers
Mapper Registers
0x010CBroadcast Status Register Register LBA 0None R32 b 1
0x0110Crate Master Register Register LBA 0None R/W32 b 1
0x0114
Internal Control Register
Register LBA 0None R/W32 b 1
0x0134Internal Request Register Register LBA 0None R32 b 1
0x013CInternal Test Register Register LBA 0None R/W32 b 1
0x0140User Output Register Register LBA 0None R/W8 b 1
0x0144User Input Register Register LBA 0None R8 b 1
0x0148Geographic Address Register Register LBA 0None R32 b 1
0x1000Mapper Array RAM LBA 0None R/W32 b
Data storageAddress FIFO
Data FIFO FIFO
FIFO
128 b
10 b
0x1000
0x1000
W
W
32 b
10 b
0x4000
0x1000
R
R
LBA 0
LBA 0
PIO TransfersPIO PCI to MB register win A/B ? LBA 1/2Register R W128 b 32 b 11
0x400
?
?
0x0130
Scaler Register
Register LBA 0None R/W32 b 1
PIO MB to PCI register ? LBA 1Register
W R128 b 32 b 11
![Page 4: LAD[31:0] 32 MBD[127:0] 128 Mux PCI R Reg PCI W Reg MB R Reg MB W Reg MB R/W Reg PCI R/W Reg PCI R /MB R Reg PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB](https://reader036.vdocuments.mx/reader036/viewer/2022081808/5a4d1b227f8b9ab059995b46/html5/thumbnails/4.jpg)
LAD[31:0]32
MBD[127:0]128
128
32
32
8
8
32
32
32
32
32
128
32
16
16
16
16
10
16
10
128
32
I/O Control Register
PCI Translation Base
MBus Upper Memory Address
MBus Lower Memory Address
MBus Translation Base
MBus Error Register
Broadcast Status Register
Crate Master Register
Internal Control Register
Internal Request Register
Internal Test Register
User Output Register
User Input Register
Geographic Address Register
Mapper Array
Address FIFO
Data FIFO
PIO PCI to MB register
PIO MB to PCI register
Data Busses
PCI In Address Register32
PCI Out Address Register 32
32 Scaler Register
32
![Page 5: LAD[31:0] 32 MBD[127:0] 128 Mux PCI R Reg PCI W Reg MB R Reg MB W Reg MB R/W Reg PCI R/W Reg PCI R /MB R Reg PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB](https://reader036.vdocuments.mx/reader036/viewer/2022081808/5a4d1b227f8b9ab059995b46/html5/thumbnails/5.jpg)
fifo_fullfifo_emptydma_accessecl_accesspci_accessmb_accessplx_accessvme_accessvme_activitymb_clk_ingmb_clk_inpci_clk_ingpci_clk_in
n_vme_rst_inn_sw_rst_offn_sw_rst_on
n_vme_rst_out
n_led_reset
alen_bigendn_blastbreqi
n_ads
n_dendmpaf_eotdp<3..0>
breqon_bterm
lad<31..0>n_lbe<3..0>lholdlholda
n_readyn_waitn_linto
n_lw_rn_lserr
n_dt_r
n_ccslclkn_linti
n_dack<1..0>n_dreq<1..0>
n_lb_resetuseri_llockiusero_llockopmereq
mba<31..0>mod_done<18..0>ev_loaded<3..0>n_bossreq
bossgrinn_bossoutbossgrout
n_dstroben_bossin
doneoutn_ddoneoutn_rd_wrn_startload
n_bufout1n_bufout0fifoemptyin
n_bufin1n_bufin0
n_ddonein
n_resetoutn_mbmastern_crmaster
n_fifoemptyoutn_resetin
n_mbenn_mbdatdirn_mbadddir
mbd<127..0>
vbddonel2_answer_readyext_tsi_int_reqj2_resv_out<7..0>
n_ga<4..0>test_out<3..0>
j2_resv_in<7..0>n_gap
test_pt<31..0>tsi_out<31..0>
vbd_start_req
XCV405EDISPLAY
CLOCK
RESET
LOCAL BUS
MAGIC BUS
TSI
TEST POINTS
![Page 6: LAD[31:0] 32 MBD[127:0] 128 Mux PCI R Reg PCI W Reg MB R Reg MB W Reg MB R/W Reg PCI R/W Reg PCI R /MB R Reg PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB](https://reader036.vdocuments.mx/reader036/viewer/2022081808/5a4d1b227f8b9ab059995b46/html5/thumbnails/6.jpg)
mb_clk_ingmb_clk_inpci_clk_ingpci_clk_in
alen_bigendn_blastbreqi
n_ads
n_dendmpaf_eotdp<3..0>
breqon_bterm
lad<31..0>n_lbe<3..0>lholdlholda
n_readyn_waitn_linto
n_lw_rn_lserr
n_dt_r
n_ccslclkn_linti
n_dack<1..0>n_dreq<1..0>
n_lb_resetuseri_llockiusero_llockopmereq
mba<31..0>mod_done<18..0>ev_loaded<3..0>n_bossreq
bossgrinn_bossoutbossgrout
n_dstroben_bossin
doneoutn_ddoneoutn_rd_wrn_startload
n_bufout1n_bufout0fifoemptyin
n_bufin1n_bufin0
n_ddonein
n_resetoutn_mbmastern_crmaster
n_fifoemptyoutn_resetin
n_mbenn_mbdatdirn_mbadddir
mbd<127..0>
vbddonel2_answer_readyext_tsi_int_reqj2_resv_out<7..0>
n_ga<4..0>test_out<3..0>
j2_resv_in<7..0>n_gap
tsi_out<31..0>
vbd_start_req
XCV405E
LOCAL BUS INTERFACE
Address decoder
State machine
TSI Block
TSI registers
State machine
Address decoder
State machine
MAGIC BUS
PIO Block
PIO registers
State machine
Address translator
Add mapper
Add translator
fifo_fullfifo_emptydma_accessecl_accesspci_accessmb_accessplx_accessvme_accessvme_activity
n_vme_rst_inn_sw_rst_offn_sw_rst_on
n_vme_rst_out
n_led_reset
test_pt<31..0>TEST POINTS
Rst & Display & Clock
Reset management
Display management
Clock management
![Page 7: LAD[31:0] 32 MBD[127:0] 128 Mux PCI R Reg PCI W Reg MB R Reg MB W Reg MB R/W Reg PCI R/W Reg PCI R /MB R Reg PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB](https://reader036.vdocuments.mx/reader036/viewer/2022081808/5a4d1b227f8b9ab059995b46/html5/thumbnails/7.jpg)
LOCAL BUS INTERFACE
Address decoder
State machine
PCI In Address Register
32
PCI Out Address Register
32ale
n_bigendn_blastbreqi
n_ads
n_dendmpaf_eotdp<3..0>
breqon_bterm
lad<31..0>
n_lbe<3..0>lholdlholda
n_readyn_waitn_linto
n_lw_rn_lserr
n_dt_r
n_ccslclkn_linti
n_dack<1..0>n_dreq<1..0>
n_lb_resetuseri_llockiusero_llockopmereq
pci_en_wr_mem_1pci_ en_rd_mem_1pci_ en_buf_mem_1
pci_ en_buf_mem_nCombinatorial
Logics
pci_ en_wrpci_ en_rd
int_pci_mbint_mb_pci
dma_pci_mbdma_pci_mb
data_in<31..0>
data_out<31..0>pci_add_out<31..0>
pci_add_in<31..0>
![Page 8: LAD[31:0] 32 MBD[127:0] 128 Mux PCI R Reg PCI W Reg MB R Reg MB W Reg MB R/W Reg PCI R/W Reg PCI R /MB R Reg PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB](https://reader036.vdocuments.mx/reader036/viewer/2022081808/5a4d1b227f8b9ab059995b46/html5/thumbnails/8.jpg)
Address decoder
State machine
32
32
mb_en_wr_mem_1mb_en_rd_mem_1mb_en_buf_mem_1
mb_en_buf_mem_nCombinatorial
Logics
mb_en_wrmb_en_rd
int_pci_mbint_mb_pci
dma_pci_mbdma_pci_mb
MAGIC BUS INTERFACE
mod_done<18..0>ev_loaded<3..0>n_bossreq
bossgrinn_bossoutbossgrout
n_dstroben_bossin
doneoutn_ddoneoutn_rd_wrn_startload
n_bufout1n_bufout0fifoemptyin
n_bufin1n_bufin0
n_ddonein
n_resetoutn_mbmastern_crmaster
n_fifoemptyoutn_resetin
n_mbenn_mbdatdirn_mbadddir
mbd<127..0>
Magic Bus In Address Register
Magic Bus Out Address Register
mb_add_in<31..0>
data_out<127..0>
mba<31..0>
data_in<127..0>
mb_add_out<31..0>
![Page 9: LAD[31:0] 32 MBD[127:0] 128 Mux PCI R Reg PCI W Reg MB R Reg MB W Reg MB R/W Reg PCI R/W Reg PCI R /MB R Reg PCI R /MB W Reg PCI R /MB R/W Reg PCI W /MB](https://reader036.vdocuments.mx/reader036/viewer/2022081808/5a4d1b227f8b9ab059995b46/html5/thumbnails/9.jpg)
PIO Block
PIO registers
State machine
mb_add_in<31..0>mb_add_out<31..0>
128
32
16
16
16
16
16
10
128
I/O Control Register
PCI Translation Base
MBus Upper Memory Address
MBus Lower Memory Address
MBus Translation Base
MBus Error Register
PIO PCI to MB register
PIO MB to PCI register 32
data_out<127..0>data_in<127..0>
fifoemptyin
pci_en_wr_io_ctrl_regpci_en_rd_io_ctrl_regpci_en_wr_pci_trans_basepci_en_rd_pci_trans_basepci_en_wr_mb_up_mem_addpci_en_rd_mb_up_mem_addpci_en_wr_mb_low_mem_basepci_en_rd_mb_low_mem_basepci_en_rd_mb_err_regpci_en_wr_pci_to_mb_regpci_en_rd_pci_to_mb_reg
pci_en_wr_mb_err_reg
mb_en_wr_pci_to_mb_regmb_en_rd_pci_to_mb_regpci_en_wr_mb_to_pci_regpci_en_rd_mb_to_pci_regmb_en_wr_mb_to_pci_regmb_en_rd_mb_to_pci_reg
pci_add_out<31..0>
pci_add_in<31..0>
Address Translator