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Laboratory Handout

CADENCE DESIGN

ENVIROMENT

Author: Feng Hong

fhong@elec.gla.ac.uk

Department of Electronics and Electrical Engineering

University of Glasgow

Glasgow, G12 8LT

February 2010

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I. Introduction CMOS technology is prevalent in integrated circuit (IC) designs nowadays, due to the wide availability of highly specified, low cost processes. Cadence is a popular industrial design environment that provides designers an all-in-one tool to implement each stage of the IC design and verification flows, as shown in Fig. 1.

The intention of this handout is to introduce new designers to the Cadence design environment, and to describe all the steps for running the Cadence tools at the Department of EE&E in the University of Glasgow. An operational trans-conductance amplifier (OTA) is provided as an example to illustrate the entire design flow. At end of this lab, each designer is expected to implement each step of the example, and will be assessed according to the familiarity of the Cadence design environment and the completeness of designing the example.

Figure 1. Analogue IC design flow and Cadence tools involved.

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II. Setting up your Linux environment 1, Log in to the workstation

The Cadence design environment of this lab is a Linux-based software suite. Each workstation in the lab-329 has CentOS version of Linux installed. Each workstation is a terminal to the design environment, which means you can access your saved works by using any of workstations in the lab. Please use your University account username and password to log in.

2, Open a terminal

After logged in, you need to open a terminal to start the Cadence design environment. On the upper left corner of the screen, you can choose: Applications Accessories Terminal, or, right click your mouse on the blank area of the desktop and choose Open Terminal.

3, Configure the system

Cadence design environment requires several application configuration files in order to work properly. All these files are required EACH TIME when you start the environment. At the command prompt, type the following commands:

source /software/synopsys/settings.bash

source /software/cadence/settings.bash

source /software/ncsu/ncsu.sh

4, Start your work using the Cadence Design Environment

Your design is normally stored in a dedicated project folder in the file system. Therefore, firstly, you need to create your own project folder for your design, and change current directory to your folder. To do these, type the following commands:

mkdir your_own_project_name

cd your_own_project_name

“your_own_project_name” is any keyword that you want to choose for your folder.

Note: 1, Try to use any other keyword rather than “your_own_project_name”.

2, You only need to create a project folder when you start a design using a DIFFERENT process technology. For existing designs or a new design using the same process technology, you can simply use the folder you have created before.

Next, there are two files need to be copied to your design folder when you start your design FOR THE FIRST TIME. These two files named “.cdsinit” and “cds.lib” are the initialisation file and the library file of the Cadence, respectively. To do these, type the following commands:

cp /software/ncsu/.cdsinit ./

cp /software/ncsu/cdssetup/cds.lib ./

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Note: 1, Don’t forget the DOT ‘.’ in front of the first file, and NO SPACE is needed.

2, There is a space in front of “./”, which represents your current folder.

3, You only need to copy there two files when creating a NEW design folder using a NEW process technology, for existing designs or a new design using same process technology, DO NOT copy them again as it will overwrite you previous work.

After you have done all the required command lines above and with NO error message, you can start the Cadence environment by typing:

msfb&

in the command terminal. The Cadence Command Interpreter Window (CIW) and Library Manager Window (LMW) should appear after a few seconds (If it takes a long time, please have a look at the FAQs in page 13).

From the CIW menus in Fig. 2, all Cadence main tools and options can be accessed. In the window area, all kind of messages (info, errors, warnings, etc) generated by the different Cadence tools appear. Therefore, it is RECOMMANDED to keep this window on the top, so you can observe any response from the system after your action.

From the LMW in Fig. 3, it can be noted that libraries manage all the designs. Each library contains cells and each cell contains different views. For example, different kinds of amplifiers (common source stage, source follower, differential amplifier, etc) can be stored as different cells in ONE library, named Amplifiers. Each of these amplifier cells has different views, such as schematic, symbol, layout and extracted, to represent the same amplifier under different occasions of usage.

Figure 2. Command Interpreter Window.(CIW)

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Figure 3. Library Manager Window.

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III. Build your first design According to the flow chart in Fig. 1, the first step of beginning a new design is to compose a circuit schematic using the given specifications, which include power, speed, area, gain and so on. In our example, a detailed design (an OTA) is provided, including the circuit topology and parameters of the circuit. However, designers will have to use their own designs instead in reality.

Firstly, a new library should be created to store your design. From Library Manager Window,

a) Select File New Library. A new window appears, shown in Fig. 4(a). b) Enter a library name, e.g., example, and click OK c) Choose “Attach to an existing techfile”, as shown in Fig. 4(b) and click OK. d) Choose “NCSU_TechLib_ami06” at Technology Library, as show in Fig.

4(c) and click OK.

(a) (b)

(c)

Figure 4. Create a new library

Now, a new library named example should appear in the library manager list. This library will use the transistors from the given technology. Next, we create a new cell called OTA in the library example. Cell is a circuit to achieve targeted specifications. It can be an amplifier, an inverter or a test circuit. One Cell can be included into another cell(s).

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From the Library Manager window,

a) Select the library name that you just created, e.g., example b) In library manager window, select File New Cell View… c) Enter a cell name, e.g., OTA in Fig. 5 d) Make sure the Library Name is example, View Name is schematic and Tool

is Composer-Schematic, and click OK. A new blank schematic editor should appears, shown in Fig. 6.

Figure 5. Create a new cell

Figure 6. A new blank schematic editor

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Figure 7. Provided OTA schematic

The next step is to add instances to your schematic. To add a new instance (any component in the Cadence Environment is called instance), press instance button

at left hand side of the window, or press “i” on keyboard when “Cmd:” at the upper left hand corner of the window is empty. Otherwise, press “Esc” on your keyboard to exit any command mode.

Two windows should appear as shown below in Fig. 8.

(a) (b)

Figure 8. Add a new instance.

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In Fig. 8(b), choose NCSU_Analog_Parts as your current library, PMOS and NMOS transistors can be found in P_Transistors and N_Transistors. Resistor, inductor and capacitor can be found in R_L_C. For “Vdd” or “GND” symbols, you can choose Supply_Nets. Voltage and current sources can be found in Voltage_Sources and Current_Sources, respectively.

Note: 1, Single click on any instance you want to add, and single click again on the schematic editing window to add it. Click and Drag will not work.

2, Use “nmos4” and “pmos4” for your NMOS and PMOS transistors. A label of “ami06n” or “ami06p” will appear beside your device if you technology library is properly attached.

The command mode will change to “instance” when you want to add any instance. The mode will shown at the upper left corner of the window. Press cancel in Fig. 8(a) or press Esc on the keyboard to quit “instance mode” after you finished adding all the instances.

Figure 9. Property editing window.

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There are six PMOS and four NMOS transistors needed to add. The parameters of these transistors are:

4 NMOS: W=15µm, L=1.05µm

4 smaller PMOS: W=30µm, L=1.05µm

2 bigger PMOS: W=49.95µm, L=1.05µm.

To change the properties of each instance, select the instance (click on it until it is highlighted) and press the property button on the right hand side of the window, or press “q”, to open the property editor window, as shown below in Fig. 9.

The Fig. 9. illustrates the parameters of one smaller PMOS transitor. There are three parameters can be adjusted in this example: Length, Width and Multiplier. Multipiler represents the number of transistors that have been parallel connected by using only one instance symbol in the schematic. For example, two parallel connected transistors with the size of W and L will be equivlent to one transitor with a size of 2W and L. Therefore, either just adjust W and L to be 30µm and 1.05µm and leave multiplier as 1, or choose W=15µm and L=1.05µm and choose multiplier as 2.

Note: 1, Change multiplier and width to be 1 and 30µm or 2 and 15µm will make no difference in schematic simulation, but it will result a better matching performance during the layout design, as it avoids a “narrow-long” layout and has the “same” W and L with NMOS.

2, Do not change other parameters unless you know why you are doing so.

After you added all the instances and adjusted all the parameters, some of the instances may need to be rotated for a better connecting posistion. To rotate an instance, choose Edit Rotate, or press ‘r’ to obtain the rotate window. Choose one of the options in rotate , sideways and upside down to rotate your instance. Try all of these options to see the differences.

When all the instances are placed in the desired positions, you can start to wire them up. To do so, select Wire (narrorw) button on the left hand side of the window, or press ‘w’ to change command mode to “wire”. Firstly, click on the starting point, then RELEASE the left mouse button, and click on the end point to finish. Press “Esc” to quit “wire mode” after you finish adding the wires.

Pins define the input and output terminals of a circuit. To add a pin, click pin button at the left hand side of the window, or press “p”. Enter a name for the pin and select direction of a pin. In our example, the directions of all the pins except “out” are input.

Save and check (first button on the left hand side) your work after you finished the schematic. On CIW, it will inform you if there is any error or warning in your schematic when you click “save and check”. Any error or warning will be highlighted on schematic. Make sure there is NO warning or error before you proceed the next step.

Next step is to generate a new view for your schematic, called symbol. The reason of doing so is that your cell may be repeatedly used as a block in other circuits, it is better to hide the detail of your schematic to avoid any confusion, and easier to

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observe and understand when used in a vary large and complicated circuits. By using pins and a symbol, a cell can be defined and used as a black box.

To add a symbol view to a circuit, select Design Create Cellview From Cellview. A new window appears as below, Fig. 10, and click OK.

Figure 10. Create a symbol view.

Figure 11(a) shows the default view of the symbol. For an amplifier, it is normally represented by a triangle. So, the drawing tools can be used to modify the default symbol into Fig. 11(b).

Note: 1, RED box defines the boundary of the symbol, therefore CANNOT be deleted, the green lines CAN be deleted and re-shaped to make the symbol as you want.

2, Put the pins (red square dots) ON the boundary.

3, DON’T delete the pins as this will result an error of pin mismatch between schematic and symbol view.

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(a)

(b)

Figure 11. Symbol editing window.

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IV Test your circuit. In order to verify your amplifier, you need to compose a new test. Therefore, a new cell, named OTAsim for example, can be created in the library example, to simulate the functionality. The test schematic is shown blow in Fig. 12.

Figure 12. OTA testing circuit.

The arrangement of the test circuit is a source follower (you can arrange the OTA into other topologies for a test as well). Under a give biasing condition, OTA will give an identical output signal as input, when a compatible load is attached.

Question:1, How to decide the biasing condition?

2, Which feature of the OTA will decide the compatibility of the load?

After the schematic is composed, you can begin to test your circuit by choose Tools Analog Environment. The Virtuoso Analogue Design Environment window should appear, as shown in Fig. 13.

In order to test your schematic, three kinds of commonly used analyses can be applied. AC analysis is normally used to test the frequency response of a circuit. DC analysis normally tests the DC working point and behaviour of the circuit. Transient analysis gives a time-based analysis, which is similar to the observation from an oscilloscope.

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In this example, a transient analysis is selected by Analysis Choose, or press the second button on the right hand side, then choose a proper the start time, stop time and step (because computer simulations are based on discrete numerical computations, the step value will determine the number of points for a wave form).

Figure 13. Virtuoso Analog Design Environment.

Choose Output To be plotted Select from schematic to pick up the signals to be observed by clicking on the node wire. Then, chooses Simulation Run or press the “green light” button on the right hand side of the window to run the simulation. The simulation results should be similar as in Fig. 14.

FAQ: 1, Why the CIW says “* Error * Failed to get the MPS handle” after I run the simulation?

Because one of the waveform tools hasn’t been installed on the workstation. Choose Session Options, and choose AWD as your waveform tool and click OK. Run the simulation again, then the waveform should be properly displayed.

2, Why CIW says the simulation is unsuccessful?

Choose Simulation Output Log to see the reason. If it says that the HSPICE hasn’t been checked out, then it is the simulator license problem. Otherwise, ask demonstrator for help.

3, Why it takes a long time for me to start the Cadence environment after I typed “msfb&” or my precious work can only be opened as read-only mode?

It may because you have typed “msfb&” more than once，or the Cadence hasn’t been quit properly at the last time.

a) Type “ps -e” in the terminal window to see all the processes running in the system, then type “kill xxxx”, where XXXX represents the process ID (PID) of msfb, to terminate all existing Cadence processes.

b) Go to your home folder from Linux menu bar, and delete all files with extension name of “.cdslck” in your home folder, your own project folder and its sub folders.

c) In the terminal, type “msfb&” again under your own folder to start the Cadence again.

“.cdslck” file is a temp file to store current status of the Cadence environment. It will be deleted automatically when Cadence is properly quitted. If not, “.cdslck” file will be leaved in the working folder to represent the Cadence is still running. This will lead to a conflict with a new Cadence process.

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(a)

(b)

Figure 14. Simulation output waveforms.

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V. Layout your circuit. The creation of the layout masks is one of the most important steps in the full-custom (bottom-up) design flow, where the designer describes the detailed geometry and the relative positioning of each mask layer to be used in actual fabrication, using Virtuoso Layout Editor. Layout design is very tightly linked to overall circuit performances (area, speed, accuracy and power dissipation), as the physical structures determine the trans-conductance of the transistors, the parasitic capacitances and resistances, and obviously, the silicon area that is used to realise a certain function. The physical (mask layout) design is an iterative process, which starts with the circuit topology and initial sizing of the transistors. It is extremely important that the layout design must not violate any of the Layout Design Rules of the fabrication process, in order to ensure a high probability of defect-free fabrication of all features described in the mask layout.

The detailed mask layout requires a very intensive and time-consuming design effort, so that automated tools are employed as much as possible. Typically, the design of digital circuits based on single-clock synchronous logic is completely automated. First, a circuit description (typically in a hardware description language (HDL) as VHDL or Verilog) is synthesized, leading to a gate-level circuit description. From this gate-level netlist, Place & Route programs generate automatically the layout. However, analogy circuit designs are very sensitive to the layout style, so that an automated procedure is normally difficult to implement. Usually a tedious, full-custom approach is followed, where the designer builds manually the layout, basically drawing rectangles of different layers.

After finished the layout design, it is also important to Extract the netlist underlying the layout view, for two main purposes:

a) This allows comparing it with the netlist extracted from the schematic. This Layout versus Schematic (LVS) comparison ensures that the layout actually implements the required functionalities.

b) If the extraction program also allows extracting parasitic capacitance and resistance from the layout view, a more accurate, Post-Layout Simulation, can be preformed taking into account the geometry of the circuit.

We will now create the layout view of the OTA example by using Virtuoso XL. After opened the schematic view of the OTA in the library manager, you can click on Tools Design Synthesis Layout XL to create a new layout view or opening an existing one, as shown in Fig. 15.

Figure 15. Opening Layout XL.

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(a) (b)

Figure 16. (a) Create a new layout view; (b) Open an existing layout view

To create a new layout view, Fig. 16(a) will appear. Make sure the Library Name and Cell Name are correct, and View Name is layout and Tool is Virtuoso.

To open an exiting layout view of a cell, Fig. 16(b) will appear. You still need to make sure Library, Cell and View names before click OK.

A Virtuoso Layout Editor window with a Layer Selection Window (LSW) should appear side by side with the schematic window, as shown in Fig. 17, if you are creating a new layout view. Otherwise, you existing layout view will be opened.

(a) LSW (b) Virtuoso Layout Editor

Figure 17.

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Because Layout XL automatically recognises all transistors and their connectivity, you can add the layout of a transistor by selecting Create Pick up from schematic, the command mode of layout window on the right hand corner should become “PickNCreate” and a new window should appear as shown in Fig. 18. You can either click on any transistor in the schematic window and click again in the layout window to add it, or click “Unplaced” button in Fig. 18 and select unplaced instances to add them at the same time, all of which will appear at the same position as they are in the schematic window. Click Cancel button or Esc from keyboard to finish adding a component.

Figure 18. Pick from Schematic.

It is noted that each layout instance is “linked” with its corresponding instance in the schematic window. By clicking one, the other will be highlighted accordingly. The suggested connection is indicated as well, when you are dragging a transistor. To view the contents of the instances, press “Shift + f”, to view only the bounding boxes again, press “Ctrl +f”.

Figure 19. Two ways of adding a NMOS transistor.

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Note: 1, CMOS transistors are symmetric devices, which means where is the source or drain of a transistor totally depends how the active region is connected. The indications that you have got when you are dragging a transistor are normally suggestions. You don’t HAVE TO follow them. They can be wrong occasionally.

2, DO NOT open a layout view by double clicking it from library manager, as it will lose the connections between the schematic view and layout view for all transistors.

Each transistor picked up from schematic is a “package” of multiple layers, as shown in left hand side of Fig. 19. Layers of n-select, n-active, poly, metal-1 and contact compose an NMOS transistor. On the right hand side, the second way of adding an NMOS is illustrated by drawing each layers using Rectangle tool and overlapping them accordingly. Precisely controlled dimensions for each layer and positioning of each devices can be achieved by using Ruler tool. To create a ruler, click Window Create Ruler or press “k” on the keyboard. To delete all the ruler makers afterward, click Window Clear all Rulers or press “Shift + k”.

FAQ: 1, Why my PMOS is longer than it longer than it is shown in the handout example?

Because in the handout, each of PMOS transistors is divided into two half-sized ones, and parallel connect them to achieve a better matching performance. To do this, a) delete the PMOS you have added in layout, b) in schematic window, change the width of your transistor to half the size and the multiplier to 2, c) add them again to the layout. You will get twice the number of PMOS when you verify your layout using LVS later on. The wider ones will have their DRAIN sheared (or Source? Why?).

2, What does each layer represent in Fig. 17(a)?

a) The black area in layout editor represents p-type substrate, b) Nwell are nactive are N-type material, c) Nselect is the boundary of ion implant and nactive should be designed inside nselect, d) These also apply to P-type as well. e) Another three layer needed in this lab are poly, metal1 and metal2, f) Different layer is on different “height” on top of the silicon surface, therefore, same layer will be regarded as “connected” if two rectangle boxes are “touched” or overlapped.

Figure 20. Connect gates of two PMOS transistors.

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Figure 21. Create a contact.

After adding all the transistors into the layout view with correct sizes, they should be placed and wired up according to the schematic. Here is how:

a) To connect two or more nodes, which are using the SAME mask layer, you can draw a “properly sized” rectangle box using the same layer in LSW, and make them all “touched” with each other, as illustrated in Fig. 20 (The highlighted part is the joint box using poly). Overlap is allowed but not compulsory.

b) To connect two nodes, which are using different mask layers, metal-1 layer is always required. To connect an active layer or poly to metal-1: 1) draw a metal-1 rectangle box on top of active area or poly, 2) add a contact on top the overlap area of theses two layers by clicking Create Contact. A create contact window will appear as shown in Fig. 21, choose proper Contact Type, and Rows or Columns if an array of contact is required. If two active areas are required to be connected, you can use metal-1 to connect them.

c) One special case is that if two NMOS or PMOS have their source connected, for example a differential pair or a current mirror, you can make a connection by overlapping one of their active areas.

d) If more than one PMOS have their bulks connected, they can be placed in a big nwell. To define the potential of a n-well (bulk of PMOS), you can a) extend the n-well by adding an extra rectangle box using nwell layer, b) place an nselect layer with nactive inside, c) place a layer of metal-1 on the top, d) add a contact on top of them. (What about the bulks of NMOS transistors?)

e) Note, the size of nwell, nselect, nactive and metal-1 should be equivalent or lager than corresponding size of the contact. It also applies for P-type material as well.

As mentioned before, for the same circuit schematic, its layout can be different among designers. If the layout can pass the Design Rule Check (DRC), Layout vs. Schematic (LVS) and Post-layout simulation, it can be regarded as a “correct” one, even if it looks significantly different from another “correct” one. However, this does not mean that you can arbitrarily place your layout. There are certain rules to distinguish one layout from good to bad. Figs. 17 & 18 give an example layout implementation for the OTA.

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Some general rules during layout design:

1, Use less layer of metals as possible and try to avoid metal layers’ cross over. (Why?)

2, Don’t orthogonally place the transistors, keep all the gates in one direction.

3, Use more than one contact to connect active region with metal layer if possible. (Why?)

4, Keep the area as small and square as possible.

5, Use wider metal layer for the power wires, such as VDD or GND. (Why?)

Figure 17. An example layout implementation of the OTA.

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(a) (b)

(c) (d)

Figure 18. An example layout implementation of the OTA (Zoomed in to each part).

During layout editing, it is RECOMMENDED to check the layout against design rules using DRC check REGULARLY by selecting Verify DRC. Results can be observed from CIW window after clicking OK in Fig. 19.

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Figure 19.DRC.

FAQ: 1, There are some errors displayed in CIW after I checked my layout using DRC. Why is not highlighted in the layout? Or I cannot observe the errors that mentioned in CIW in the layout.

Normally, DRC errors are highlighted on the layout view. It is possible that some errors are really small in size and hardly to be observed from certain zoom size. All the errors are highlighted using white markers. Therefore, select “Verify Markers Find” then the following window will appear.

Figure 20.Find Marker.

Select “Zoom to Markers” and click Apply, the layout view will bring you to the errors one by one.

2, Why my transistors or other components cannot be placed in a line? Or there are some errors in CIW that says some “grid” problem?

All the components are placed and aligned using grid control. Choose “Options Display” or press “e” to open Display Options window. On the upper right corner, there is a section called Grid Controls. Choose Type = dots, Minor Spacing = 1, Major Spacing = 5, X Snap Spacing = 0.15, Y Snap Spacing = 0.15, then Click on Apply. The problem should be fixed now. If not, change X and Y Snap Spacing to be 0.05.

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VI. Verify your layout. Finish the entire layout can take a long time for new designers. It is absolutely normal for everyone. However, enthusiasm, patient and carefulness are required for a new designer to become an experienced one. DRC is the best “teacher” to check the entire sizing and spacing mistakes. It is iterative to achieve the task. Once the new layout view passed the DRC check with no error or warning, it is time to verify the connectivity by using LVS check. Your layout will be firstly extracted, which can generate a new netlist from your layout. Then, this new netlist will be compared against the schematic netlist to check if there is any un-matched device or connection.

To extract your layout, click Verify Extract… in Virtuoso editing window of the layout, an extractor window should appear, as shown in Fig. 21(a).

(a)

(b)

Figure 21.Extractor.

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Figure 22.Extracted view.

In Fig. 21(a), select Set Switches to open Set Switches window Fig. 21(b). Select Extract_parasitic_caps and click OK. This will add parasitic capacitances to the extracted layout if there is any metal layer overlapping in the layout. After click OK, a new view named “extracted” should appear in the view list of the library manager. Open this view by double clicking, the extracted view will appear and show all the interconnections, recognised transistors and parasitic capacitances, as shown in Fig. 22 (Highlighted part is VDD).

Figure 23.LVS window.

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The Cadence has transferred the layout as another new netlist. Next step is to compare it with the schematic netlist using LVS. To do so, in the Extracted view window, click Verify LVS, then the LVS window should appear as Fig. 23. Make sure all the information is the same as provided, shown in the figure, and then click Run. In CIW, it should says “LVS job is now started.” After a few seconds, the Analysis job result window, as shown in Fig. 24, should appear and inform you that the analysis job is succeeded.

Figure 24.Extracted result.

Click Output button in Fig. 23, a window should appear and display the result similar as follow:

@(#)$CDS: LVS.exe version 5.1.0 06/20/2007 02:10 (cicln03) $

Command line: /software/cadence/IC5141/tools.lnx86/dfII/bin/32bit/LVS.exe -dir /home/fhong/Study/Cadence/MSc/LVS -l -s -t /home/fhong/Study/Cadence/MSc/LVS/layout /home/fhong/Study/Cadence/MSc/LVS/schematic

Like matching is enabled.

Net swapping is enabled.

Using terminal names as correspondence points.

Net-list summary for /home/fhong/Study/Cadence/MSc/LVS/layout/netlist

count

10 nets

6 terminals

12 pmos

4 nmos

Net-list summary for /home/fhong/Study/Cadence/MSc/LVS/schematic/netlist

count

10 nets

6 terminals

6 pmos

4 nmos

Terminal correspondence points

N5 N4 V+

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N7 N5 V-

N3 N2 ibias

N9 N9 out

N6 N6 vdd

N0 N1 vss

Devices in the netlist but not in the rules:

pcapacitor

Devices in the rules but not in the netlist:

res cap nfet pfet nmos4 pmos4

The net-lists match.

layout schematic

instances

un-matched 0 0

rewired 0 0

size errors 0 0

pruned 0 0

active 16 10

total 16 10

nets

un-matched 0 0

merged 0 0

pruned 0 0

active 10 10

total 10 10

terminals

un-matched 0 0

matched but

different type 0 0

total 6 6

Probe files from /home/fhong/Study/Cadence/MSc/LVS/schematic

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In this file, the number of transistors, nets, and terminals are displayed for schematic view and extracted view. If the number of the nets of extracted view is different from schematic view, it means that you have some connection errors during layout. To find out where is the mistake, click “info” button in Fig. 23, the following window Fig. 25 should appear.

Figure 25.Environment Options setting window.

Click on Netlist from Extracted part, a log file of all the recognised nets and devices from the layout view will be opened. By clicking any part of the components under Extracted View, CIW will display the name of this net. Find the error nets that are displayed in the log file by doing so, and modify them in the Layout View. You need close the LVS windows and Extracted View window to extract your layout again for a new check. If the correct nets and devices are obtained as shown above, you are ready for the post-layout simulation.

FAQ: 1, What should I do if the LVS job is unsucceeded in Fig. 24?

Save all your works and close the Cadence. In your project folder, you need to delete a folder named “LVS” to erase all the old files which may cause conflict. Make sure you are using “msfb&” to open the environment again rather than “icfb&”. Open your extracted view and run LVS again.

2, Do I need to draw the layout for the resistor and capacitor for the “OTAsim” schematic?

No. OTAsim schematic is just used to test the functionality of the OTA schematic netlist and its layout netlist.

Post-layout simulation will use the actual extracted layout netlist with the intrinsic parasitic capacitors for the circuit simulation, rather than using the ideal schematic netlist. Here is how:

a) Open the simulation schematic, as shown in Fig. 12. b) Open the analogue environment, as shown in Fig. 13. c) Choose Setup Environment option, and add extracted at the first place in

Switch View list, as shown in Fig. 26. d) Click OK, and run the simulation same again as before. If you have got the

same result as previous one, congratulations, your design works. Otherwise, go back to layout editor and think about if is there any possible parasitic capacitor could short your circuit in some way, or is there any misconnected against the schematic, etc.

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Figure 26.Environment Options setting window.

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VII. Add pads for your chip Pads are the components that connect your internal pins and metal layer to external terminals. The external terminals will be bonded to the metal pads. Different technology library normally contains its own ready-to-use pad library. For AMI 06, pads can be found from the NCSU_TechLib_ami06 in the Library list, as shown in Fig. 27.

Figure 27 List of Pads in AMI06 TechLib.

As the schematic of these pads are intellectual properties of the foundry, layout view is the only view that can be observed. There are different kinds of pads listed in the library. Here is a summary of the main pads that could be used.

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Pad name Description Padfc Pad Frame Corner. Padgnd Group Pad Padio Input/Output Pad (Analogue Signal) Padnc Pad Spacer with No Connection to Bonding Pad Padout Ouput Pad with Buffer Padspace Padless Spacer without Bonding Pad Padvdd Power Pad Padaref Analogue Reference Pad Padbidir Bi-directional Pad with Buffer Padinc Buffered Input Pad with Complementary Signals (Digital Signal)

To add the pads into your design, you need to make sure that there is NO DRC error or warning in your existing layout. Then, add the pads as new instance in your layout editor. There block views and detailed views are shown in Figs. 28 and 29. You can use “shift + f” and “ctrl + f” to switch between two views.

Note: 1, The pads may introduce lots of DRC errors as they were designed under a slightly different DRC rule. Don’t worry about these errors as long as your design hasn’t introduced any.

2, Different pads use different metal layers for connection (Metal 1 or Metal 2). Please be careful when you connect them.

As there are six pins in the OTA, six corresponding pads are required, respectively. There are “padgnd”, “padout”, “padvdd”, “padref” and two “padio”. Meanwhile, couple of “padfc” and “padspace” are required to complete the entire pad frame.

As shown in Figs. 30 and 31, pads with four frame corners should surround the entire chip. After finished the pad frame with wire connections to the OTA, you are ready to send the design to the foundry.

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Figure 28 Block views of some pads.

Figure 29 Detailed views of some pads.

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Figure 30 Full block view of the entire chip.

Figure 31 Detailed view of the entire chip.

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VIII. Submit your chip to the foundry

There are couple of formats that used for submission of your chip. The formats may vary between foundries. In this handout, we use “gds” format.

From CIW window, Choose “File -> Export-> Stream”. The Virtuoso Stream Out window should appear. Click on Library Browser in the window, navigate to your design and highlight the layout view, the design should be automatically filled in. Close the Library Brower that you just opened and click OK to save your “OTA.gds” file. If you want the file to be stored in some other directory, you can select “Browe…” button behind the Output File option.

This part will not be assessed in your lab exam. Just to enrich your knowledge.

Figure 32 Virtuoso Stream Out window.