CMPEN270 – Digital DesignLab6 – Basic Building Blocks

Penn State Erie, The Behrend College

1 DiscussionThe purpose of this lab is to design, simulate, and implement a decimal digit adder that can be daisy-chained together to form a chain of adders that can add BCD digits. The entity description for the decimal adder is given in listing 1.

entity DecimalAdder isport( cin: in std_logic;

A, B: in std_logic_vector(3 downto 0);errA, errB, cout: out std_logic;sum: out std_logic_vector(3 downto 0));

end DecimalAdder;

Listing 1: The entity description of the decimal adder.

A binary coded decimal (BCD) number is a 4-bit binary number whose value represents a single decimal digit from 0 to 9. So, for example, the BCD code for 610 = 01102. Adding two BCD digits requires a little extra work to insure that the output represents a valid BCD digit. Consider the problem of adding 5+6 shown in Figure 1.

0 1 0 1+ 0 1 1 0

1 0 1 1

Figure 1: The sum of two BCD digits.

In this case the result is a valid binary value, 1110, but an illegal BCD result because the result is out of range. The solution to this problem is to add 6 to the sum of two BCD digits whenever the sum is larger than 9. The sum of two BCD digits generates a carry whenever the sum is larger than 9. Adding 6 to the sum generated in Figure 1 gives us the result in Figure 2.

1 0 1 1+ 0 1 1 0

0 0 0 1

Figure 2: Correcting the sum from Figure 1.

The main function of the decimal adder is to add together two BCD digits A and B and output the corrected sum on its output. If either A or B corresponds to an out-of-range value, like 1100, then the corresponding error output errA or errB should equal 1, otherwise the error outputs should equal 0. The sum output should equal 0 whenever there is an out-of-range input. The cin input allows decimal adders to be daisy-chained together to build a multi-digit BCD adder. Table 1 describes the relationship between the inputs and outputs of the decimal adder.

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cin A B sum cout errA errB0 0-9 0-9 A+B =1 if (A+B)>9 0 01 0-9 0-9 A+B+1 =1 if (A+B+1)>9 0 0x >9 0-9 0 0 1 0x 0-9 >9 0 0 0 1x >9 >9 0 0 1 1

Table 1: The behavior of the DecimalAdder described in Listing 1.

The decimal adder will be built from basic build blocks. A common design error when sketching the datapath for the DecimalAdder is to add the correction factor of 6 to output of the 4-bit adder computing A+B only when the sum is greater than 9. To see why this is a problem let A=9 and B=8. The output of a 4-bit adder in this case will be 0001 with the carry out of 1. If you compare just the output of the adder to 9 then your circuit will not add the needed correcction factor. The carry out bit of the 4-bit adder must somehow be included in your circuit. Another common problem is to mix 4-bit and 5-bit operands as inputs to a component. For example, consider the problem of comparing the output of a 4-bit adder to 16. Since 16 is a 5-bit value, the comparator must be 5-bits wide, however the adder output is 4-bits wide. In this case the concatination operator (page 44 of the Low-Carb VHDL Tutorial) would be used to pad the 4-bit sum with a 5th bit.

Once the decimal adder has been verified to function correctly in a simulation, it will be combined with the hex2seven converter, synthesized, and downloaded onto the PLTD boards.

You will be utilizing basic building blocks to realize the decimal adder circuit. In order to make these basic building blocks as reusable as possible the width of their input arguments must be adjustable. This is accomplished using the generic statement. Listing 2 shows the entity description for an N-bit comparator. That is, each of its inputs is N-bits wide.

entity compare is generic(N: integer := 4); port( x,y : in std_logic_vector(N-1 downto 0);

g,l,e: out std_logic);end compare;

Listing 2: The entity description of a generic comparator.

If you wanted to create a 4-bit instance of this comparator called check that checked if an adder’s output was greater than 9, you include the component instantiation statement show in Listing 3.check: comparator generic map(4) port map (adder_out, constant_9, g, open, open)

Listing 3: An instantiation of the generic comparator given in Listing 2.

You could do this another way. The assignment statement in the definition of the generic means that the default value for N is 4. Consequently, in the instantiation of the check comparator, you could leave the generic map statement off entirely and have the same effect. Thus Listing 4 is equivalent to Listing 3.check: comparator port map (adder_out, constant_9, g, open, open)

Listing 4: An equivalent instantiation statement to Listing 3.

In both cases you would need to define a std_logic_vector called constant_9 which is assigned the value “1001“. The open statement is used whenever an output is unused. It allows the VHDL compiler to optmize the design by removing the logic associated with that output.

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2 Pre-Lab1. Complete the Table 2 describing the behavior of the decimal adder. You will use these values in

the testbench.

cin A B sum cout errA errB0 0000 00000 0011 01011 0011 01011 0011 01101 1000 01100 1000 01101 1001 10010 1100 01101 1000 1110

Table 2: The behavior of the DecimalAdder described in Listing 1.

2. Write an If/then statements for the functioning of the errA and errB signals.3. Write an If/then statement describing the logic to switch the output to 0 if either errA or errB is

asserted.4. Write an If/then statement describing when to add the correction factor to A+B. Make sure that

your circuit can correctly handle inputs like 6+3, 7+6, and 9+8.5. Draw a schematic for DecimalAdder. Make sure that paired data inputs (e.g. data inputs to an

adder) have the same number of bits. Make sure to follow the Schematic Guidelines posted on the class ANGLE page.

6. Go to the testbench folder of Lab6 and write down the entity description for the mux, comparator, and adder.

3 In-labUse Xilinx ISE to write, simulate, and implement the decimal adder onto the PLDT-3 board.

1. Create a new VHDL project called lab6.2. Explicitly copy your hex2seven, generic adder, generic comparator, generic mux, and testbench

into the project directory. Then add them to the lab6 project.3. Create the VHDL file for the decimal adder using the prelab schematics.4. Edit the CORRECT_SUM, CORRECT_ERRA, CORRECT_ERRB, and CORRECT_COUT

entries in the self checking testbench to match the values in Table 2.5. Test and verify the correction operation of the decimal adder using the testbench.6. Create the VHDL DecimalDisp component which combines the DecimalAdd with a hex2seven

converter to display the output.7. Assign the cin to pin 25 and wire it to a push button as shown in Figure 1. Assign A and B to the

dip switches, making sure that the MSB is the left-most switch and the LSB is the right-most switch. Assign sum to one of the 7-segment displays. Assign errA, errB, and cout to individual LEDs.

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Figure 1: The completed Decimal Adder with A=7, B=5, and cin=0.

4 Lab ReportEach team of two students will turn in a single lab report. It should contain the following.

Standard cover page with the following rubric.

Percentage ScoreSchematic 30VHDL 20Timing 30PreLab 20

A proper schematic VHDL code for the body of the DecimalAdder Timing diagram

o Remove “junk” signalso Include all signals in the VHDL code for the Decimal Adder

PreLabs from both students

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